JP2002300029A - Pll circuit and its lock decision circuit, and test method and device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a lock decision circuit for a PLL circuit that accurately detects a locked/unlocked state on the basis of a multiplied signal generated by the PLL circuit. SOLUTION: The lock discrimination circuit is provided with a comparator circuit 23 that compares whether or not a result of count by an up-down counter 24 for counting number of cycles of an output signal over a prescribed cycle period of an input signal X1 of the PLL circuit 10 is coincident with a value (a value of a multiple number latch register 22) depending on a multiple number of the PLL circuit 10 and the prescribed count period, compares whether or not a result of subtraction from the result of count every time the output signal is counted by one cycle over a succeeding count period of the input signal X1 is coincident with zero (a value of a '0' value latch register 21) and outputs a decision signal denoting a lock state when both the comparison results indicate the coincidence.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop (PLL) circuit, and more particularly to a lock detection circuit of a PLL circuit.

[0002]

2. Description of the Related Art As a lock detection circuit of a PLL circuit, for example, a configuration as shown in FIG. 9 has been conventionally known.
FIG. 10 is a timing chart for explaining the operation of the circuit shown in FIG. As the configuration shown in FIG. 9, for example, JP-A-64-24630 is referred to.

Referring to FIG. 9, a phase frequency comparator (Ph
ASE Frequency Comparator (PFC) 101, a charge pump 102 for controlling charging and discharging current to a capacitor (not shown) by an UP signal and a DOWN signal from the phase frequency comparator 101, and a low band for smoothing the voltage of the capacitor A loop filter 103 comprising a pass filter;
A voltage-controlled oscillator 104 which receives the output voltage of the low-pass filter 103 as a control voltage and varies the oscillation frequency;
A frequency divider (1/1) that divides the output of the voltage controlled oscillator 104 by N
N) 105, and the phase frequency comparator 101 compares the phase and frequency of the input signal X1 with the frequency-divided signal from the frequency divider 105. Note that the phase frequency comparator 101 is
Phase Comparator that detects the phase difference between input signals
of course.

A phase frequency comparator 101 outputs an UP signal and a DOWN signal having a pulse width corresponding to the phase difference and the frequency difference between the input signal and the output signal of the frequency divider 105, respectively.
Signal and DOWN signal are exclusive NOR (EXNOR)
The output P of the EXNOR circuit 106
c is the clock input terminal C of the D-type flip-flop 108
K, the signal Pa obtained by delaying the output of the EXNOR circuit 106 by td by the delay circuit 107 is input to the data input terminal D of the D-type flip-flop 108, and the D-type flip-flop 108 A signal sampled at the rising edge is output from the data output terminal Q as a lock determination signal SL. As shown in the timing chart of FIG. 10, when the phase difference is greater than the delay time td, the determination signal SL outputs a low level to indicate an unlocked state.
Since almost no OWN pulse is output, the signal P
When the phase difference is smaller than the delay time td, the determination signal SL outputs a high level.

In the above-described conventional circuit, the locked state is determined using the delay circuit 107 having a delay time of td. For this reason, if the delay time of the delay circuit changes due to ambient temperature, manufacturing variations, or the like, the lock determination criterion also changes, and the locked state / unlocked state cannot be accurately determined. are doing.

In the above-mentioned conventional circuit, P
Instead of monitoring the signal (the input signal and the output signal of the frequency divider) generated by the LL circuit, the UP /
Locking is determined by comparing the logic operation result of the DOWN signal with the delay time, and locking is not determined by directly comparing the input signal to the phase comparator. For this reason, the determination of the locked state is not always accurate, and the above-described circuit cannot be applied to the PLL circuit selection process.

Further, in the above-mentioned conventional circuit,
It is difficult to accurately determine the locked / unlocked state in real time while operating the PLL circuit.

On the other hand, in order to accurately measure the multiplication factor of the output signal of the PLL circuit, it is necessary to directly observe the output of the PLL circuit at its near end with a measuring instrument, which increases the test time. Further, when a test method (waveform observation method) for directly observing the output of the PLL circuit is realized by an LSI tester or the like, constraints due to AC characteristics such as timing accuracy of the LSI tester, skew between pins, and test patterns are accumulated. (For example, when the output signal pattern of the PLL circuit from the unlocked state to the locked state of the PLL circuit is taken into the local memory, an enormous memory capacity may be required) In view of the above, it is difficult to make an accurate determination.

As a publication relating to a technique using a counter for lock determination, a counting period is generated by a counting period generating circuit from an input reference signal, an output signal of a PLL circuit is counted by the counter for the counting period, and the count value is calculated. Unexamined Japanese Patent Application Publication No. 10-3 discloses a phase lock detection circuit for comparison by a comparison circuit
Reference is also made to the description in, for example, Japanese Patent Publication No. 22200.

[0010]

SUMMARY OF THE INVENTION Accordingly, one of the problems to be solved by the present invention is to lock a PLL circuit for accurately detecting a locked / unlocked state based on a multiplied signal generated by the PLL circuit. An object of the present invention is to provide a judgment circuit and a test method and apparatus.

The present invention provides means for solving the above-mentioned problem, and also provides a PLL circuit for controlling a current of a charge pump or the like using a lock detection counter, as will be apparent from the following description. are doing.

[0012]

According to the present invention, there is provided a lock determining circuit for a PLL circuit for outputting an output signal obtained by multiplying the frequency of an input signal by providing a means for solving the above-mentioned problem.
The number of cycles of the output signal is counted over a first counting period determined based on the cycle of the input signal, and the counting result is a first number determined by the multiplication factor of the PLL circuit and the counting period. A first means for comparing whether the output signal is equal to a value, and, based on the counting result, the output signal over a second counting period determined based on a cycle of the input signal after the first counting period. The second means for comparing whether or not the result of subtracting each time is counted for one cycle matches a predetermined second value, and the comparison results of the first and second means both match. And a third means for outputting a determination signal indicating that the lock state is established when the state is indicated.

According to the present invention, there is provided a counter for counting the number of cycles of an output signal of a PLL circuit over a predetermined counting period determined based on a cycle of an input signal of the PLL circuit, and a counter for counting the number of cycles of the output signal. A plurality of coincidence detection circuits that compare bit by bit whether or not they match a value determined from the multiplication number and the counting period; and a plurality of coincidence detection circuits are provided corresponding to the plurality of coincidence detection circuits. Based on the output, activation and deactivation are respectively controlled, and when in an active state, based on a phase comparison detection result of the phase comparator, a plurality of current control circuits for charging and discharging the capacitance, When the output of the match detection circuit indicates a match with the match detection circuit corresponding to any one of the most significant bit to the least significant bit of the count value of the counter The output of the match detection circuit corresponding to the one bit is valid only when all the outputs of the match detection circuit corresponding to the most significant bit and each bit of the higher bits than the one bit indicate a match. A control circuit for performing control, wherein when the coincidence detection circuit corresponding to the most significant bit of the count value of the counter indicates a mismatch state, each of the coincidence detections corresponding to the least significant bit from the most significant bit The current control circuits corresponding to the circuits are all activated, the current value of the charge pump is the maximum value, and the count value of the counter is sequentially from the most significant bit side to the least significant bit side. When the output of the match detection circuit corresponding to each bit indicates a match, the current control circuit corresponding to the match detection circuit includes:
The state of the counter is changed from the active state to the inactive state, and the current of the charge pump is reduced by the current value of the current control circuit in the inactive state. When the match detection circuit indicates a match, all of the plurality of current control circuits are inactive, and are not controlled by the output of the match detection circuit. A configuration may be adopted in which the capacitance is charged and discharged based on the phase comparison result.

[0014] The above-mentioned object is achieved by the invention of each claim of the present application as will be apparent from the following description of embodiments.

[0015]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a basic configuration of an embodiment of the present invention. Referring to FIG. 1, the PLL circuit includes a phase frequency comparator (P) having an input signal X1 as an input.
FC) (101) and a charge pump that charges / discharges a capacity (not shown) according to a comparison result signal (UP / DOWN) from the phase frequency comparator 101 and generates a voltage corresponding to a phase frequency difference. (CP) (102), a loop filter (LPF) (103) for smoothing the voltage,
An output voltage of the loop filter (103) is input as a control voltage, and an output signal φ having an oscillation frequency corresponding to the control voltage is output.
A voltage-controlled oscillator (104) for outputting a (multiplied signal);
A frequency divider (DIV) (105) that divides an output signal φ of the voltage controlled oscillator (104). The phase frequency comparator (101) includes an input signal (X1) and a frequency divider (10).
5) Compare the difference of the phase frequency of the output signal. In FIG. 1, for example, a phase frequency comparator (PFC) (101) converts a frequency of a frequency-divided signal of a frequency divider (105) into an input signal (X
When the frequency is lower than the frequency of 1) (and when the frequency-divided signal is behind the phase of the input signal (X1)), an UP pulse is output, and the frequency of the frequency-divided signal is lower than the frequency of the input signal (X1). Is large (and when the frequency-divided signal is ahead of the phase of the input signal (X1)), a DOWN pulse is output. Note that the phase frequency comparator (PFC) (101)
Of course, it may be replaced by a phase comparator that detects the phase difference between the edge of the input signal (X1) and the edge of the frequency-divided signal. In this case, the phase comparator outputs a comparison result signal (UP / DOWN) based on the phase difference to the charge pump 102.

The lock determination circuit of the PLL circuit (10) includes a "0" value holding register (21), a multiplier holding register (22), a comparison circuit (23), and an up / down counter (24). Have.

The up-down counter (24) inputs an input signal (X1) (or a frequency-divided signal thereof) from a control terminal as a control signal for controlling the up-counting / down-counting operation. At the logical value of the PLL circuit (1
0) (or its divided signal)
On the other hand, when the control signal has the second logical value, the count-down operation is performed in response to the output signal (φ) of the PLL circuit (10) (or the frequency-divided signal thereof).

The comparison circuit (23) receives the input signal (X1)
(Or its divided signal), the control signal for controlling the up-counting / down-counting operation is input, and the count value of the up-down counter (24) is input to determine whether the locked state is established. When the control signal transitions from the first logical value to the second logical value, the count value of the up / down counter (24) is held in the multiplier holding register (22). A first determination signal (not shown) that is activated when the value matches a predetermined first value, and latched and output.

Subsequently, the comparator (23) sets the count value of the up / down counter (24) to the "0" value holding register (21) when the control signal transitions from the second logical value to the first logical value. ) Is compared with a predetermined second value, and a second determination signal (not shown) activated when it matches is generated and latched and output. When both the first and second determination signals are active, control is performed to output a determination signal indicating a locked state.

FIG. 2 is a diagram for explaining the operation of the embodiment of the present invention. In this example, for simplicity, it is assumed that the voltage-controlled oscillator (104) of the PLL circuit (10) in FIG. 1 outputs an output signal (φ) having a frequency obtained by multiplying the frequency of the input signal (X1) by eight. It is assumed that the duty ratio of X1 is 50%. In this case, in the configuration shown in FIG. 1, the input signal (X1) having the duty ratio of 50% is used as it is as the control signal.
1) may be supplied as a control signal to a comparison circuit (23) and an up / down counter (24) via a waveform shaping circuit (not shown), or an input signal (X1).
A signal obtained by dividing the frequency of the signal by a frequency divider (not shown) by 比較 is compared with a comparison circuit (23) and an up / down counter (24)
May be supplied as a control signal.

Referring to FIGS. 1 and 2, when the input signal (X1) is at the High level, the up / down counter (24) sets the output signal (φ) of the PLL circuit (10) to Hi.
At the falling edge from the gh level (first logical value) to the low level (second logical value), the count-up operation is performed, and “0”, “1”, “2”, “3”, “4” are performed. "And count up.

In response to the falling transition of the input signal (X1) from the high level to the low level, the comparison circuit (23) sets the count value of the up / down counter (24) and the multiplication number holding register (22). It is determined whether or not the value “4” held in the storage area matches (see “Comparative determination 1” in FIG. 2). A PLL is stored in the multiplier holding register (22).
The multiplication number of the output signal of the circuit (10) and the PLL circuit (1
0) is stored based on the output signal (φ) counting period. For example, when the multiplication number is “8” and the output signal (φ) of the PLL circuit (10) is counted for a half cycle period of the input signal (X1), the multiplication number holding register (2
2) stores “4”.

Subsequently, when the input signal (X1) is at the low level, the up / down counter 24 enters the countdown mode, and counts down from the count value "4" at the falling edge of the output signal (φ) of the PLL circuit (10). The operation is performed, and the countdown is performed to “3”, “2”, “1”, and “0”. Then, the input signal (X1) is Low.
In response to the rising transition from the high level to the high level, the comparison circuit (23) sets the up / down counter (2
It is determined whether the count value of 4) matches the value “0” of the “0” value holding register (21) (see “Comparison 2” in FIG. 2). When the PLL circuit (10) is in the locked state, the up-count number and the down-count number of the output signal (φ) in the half cycle period of the input signal (X1) are both “4”, and “comparison judgment 1” "Comparison judgment 2"
Since both match, the comparison circuit (23) outputs a determination signal indicating a locked state when both "comparison determination 1" and "comparison determination 2" indicate a match. On the other hand, PL
When the L circuit (10) is in the unlocked (unlocked) state, the up-count and / or down-count of the output signal (φ) during the half cycle of the input signal (X1) is “4”. However, since the "comparison determination 1" and / or the "comparison determination 2" do not match, the comparison circuit (23) outputs a determination signal indicating an unlocked state.

The comparison circuit (23) preferably has the configuration shown in FIG.
For reference, the count value of the counter (24 in FIG. 1) is viewed.
And a multiplier holding register (2) for storing the first value.
It is checked whether the corresponding bits in 2) match each other.
A plurality of match detection circuits (31₁~ 3
1₃) (Also referred to as a “first group match detection circuit”) and the first
Group match detection circuit (31₁~ 31₃) Output,
When all the outputs of the first group match detection circuits indicate a match
To the first logic circuit (3
2₁) And the second logical value of the control signal (Y1).
At the time of transition to the logical value, the first logical circuit (32₁Out)
And outputting the first determination signal as the first determination signal.
1 latch circuit (33₁) And a counter (24 in FIG. 1)
"0" that stores the bit of the count value and the second value
The corresponding bits of the value holding register (21) are mutually
Multiple match detections that detect bit-by-bit
Road (31 ₄~ 31₆) (Also referred to as "second group match detection circuits")
), And inputs the outputs of the second group of coincidence detection circuits,
When all the outputs of the match detection circuits of the second group indicate a match
A second logic circuit (32
₂) And the first logic value from the second logical value of the control signal (Y1).
At the time of transition to the logical value, the output of the first logic circuit is sampled.
A second latch that pulls and outputs the second determination signal
Circuit (33₂) And said first and second latch circuits.
The first and second determination signals are input and the first and second determination signals are input.
The output of the logical AND of the judgment signal of No. 2 is used as the judgment signal.
And an AND circuit (34) for outputting from the child.

In one embodiment of the present invention, the comparison circuit (23) converts the first logical value of the control signal (Y1) to the second logical value.
At the time of transition to the logical value of
It is determined whether or not the count value of 4) coincides with the multiplication number holding register (22). If the count value coincides, a determination signal to be activated is output, and the up / down counter (2) is output.
At the time of the down-counting of 4), at the time of transition from the second logical value of the control signal to the first logical value (the comparison determination is made as to whether the count value matches the “0” value holding register (21) or not). Instead, the up-down counter (24) may be reset (cleared to zero). In such a configuration, detection from the unlocked state to the locked state can be performed.

The present invention, in another embodiment, is shown in FIG.
Referring to FIG. 1, the count value of the counter (24 in FIG. 1) that counts the number of cycles of the output signal over a predetermined counting period determined based on the cycle of the input signal (X1) of the PLL circuit is equal to the multiplication number and the count. (when counting period is one cycle, this value is the multiplication factor) value determined from the period whether matches, a plurality of coincidence detection circuit for comparing each bit (31 1 _{to 31 4)} , A plurality of match detection circuits (31
_{1-31 4)} provided corresponding, on the basis of the output of the coincidence detection circuit, activation and deactivation and are controlled respectively,
When activated, each based on the comparison result of detection of the phase frequency comparator comprises a plurality of current control circuit (43 1 _{to 43 4)} for charging and discharging the capacitance.

The coincidence detection circuit corresponds to any one of the most significant bit (MSB) to the least significant bit (LSB) of the count value of the counter (24 in FIG. 1). Indicates a match, only when all the outputs of the match detection circuit corresponding to the most significant bit and each bit higher than the one bit indicate a match, the match corresponding to the one bit control circuit for sequentially controlling the enable output of the detection circuit (a logic circuit ₄₀ 1 to 40 _3, the register ₄₁ 1 to 41 ₄₎ and a. The control circuit, when the output of the coincidence detection circuit corresponding to the most significant bit (31 ₄₎ indicates a mismatch, the coincidence detection circuit than the most significant bits corresponding to all the bits of the lower (31 _{3-31 In} contrast to ₁ ), even if the output of the coincidence detection circuit indicates a coincidence, the output is invalidated and is not transmitted to the corresponding current control circuit.

In this embodiment, a PLL circuit
The output signal (φ) of (10) is, for example, the input signal (X1)
Counting with a counter (24 in FIG. 1) for one cycle
Compare the match detection circuit that compares the count value with the multiplier.
Based on the result, how close you are to the locked state
Are sequentially compared from the MSB side (a kind of binary search
Method), the magnitude of the charge pump current according to the judgment result
Variable to reduce the time required for locking.
Can be. In other words, the highest value of the count value of the counter
Match detection circuit (31) corresponding to the bit (MSB)₄)But
When a mismatch condition is indicated, the most significant bit to the lowest
Each match detection circuit (31 ₄~ 31
₁) Corresponding to each of the current control circuits (43₄~ 43₁)
Are activated, and the current value of the charge pump is
Large value. Of the count value of the counter (24 in FIG. 1)
Most significant bit (MSB) to least significant bit (LSB)
In order, the match detection circuit for the corresponding bit
When indicating, in order from the MSB side to the LSB side,
The corresponding current control circuit switches from the active state to the inactive state
And the current value of the current control circuit that has become inactive.
And lower the charge pump current (the current value in FIG. 8).
I), MS of the count value of the counter (24 in FIG. 1)
B, all of the coincidence detection circuits corresponding to LSB
When it indicates a match, a plurality of current control circuits (43₁~ 43
₄) Is inactive and controlled by the output of the match detection circuit.
At least one current control circuit (42) not controlled
(Charge pump) is connected to the phase frequency comparator (10 in FIG. 1).
1) Capacity according to the comparison result output (UP / DOWN)
(Not shown).

More specifically, the counter (24 in FIG. 1)
Multiplier that stores the bit of the count value and the multiplier N
The corresponding bits of the holding register (22 in FIG. 6)
Is detected bit by bit to determine if
A match detection circuit (31₁~ 31
₄) Is replaced by M bits, which is the number of bits representing the multiplication number N in binary.
6 (= the number of bits of the count value of the counter).
M = 4), corresponding to the first to Mth bits of the counter.
The outputs of the first to M-th match detection circuits are
To fourth latches that latch based on the transition edge of
Circuit (41₁~ 41₄) And the first to M-1 latch times
Logic circuit (40 ₁~ 40₃)
And I-th (where i is 1 to M-1)
(Integer) logic circuit is the i-th block of the counter (24 in FIG. 1).
I-th match corresponding to the set (where i is 1 to M-1)
Detection circuit (31_i) And the (i + 1) th bit
The (i + 1) th match detection circuit (31_{i + 1}) Output
The (i + 1) th latch circuit (41_{i + 1}) Output signal
And the output of the (i + 1) th latch circuit is activated.
Depending on whether it is active or inactive,
Output the match detection circuit output signal
), Mask (output a fixed value, and perform the i-th match detection).
The output signal of the output circuit is not output and is invalidated).

Further, the first to M-th current control circuits (43 ₁ ) provided corresponding to the first to M-th (M = 4 in FIG. 6) latch circuits (41 _{1 to} 41 ₄ ). ~ 4
3 ₄ ) respectively receives the output signals of the _{first to} M-th latch circuits (41 _{1 to} 41 ₄ ) as control signals from a control terminal C. When the control signal of the control terminal C is active, A first switch (PM1 in FIG. 7B) inserted in the charging path between VDD and the output terminal O
2) and the second switch (NM12 in FIG. 7B) inserted in the discharge path between the output terminal O and the ground are both turned off. When the control signal is inactive, the second switch is turned off. The first and second switches are turned on, and the comparison result signal (UP) from the phase frequency comparator (101 in FIG. 1) is output.
/ DOWN), a constant current is supplied to the output terminal O from the power supply side, and discharge is performed from the output terminal O to the ground by the constant current. Current control circuit of the first through M ₍₄₃ 1 to 4
An output terminal of 3 ₄₎ are commonly connected to a capacitor terminal of the charge pump. The current control circuit (43 ₁
The sum of the output current of ~ 43 _4), a current controlled oscillator (I
Needless to say, the configuration may be used as the control current of (CO). The current control oscillator (ICO) is configured to convert, for example, the output voltage of the loop filter (103 in FIG. 1) into a current (control current) and vary the oscillation frequency according to the current value.

[0031]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

FIG. 3 is a diagram showing the configuration of one embodiment of the present invention. The PLL circuit in FIG. 3 has the same configuration as that shown in FIG. The input signal X1 of the PLL circuit 10 is frequency-divided by で in the 分 frequency divider 11, and the frequency-divided signal Y1 is input to the PLL circuit 10 as an input signal. The PLL circuit 10 outputs, for example, a signal obtained by multiplying the frequency of the frequency-divided signal Y1 by “20”, and halves the output signal (multiplied by 20) of the PLL circuit 10.
The signal whose frequency has been divided by で in the frequency divider 12 is output as an output signal φ. As a result, the frequency multiplication number of the output signal φ with respect to the input signal X1 depends on the frequency division ratio of the input signal X1 and the PLL.
From the multiplication number of the circuit 10 and the division ratio of the output signal, (1/1 /
2) × 20 × (１ ／) = 5 times (multiplication number is 5) The frequency division ratio of the input signal X1 and the PLL circuit 1
Of course, the multiplier of 0 and the division ratio of the output signal are not limited to the above numerical values.

Referring to FIG. 3, the lock determination circuit 20
Receives the frequency-divided signal Y1 as a control signal Y1 for controlling the up-counting / down-counting operation, and when this control signal is at the High level,
An up-down counter that counts up by receiving an output signal φ of the frequency divider 12 and counts down by receiving an output signal φ of the 1/2 frequency divider 12 of the PLL circuit 10 when the control signal Y1 is at a low level. 24 and the transition value of the control signal Y1 from the High level to the Low level, the count value of the up / down counter 24 is changed to a predetermined first value (multiplier = 5) is compared to determine whether it matches, generates a first determination signal that becomes active when it matches, latches it, and raises and lowers it when the control signal Y1 transitions from low level to high level. It is determined whether or not the count value of the counter 24 matches a predetermined second value (zero value) held in the “0” value holding register 21. Control for generating and latching a second determination signal that becomes active when the two match, and outputting a determination signal indicating that the locked state is established when both the first and second determination signals are active. And a comparison circuit 23 for performing

In FIG. 3, the multiplier switching signal is a PLL
Input to the circuit 10 and the multiplier holding register 22;
The PLL circuit selects one of a plurality of values of the multiplier in accordance with the value of the multiplier switching signal, and sets a value corresponding to the multiplier in the multiplier holding register 22.

FIG. 5 is a diagram showing an example of the configuration of the comparison circuit 23 shown in FIG. The multiplier is "5", and the value held in the multiplier holding register 22 is "5"("101": 3 bits). This is because the output signal φ counted by the up / down counter 24 is the input signal X
This is because the frequency of 1 is multiplied by 5 and the output signal φ over one cycle period of the input signal X1 is counted for 5 cycles.

Referring to FIG. 5, the comparison circuit is an up-conversion circuit.
The count value (3 bits) of the
Each corresponding bit of the multiple holding register 22 (3 bits)
That constitutes a match detection circuit that detects whether or not
Logical NOR (EXNOR) circuit 31₁~ 31₃And mosquito
Count value and the value of the “0” value holding register 23 (3 bits)
Match detection circuit that detects whether the corresponding bit matches
Exclusive-NOR (EXNOR) circuit 31₄
~ 31₆And the EXNOR circuit 31₁~ 31₃Input
Logical AND (AND) circuit 32 as a force₁And EXNOR times
Road 31₄~ 31 ₆AND (AND) with the output of the as input
Circuit 32₂And the AND circuit 32₁The output of
D which is sampled and output at the rising edge of the signal Y1
Type flip-flop 33₁And the AND circuit 32₂Output
Is sampled and output at the falling edge of the signal Y1.
D-type flip-flop 33₂And a D-type flip-flop
33₁Output (first determination signal) and D-type flip-flop
Step 33₁ANDing with the output of (the second determination signal) as an input
(AND) circuit 34, and the AND circuit 34
Is the lock state determination signal (when the output is
(Locked when unlocked, Low). D type
Lip flop 33₁And D-type flip-flop 33
₂Is preferably reset at the time of initialization etc.
It is configured as a flip-flop with a terminal.

FIG. 4 is a timing chart for explaining the operation of one embodiment of the present invention. The operation of one embodiment of the present invention will be described with reference to FIG. 4, FIG. 3 and FIG.
4, the input signal X1, the control signal Y1, the output signal φ, the output and operation of the up / down counter 24 (counter) (up (UP) count and down (DOWN) count), the multiplication number holding register 24, The timing of the determination operation in the “0” value holding register 21 and the comparison circuit 23 is shown. It is assumed that the duty ratio of the control signal Y1 obtained by dividing the input signal X1 by で by the frequency divider 11 is 50%. The up / down counter 24 determines that the control signal Y1 is Hi.
At the time of the gh level, the count-up operation is performed at the falling edge of the output signal φ multiplied by 5 from the high level to the low level, and from the value “0” to “1”,.
(Φ cycles t1 to t)
5).

[0038] In the comparison circuit 23, the count value of the up-down counter 24 and, the AND circuit 32 ₁ of the output to input the output of the EXNOR circuit ₃₁ 1 to 31 ₃ for comparing the value of the multiplication number holding register 22 "5" (comparison) has been supplied to the data input terminal of the D-type flip-flops 33 ₁ to receive the falling transition of the control signal Y1 to Low level from the High level (transition of the control signal Y1 of the start of a cycle t6) And the D-type flip-flop 33
₁ is the count value of the up / down counter 24 and “5”
Latching the output of the AND circuit 32 ₁ is a comparison of. In this case, the output of the AND circuit 32 ₁ is High level, the output Q of the D-type flip-flop 33 ₁ Hi
gh level (PASS). In the example shown in FIG. 4, since the determination result in cycles t1 is PASS, the cycle t6, the output Q of the D-type flip-flop 33 ₂ is held by a High level (PASS), the AND circuit 34 A high level indicating PASS (locked state) is output.

Then, the control signal Y in cycle t6
1 from a High level to a Low level,
The up / down counter 24 enters a countdown mode, and performs a countdown operation from “5” at the falling edge of the output signal φ, and outputs “4”, “3”, “2”,
Count down to "1" and "0".

In the comparison circuit 23, the count value of the up / down counter 24 and the "0" value holding register 21
EXNOR circuit ₃₁ for comparing the the value "0" 4-31 ₆
Hig output of the AND circuit 32 ₂ for receiving the output (comparison result) is supplied to the data input terminal of the D-type flip-flop 33 _2, the control signal Y1 from the Low level
In response to a falling transition of the h level, D-type flip-flop 33 ₂ latches the count value of the up-down counter 24 and the output of the AND circuit 32 ₂ is a comparison result of "0". Figure In 4 shows an example, since the determination result in cycles t11 is PASS, the output Q of the D-type flip-flop 33 ₂ is the High level (PASS), D-type flip-flops 33 ₁ and D-type flip-flop 33 ₂ AND circuit 34, which receives the output of
A High level indicating SS (locked state) is output.
That is, the value of the decision signal outputted from the AND circuit 34 of the comparison circuit 23, the output of D-type flip-flop 33 ₁ (first determination signal), the output of D-type flip-flop 33 ₂ (second determination signal) When both are at the High level, H
high level and the D-type flip-flops 33 ₁ , 3
3 ₂ Low when either or both of the Low level of the output
Level.

If the count value of the up / down counter 24 and the result of comparison between the "0" value holding register 21 and the multiplier holding register 22 change from a match state to a mismatch state, the value of the determination signal becomes , D-type flip-flop 3
3 _1, 33 ₂ of the control signal Y which defines a latch timing
1 is updated on the rising and falling edges.

Note that the comparison circuit 23 outputs the H level of the control signal Y1.
At the time of the transition from the high level to the low level, it is determined whether or not the count value of the up / down counter 24 matches the multiplier holding register 22. If the count value matches, a determination signal that becomes active is output. When the down counter 24 counts down, the control signal transitions from a low level to a high level (the count value is “0”).
It is also possible to adopt a configuration in which the up-down counter 24 is reset (cleared to zero), and the up-down counter 24 is reset (zero clear). In such a configuration, detection from the unlocked state to the locked state can be performed.

The lock determination circuit 20 shown in FIG.
By integrating it on the same chip as the L circuit 10, the PL
The test circuit may be incorporated in the L circuit 10, or may be configured as an external circuit as a test circuit.

As an application to a test system, for example, a PLL circuit 10 is connected to a device under test (Device
Automatic test equipment (A) such as an LSI tester for testing as an under test (DUT)
It may be configured as a test jig added to a load board of TE). In this case, the ATE applies the input signal X1 from the driver to the DUT, inputs the determination signal output from the lock determination circuit 20 from the comparator, determines the lock state, and determines pass / fail (PASS / FAIL). According to such a configuration, in the ATE, it is not necessary to accumulate the output signal of the PLL circuit in the local memory or the like on a cycle basis, and the required capacity of the local memory can be reduced.
In addition, arranging the test circuit in the immediate vicinity of the pin of the DUT makes the timing accuracy and the like required for the ATE moderate, and has the advantage that the test can be performed accurately and accurately with an inexpensive ATE. Even when the lock determination circuit 20 is incorporated in the PLL circuit 10, the test is facilitated according to the same principle as described above.

Next, a second embodiment of the present invention will be described. FIG. 6 is a diagram showing the configuration of the second exemplary embodiment of the present invention. The configuration of the PLL circuit is the same as the configuration shown in FIGS. In FIG. 6, the bit number of the multiplier holding register 22 is set to "4", and a match detecting circuit for detecting whether the count value of the multiplier holding register 22 matches the count value of the up / down counter 24 (see FIG. 3) is equivalent to 4 bits. (Ie, the number of bits when the multiplication number is expressed in binary), ie, E
And a XNOR circuit ₃₁ 1 to 31 _4.

In this embodiment, the EXNOR circuits 31 _{1 to} 3 ₁
Based on the coincidence detection output of 1 _4, or approaching much the locked state, from MSB (most significant bit) side of the count value of the counter to the LSB (least significant bit) side, performs sequential control, the input signal X1 In each cycle, the current of the charge pump CP (102 in FIG. 1) is variably controlled. The output of the EXNOR circuit corresponding to a certain bit from the MSB to the LSB of the count value of the counter is determined by the corresponding latch circuit when all the outputs of the EXNOR circuit of higher bits than the bit indicate a match (at a high level). It is latched and variably controls the current of the charge pump CP.

That is, for example, the multiplier of the PLL circuit is “10”, “1010” is held in the multiplier holding register 22, and the counter value and the first bit (L
SB) each other, are input to EXNOR circuit 31 _1, the fourth bit (MSB) among the counter value and register 22,
Are input to EXNOR circuit 31 _4, the second bit of the counter value and register 22, the third bit each other, are input to EXNOR circuits ₃₁ 2, 31 _3.

The output of the EXNOR circuit 31 ₄ is the corresponding D
It is input to the data input terminal D of the type flip-flop 41 _4.

The output Q of the EXNOR circuit 31 ₃ and the output of the D-type flip-flop 41 ₄ is inputted to the AND circuit 40 _3, the output of the AND circuit 40 _3, the data input of a corresponding D-type flip-flop 41 ₃ It is input to terminal D.

The output Q of the EXNOR circuit 31 ₂ and the output of the D-type flip-flop 41 ₃ is input to the AND circuit 40 _2, the output of the AND circuit 40 _2, data input of the corresponding D-type flip-flop 41 ₂ It is input to terminal D.

The output Q of the EXNOR circuit 31 ₁ and the output of the D-type flip-flop 41 ₂ is inputted to the AND circuit 40 _1, the output of the AND circuit 40 _1, the corresponding D-type flip-flops 41 ₁ Data input It is input to terminal D.

[0052] The clock input terminal of D-type flip-flop ₄₁ 1-41 _4, the divider of the input signal X1 (FIG. 3 11
Input signal X1) is commonly input.

D-type flip-flops 41 ₄ , 41 ₃ , 4
1 _2, 41 ₁ of the output a, b, c, d controls charging of the charge pump, discharge current, respectively, the current control circuit 4
3 _{4, 43 3,} are input to the 43 2, 43 ₁ of the control terminal C.

[0054] The current control circuit ₄₃ 1 to 43 ₄ will be explained in detail later, type phase frequency comparator UP signal output from the (101 in FIG. 1), the DOWN signal U terminal, a D terminal, When the control terminal C is at the low level, the UP signal and the DOWN signal charge and discharge the capacity (not shown) during the active period, respectively.

[0055] AND circuit 40 _3, the output of the D-type flip-flop 41 ₄ is High level count value of the (multiplication number holding register 22 and the counter (24 in FIG. 3) M
SB each other coincide), the outputs the output of the EXNOR circuit 31 ₃ for comparing a lower bit to the data input terminal of the D-type flip-flop 41 _3, the output of D-type flip-flop 41 ₄ is at Low level (MSB among the multiplication number holding register 22 count value of the counter does not match), the masked output of the EXNOR circuit 31 _3, and outputs a fixed value Low level.

[0056] AND circuit 40 _2, the output of D-type flip-flop 41 ₃ is High level (fourth and multiplication number holding register 22 count value of the counter, the third bit among both matches), the first outputs the output of the EXNOR circuit 31 ₂ for comparing the 2-bit data input terminal of the D-type flip-flop 41 _2, the output of D-type flip-flop 41 ₃ is at Low level (count of said counter and multiplication number holding register 22 At least one of the third and fourth bits of the value does not match)
If masks the output of the EXNOR circuit 31 _3, and outputs a fixed value Low level.

[0057] AND circuit 40 _1, in a case that the output of D-type flip-flop 41 ₂ is High level (fourth to second bit among the multiplication number holding register 22 and the count value of the counter are both matches), first Bit (LSB)
The output of the EXNOR circuit 31 ₁ for comparing output to the data input terminal of the D-type flip-flop 41 _1, and when the output of the D-type flip-flop 41 ₂ is Low level (multiplication number holding register 22 and the up-down counter first 2 to at least a bit of the fourth bit do not match), the masked output of the EXNOR circuit 31 _1, L
Outputs the low level.

Current control circuit 42 without control terminal C
Inputs the UP signal and the DOWN signal output from the phase frequency comparator (101 in FIG. 1) to the U terminal and the D terminal,
When the P signal and the DOWN signal are active,
The capacity (not shown) is charged and discharged.

The current control circuit 42 and the current control circuits 43 ₁ to 43 ₁ .
An output terminal O of 43 ₄ are commonly connected, charging the capacitance of the connected (not shown) between the output terminal and the Grant,
Discharge. The capacitance may be provided in the loop filter (103 in FIG. 1).

FIG. 7A is a diagram showing the configuration of the current control circuit 42 (see FIG. 6). The current control circuit 42 includes a switch transistor that is turned on and off by an UP / DOWN signal in a current path of a constant current source.
A charge / discharge control circuit serving as a charge pump of the circuit is configured. Referring to FIG. 7A, the current control circuit includes:
A P-channel MOS transistor PM1 for inputting an UP signal to a gate and an N-channel MOS transistor NM1 for inputting a DOWN signal to a gate include a constant current source Io1 between the source of the P-channel MOS transistor PM1 and the power supply VDD. Connected, N-channel MO
A constant current source Io2 (sinking with the same constant current Io as the constant current source Io1 for supplying discharge current) is connected between the source of the S transistor NM1 and the ground, and the P channel M
Drain of OS transistor PM1 and N-channel MOS
The drain of the transistor NM1 is connected to the output terminal O. In this configuration, while the UP signal is at the Low level, the P-channel MOS transistor PM1 conducts, outputs a constant current Io from the power supply VDD to the output terminal O, and charges a capacitor (not shown) connected to the output terminal O. , DOWN signal is at the High level, the N-channel MOS transistor NM1 conducts, and the output terminal O discharges to the ground with the constant current Io.

[0061] FIG. 7 (b) is a diagram showing the configuration of the control terminal current with a C control circuit ₄₃ 1 to 43 ₄ (see FIG. 6). Referring to FIG. 7B, this current control circuit
A P-channel MOS transistor PM11 that uses an inverted signal of the P signal as a gate; and an N-channel MOS transistor NM11 that inputs a DOWN signal to the gate.
Source and power supply V of channel MOS transistor PM11
A constant current source IO1 and a P-channel MOS transistor PM12 are connected in series between DD. The source of the P-channel MOS transistor PM12 is connected to the power supply VDD, the gate receives an inverted signal of the control signal C, and the drain is connected to the constant current source Io1. Between the source of the N-channel MOS transistor NM11 and the ground, a constant current source Io2 (with the same constant current as the constant current source Io1 supplying the discharge current) and an N-channel MOS
The transistor NM12 is connected in series. The drain of the P-channel MOS transistor PM11 and the drain of the N-channel MOS transistor NM11 are connected to the output terminal O. N channel MOS transistor N
The source of M12 is connected to the ground, the gate receives a signal obtained by inverting the control signal C by the inverter INV, and the drain is connected to the constant current source Io2.

When the control signal C is at the low level, the gate of the p-channel MOS transistor PM12 is set to the low level to conduct and the n-channel MOS transistor N
Since a High-level signal obtained by inverting the control signal C by the inverter INV is input to the gate of M12, N
The channel MOS transistor NM12 is also turned on, and performs the same operation as the circuit shown in FIG. UP
While the signal is at the Low level, the P-channel MOS transistor PM11 conducts and outputs a constant current Io from the power supply VDD to the output terminal O to charge a capacitor (not shown).
While the signal is at the High level, the N-channel MOS transistor NM11 conducts, and discharges the accumulated charge of the capacitor (not shown) from the output terminal O to the ground.

On the other hand, when the control signal C is at the high level, the P-channel MOS transistor PM12 is turned off, and the gate of the N-channel MOS transistor NM12 has L at which the control signal C is inverted by the inverter INV.
Since the low level is input, the N-channel MOS transistor NM12 is also turned off, and the control signal C becomes H level.
The current control circuit 43 _i at the high level (where i
Are inactive. In this case, the current control circuit 43 _i is regardless of the value of the UP input, DOWN signal is not performed charging and discharging operations of the capacitor.

FIG. 8 is a timing chart showing an example of the operation of this embodiment. In the initial state, it is assumed that D-type flip-flop ₄₁ 1-41 ₄ are reset, their outputs are Low level. In the first cycle of the input signal X1 (the control signal Y1 in FIG. 3 is High level),
The count value of the up / down counter 24 (see FIG. 3) has not reached the multiplication number “10”. In this case, since the number of cycles of the output signal φ of the PLL circuit per cycle of the input signal X1 has not reached “10”, it is necessary to increase the frequency of the output signal φ of the PLL circuit. In FIG. 3, the 1/2 frequency divider 12 is omitted, and the output of the PLL circuit 10 is directly used as the output signal φ so that the multiplication factor “1” is obtained.
0 "is obtained. In this case, the up / down counter 24
(See FIG. 3) inputs the output signal of the PLL circuit 10 as a count signal.

EXNOR circuit 31 of FIG.₁~ 31₄Out of
The force is at a low level, and the up-down counter 24
D-type flip-flop 4 corresponding to MSB of count value
1₄Because the output a of is low level,
The AND circuit 40₃, 40 ₂, 40₁Output is Low
Level and the D-type flip-flop 41₃, 41₂,
41₁Are also Low level. Low
The level signals a, b, c, and d are input to the control terminal C.
Current control circuit 43₄, 43₃, 43₂, 43₁Will eventually
Is also activated, in this case, the capacity of the charge pump
The charged current value I is the maximum.

[0066] up-down counter 24 (see FIG. 3) the fourth bit (MSB) count value of the counter value when it becomes "8" of "1" and the output of the EXNOR circuit 31 ₄ is in the High level , at the rising edge of the next input signal X1 (timing t1), D-type output a of flip-flop 41 ₄ consists High level from Low level, the current control circuit receiving the output a of the D-type flip-flop 41 ₄ to the control terminal C 43 ₄ deactivates. As a result, the current value I charged to the capacity of the charge pump is
Reducing the current value Io caused by the current control circuit 43 ₄ (down one step).

[0067] output a D-type flip-flop 41 ₄ H
When the igh level, the AND circuit 40 ₃ EXNOR
And outputs the output of the circuit 31 _3, in this case, since the third bit of the third bit and the counter value of the register 22 are both "0", the output of the EXNOR circuit 31 ₃ Hi
becomes gh level, it passes through the AND circuit 40 _3, the rising edge of the input signal X1, D-type flip-flop 4
1 ₃ latches the output of the EXNOR circuit 31 _3. FIG.
In the example shown in FIG. 7, the timing t when the counter value becomes "9"
In 2, the output b of D-type flip-flop 41 ₃ H
It has transitioned to the high level. As a result, the current control circuit 43 ₃ for receiving an output b of D-type flip-flop 41 ₃ to the control terminal C starts to deactivation. In this case, the current value I charged in the capacity of the charge pump depends on the current control circuit 43
₃ (decrease by one step).

Further, at timing t3, the counter value becomes "11", and the second bit of the register 22 and the second bit of the counter value are both "1".
The output of the OR circuit 31 ₂ becomes High level, the output value passes through the AND circuit 40 _3, D-type flip-flop 41 ₂ at the rising edge of the input signal X1 is EXNO
Latches the output of the R circuit 31 _2, its output is transitioning to the High level. As a result, the current control circuit 43 which receives the output c of the D-type flip-flop 41 ₂ to the control terminal C
₂ turns to the inactive state. As a result, the current value I is stored in a capacitor of the charge pump decreases the current value Io caused by the current control circuit 43 ₂ (down one step).

Further, at timing t4, the counter value becomes "10", and the first bit of the register 22 and the first bit of the counter value are both "0".
The output of the R circuit 31 ₁ becomes High level, the output value passes through the AND circuit 40 _1, D-type flip-flop 41 ₁ at the rising edge of the signal X1 latches the output of the EXNOR circuit 31 _1, the output is High Has transitioned to the level. As a result, the D-type flip-flop 41 ₁
Output d and the current control circuit 43 ₁ is deactivated for receiving the control terminal C of the current value I is stored in a capacitor of the charge pump
Decreases the current value Io caused by the current control circuit 43 ₁ (down one step).

[0070] In this state, the current control circuit ₄₃ 4 -
43 ₁ all deactivated, only the current control circuit 42,
The UP signal from the phase frequency comparator (101 in FIG. 1) and D
In response to the OWN signal, the capacitor (not shown) is charged and discharged.

[0071] Incidentally, changing the current value of the current source in the current control circuit ₄₃ 4 _{~43 1,} W (gate width) of the MOS transistor / L (gate length) ratio that is set to a different value, the current driving capability May be set to be different from each other.

The UP and D signals from the phase frequency comparator (101 in FIG. 1) are obtained only by the current control circuit (102 in FIG. 1).
Normal P in which the charge and discharge of the capacity are performed by the OWN signal
Unlike the configuration of the LL circuit, according to this embodiment, the count value of the counter is compared bit by bit with the register storing the multiplier, and the phase frequency comparator (101 in FIG. 1) as long as the MSB does not match. The current value charged by the UP pulse signal from the controller (and the current value discharged by the DOWN pulse signal) is set to a large current value, and successive approximation control is performed in order from the MSB to the LSB, and each time a bit matches, the phase frequency comparator The current value charged by the UP pulse signal (and the current value discharged by the DOWN pulse signal) from (101 in FIG. 1) is reduced, and as described above, the charge increases as the distance from the lock state approaches the lock state. The current value supplied to the pump is varied, so that the number of cycles of the output signal of the PLL circuit is prevented from exceeding the target multiplication factor, and the multiplication factor is reached. Thereby making it possible to shorten the time required for the (locked).

A determination signal output from the lock determination circuit (20 in FIG. 3) is input to a processing device or the like, and the processing device supplies a clock signal from the PLL circuit based on the state of the determination signal. The required control may be performed on a circuit or the like that receives the signal, and the determination signal is applied to an arbitrary application.

The input signal X1 to the PLL circuit may be a clock signal supplied from a crystal oscillation circuit or the like,
In addition, any reference clock supplied from the clock generator may be used. Further, the PLL circuit may be a clock recovery circuit for extracting a clock from an input signal, or may be applied to a frequency synthesizer. As described above, the present invention is not limited to the configuration of the above-described embodiment, and various modifications and corrections that can be made by those skilled in the art within the scope of the claims set forth in the claims. Of course.

[0075]

As described above, according to the present invention,
Since the locked state is determined based on the output signal of the PLL, it is possible to achieve an accurate test.

By installing the lock detection circuit of the present invention in a PLL or externally attaching it as a test circuit, an accurate test can be realized even in an automatic test apparatus for performing a mass production test of the PLL.

Further, according to the present invention, the time required for locking can be reduced by sequentially comparing the degree of approach to the locked state and varying the magnitude of the current of the charge pump in accordance with the determination result. The effect is that it can be done.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation principle of one embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of one embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a comparison circuit according to one embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 7 is a diagram showing a current control circuit according to a second embodiment of the present invention.

FIG. 8 is a diagram for explaining the operation of the second exemplary embodiment of the present invention.

FIG. 9 is a diagram showing a configuration of a conventional lock detection circuit.

FIG. 10 is a timing chart for explaining the operation of the conventional lock detection circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 PLL circuit 11, 12 Divider 20 Lock determination circuit 21 "0" value holding register 22 Multiplier holding register 23 Comparison circuit 24 Up / down counter 311-316 Exclusive-NOR circuit 321, 322, 34, 401-403 AND circuits 331-332, 411-414 D-type flip-flops 42 Current control circuits 431-434 Current control circuits 101 Phase frequency comparators 102 Charge pumps 103 Loop filters 104 Voltage controlled oscillators 105 Frequency dividers 106 Exclusive NOR circuits 107 Delay circuit 108 D-type flip-flop

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J106 AA04 CC02 CC21 CC41 CC52 CC54 DD08 DD19 DD32 DD38 EE09 EE15 GG13 HH03 JJ09 KK32

Claims (16)

[Claims] 1. A lock determination circuit of a PLL (Phase Locked Loop) circuit for outputting an output signal obtained by multiplying the frequency of an input signal, wherein the output signal is output over a first counting period determined based on a cycle of the input signal. The number of cycles of the signal or the signal obtained by dividing the output signal by a predetermined dividing ratio is counted, and the counting result is obtained by multiplying the PLL circuit and the counting period, or multiplying the PLL circuit and the counting number. A first value for comparing with a first value determined from the period and the frequency division ratio;
Means for subtracting from the count result each time the output signal is counted for one cycle over a second count period determined based on the cycle of the input signal after the first count period. Second means for comparing whether or not the result obtained matches a predetermined second value; and when both the comparison results of the first and second means show a match, it indicates that the apparatus is in a locked state. A lock determination circuit for a PLL circuit, comprising: third means for outputting a determination signal. 2. An oscillator for outputting an output signal obtained by multiplying the frequency of an input signal, a frequency divider for dividing the output signal of the oscillator, and a frequency-divided signal of the frequency divider and the input signal. A charge pump that charges and discharges a capacitance based on a result of the phase comparison by the phase comparator and generates a voltage corresponding to a phase difference between the divided signal and the input signal; And a filter for smoothing the voltage of the input signal, wherein the oscillator varies the oscillation frequency based on the output of the filter. Over, the output signal, or a counting result of counting the number of cycles of the signal obtained by dividing the output signal at a predetermined frequency division ratio, the multiplication number of the PLL circuit and the counting period, or , The PL
First means for comparing whether or not the multiplication factor of the L circuit, the counting period, and the frequency division ratio match a first value; and, from the counting result, the next counting period of the input signal. Over, the second means for comparing whether or not the result obtained by subtracting the output signal each time the cycle is counted is equal to a zero value; and the comparison results of the first and second means are both the same. And a third means for outputting a determination signal indicating that the lock state is established when the signal indicates the lock state. 3. An oscillator for outputting an output signal obtained by multiplying a frequency of an input signal, a frequency divider for dividing the output signal of the oscillator, and a frequency-divided signal of the frequency divider and the input signal. A charge pump that charges and discharges a capacitance based on a result of the phase comparison by the phase comparator and generates a voltage corresponding to a phase difference between the divided signal and the input signal; A first input terminal for inputting a signal to be counted in a lock determination circuit of a PLL (Phase Locked Loop) circuit in which the oscillator varies an oscillation frequency based on an output of the filter. And a second input terminal for inputting a control signal for controlling up-counting and down-counting operations, and an output terminal for outputting a count value. The output signal of the PLL circuit or a signal obtained by dividing the output signal by a predetermined dividing ratio is input as the signal to be counted from the first input terminal, and the input signal or the input signal to the PLL circuit is input. Is input from the second input terminal as the control signal for controlling up-counting and down-counting operations when the control signal has a first logical value. A counter that performs a count-up operation in response to the target signal, and performs a count-down operation in response to the count target signal when the control signal has a second logical value; a first input terminal that receives the control signal as an input; A second input to which a count value from the output terminal of the counter is input;
A comparison circuit having at least an input terminal for outputting a lock determination result and a count value of the counter when the control signal transitions from the first logical value to the second logical value. A first comparing unit that compares and determines whether or not the control signal matches a predetermined first value, and outputs a first determination signal that is made active when the two values match each other; At the time of transition from the logical value of the counter to the first logical value, it is determined whether or not the count value of the counter matches a predetermined second value. A second comparison unit that outputs a second determination signal; and the first and second comparison units from the first and second comparison units.
A comparison circuit having a logic circuit for receiving a determination signal of the formula (1) and outputting a determination signal having a value indicating a locked state from the output terminal when the first and second determination signals are both active; A lock determination circuit for a PLL circuit, comprising: 4. An oscillator for outputting an output signal obtained by multiplying the frequency of an input signal, a frequency divider for dividing the output signal of the oscillator, and a frequency-divided signal of the frequency divider and the input signal. A charge pump that charges and discharges a capacitance based on a result of the phase comparison by the phase comparator and generates a voltage corresponding to a phase difference between the divided signal and the input signal; A first input terminal for inputting a signal to be counted in a lock determination circuit of a PLL (Phase Locked Loop) circuit in which the oscillator varies an oscillation frequency based on an output of the filter. And a second input terminal for inputting a control signal for controlling up-counting and down-counting operations, and an output terminal for outputting a count value. The output signal of the PLL circuit or a signal obtained by dividing the output signal by a predetermined dividing ratio is input as the signal to be counted from the first input terminal, and the input signal or the input signal to the PLL circuit is input. Is input from the second input terminal as the control signal for controlling up-counting and down-counting operations when the control signal has a first logical value. A counter that performs a count-up operation in response to the target signal, and performs a count-down operation in response to the count target signal when the control signal has a second logical value; a first input terminal that receives the control signal as an input; A second input to which a count value from the output terminal of the counter is input;
And at least an output terminal for outputting a lock determination result. At the time of transition of the control signal from the first logical value to the second logical value, the count value of the counter is predetermined. A comparison circuit that compares and determines whether or not the first value matches the first value, and outputs a determination signal that becomes active from the output terminal when the first value is matched. A lock determination circuit for a PLL circuit, wherein the count value of the counter is reset at the time of transition to a first logical value. 5. A transition edge from said second logical value to said first logical value of said output signal of said PLL circuit or a signal obtained by dividing said output signal by a predetermined dividing ratio, and said PLL.
From the second logical value of the input signal to the circuit to the first
When the transition edges to the logical value of the above overlap each other, the counter is configured to output the output signal of the PLL circuit or the second signal of the counting target signal including the signal obtained by dividing the output signal by a predetermined dividing ratio. 5. The lock circuit of a PLL circuit according to claim 3, wherein a count operation is performed at a transition edge from a logical value of 1 to the second logical value. 6. The comparison circuit, wherein the first comparison unit determines whether a bit of a count value of the counter and a corresponding bit of a first register storing the first value match each other. A plurality of coincidence detection circuits (hereinafter referred to as a "first group coincidence detection circuit") for detecting whether each bit is a bit, an output of the first group of coincidence detection circuits being input, and an output of the first group of coincidence detection circuits And a first logic circuit that outputs a signal that becomes active when all show coincidence, and the first logic circuit at the time of transition of the control signal from the first logic value to the second logic value A first latch circuit that samples the output of the counter and outputs the first determination signal as the first determination signal, wherein the second comparison unit stores the bit of the count value of the counter and the second value The corresponding bits of the second register are A plurality of match detection circuits (referred to as a "second group of match detection circuits") for detecting whether each bit matches or not, and an output of the second group of match detection circuits; A second logic circuit that outputs a signal that becomes active when all outputs of the match detection circuit indicate a match; and at the time of transition of the control signal from the second logic value to the first logic value, A second latch circuit that samples an output of the first logic circuit and outputs the sampled signal as the second determination signal, wherein the logic circuit that outputs the determination signal from the output terminal includes the first and second logic circuits. 2 of the first and second latch circuits.
4. A lock determination circuit for a PLL circuit according to claim 3, further comprising an AND circuit that receives the determination signal of (1) as an input and outputs a logical product output of said first and second determination signals from said output terminal. . 7. The PLL circuit according to claim 6, further comprising a lock determination circuit, wherein the number of bits of the binary value of the first value in the count value of the counter is M bits. The group match detection circuit
A first to M-th match detection circuit corresponding to first to M-th bits of the counter, and a first latch for latching outputs of the first to M-th match detection circuits based on transition edges of the input signal A first to an (M−1) th logic circuit provided corresponding to each of the first to (M−1) th match detection circuits;
The i-th (where i is an integer of 1 to M-1) logic circuit includes an i-th match detection circuit corresponding to an i-th bit (where i is an integer of 1 to M-1) of the counter. An output signal and an output signal of the (i + 1) th latch circuit for latching an output of the (i + 1) th match detection circuit corresponding to the (i + 1) th bit; The i-th output depending on whether the output is active or inactive
The first to M-1 logic circuits are configured to output or mask the output signal of the coincidence detection circuit, and are provided corresponding to the first to Mth latch circuits. A first to M-th current control circuits, wherein the first to M-th current control circuits
And an output signal of the latch circuit is input as an activation control signal, and when the activation control signal is active, a first switch inserted into a charging path between a power supply and an output terminal; When the activation control signal is inactive, the first and second switches are turned off together with the second switch inserted in the discharge path between the first and second switches.
Is turned on, and based on the comparison result signal from the phase comparator, the output terminal is charged and discharged respectively, and the first to M-th currents whose output terminals are commonly connected to the capacitor A PLL circuit, comprising: a control circuit; 8. An oscillator for outputting an output signal obtained by multiplying the frequency of an input signal, a frequency divider for dividing the output signal of the oscillator, and a frequency-divided signal of the frequency divider and the input signal. A charge pump that charges and discharges a capacitance based on a result of the phase comparison by the phase comparator and generates a voltage corresponding to a phase difference between the divided signal and the input signal; A PLL (Phase Locked Loop) circuit in which the oscillator varies the oscillation frequency based on the output of the filter. A predetermined counting period determined based on a cycle of the input signal. A counter for counting the number of cycles of the output signal, and determining whether or not the count value of the counter matches a value determined from the multiple of the output signal and the counting period. A plurality of match detection circuits for comparing each bit; and a plurality of match detection circuits are provided corresponding to the plurality of match detection circuits. Activation and deactivation are respectively controlled based on an output of each of the match detection circuits, and an active state is determined. When, based on the phase comparison detection result of the phase comparator, a plurality of current control circuits that charge and discharge the capacitance, and any one of the most significant bit to the least significant bit of the count value of the counter When the output of the match detection circuit indicates a match with respect to the match detection circuit corresponding to the bit, all the outputs of the match detection circuit corresponding to the most significant bit and each bit of the higher order bit than the one bit are all output. Only when indicating a match, the output of the match detection circuit corresponding to the one bit is made valid, and the output of the match detection circuit is transmitted to the corresponding current control circuit. And a control circuit for controlling the coincidence detection corresponding to the least significant bit from the most significant bit when the coincidence detection circuit corresponding to the most significant bit of the count value of the counter indicates a mismatch state. The current control circuits corresponding to the circuits are all activated, the current value of the charge pump is set to the maximum value, and the count value of the counter is sequentially counted from the most significant bit to the least significant bit, When the output of the match detection circuit corresponding to each bit of the count value indicates a match, the current control circuit corresponding to the match detection circuit is switched from an active state to an inactive state, and The current of the charge pump is reduced by the current value of the current control circuit, and all the bits corresponding to the least significant bit to the least significant bit of the count value of the counter are reduced. When the match detection circuit indicates a match, all of the plurality of current control circuits are deactivated, and at least one of the current control circuits is not controlled by the output of the match detection circuit. A PLL circuit for charging and discharging the capacitance based on a result. 9. A phase comparator, a charge pump for charging or discharging a capacitance based on a phase comparison result from the phase comparator to generate a voltage according to a phase difference, and smoothing a voltage according to the phase difference. A voltage-controlled oscillator whose oscillation frequency is varied based on an output voltage of the filter; and a frequency divider that receives an output signal from the voltage-controlled oscillator, divides the frequency, and outputs the divided signal. The comparator detects a phase difference between the input signal and the frequency-divided signal divided by the frequency divider. The output signal is obtained by multiplying the frequency of the input signal by N.
In a phase locked loop (LL) circuit, a counter that counts up based on an output signal output from the PLL circuit during one cycle period of the input signal, and a count value of the counter when one cycle period of the input signal elapses Is a circuit for detecting whether or not the value of the counter is equal to the multiplier N. A bit of a count value of the counter and a corresponding bit of a first register storing the multiplier N are determined to be equal to each other. Is provided for each bit, and a match detection circuit for activating an output signal when the number of bits matches is provided for the number of bits (M) corresponding to the binary number of the multiplier N, and the first to M-th bits of the counter are provided. A first to an M-th latch circuit that latches an output of the corresponding first to M-th match detection circuits based on a transition edge of the input signal; A first through logic circuits of the M-1 provided corresponding to the respective detection circuits,
The i-th (where i is an integer of 1 to M-1) logic circuit includes an i-th match detection circuit corresponding to an i-th bit (where i is an integer of 1 to M-1) of the counter. An output signal and an output signal of the (i + 1) th latch circuit for latching an output of the (i + 1) th match detection circuit corresponding to the (i + 1) th bit; The i-th output depending on whether the output is active or inactive
The first to M-1 logic circuits are configured to output or mask the output signal of the coincidence detection circuit, and are provided corresponding to the first to Mth latch circuits. A first to M-th current control circuits, wherein the first to M-th current control circuits
An output signal of the latch circuit is input as an activation control signal, and when the control signal is active, a first switch inserted in a charging path between a power supply and an output terminal; and the output terminal and the ground. Are turned off together with the second switch inserted in the discharge path between the first and second switches, and when the activation control signal is inactive, the first and second switches are turned on, and the comparison result from the phase comparator is output. Supply of a constant current from the power supply side to the output terminal based on the signal;
And a first to an M-th current control circuit that performs discharge by a constant current from the output terminal to the ground. The output terminals of the first to the M-th current control circuits are connected in common, and the capacity of the charge pump is A PLL circuit connected to a terminal. 10. A phase comparator, a charge pump for charging or discharging a capacitance based on a comparison result signal from the phase comparator to generate a voltage according to a phase difference, and smoothing a voltage according to the phase difference. A filter that changes an output voltage of the filter into a current, a current control oscillator that changes an oscillation frequency based on a control current, and a frequency divider that inputs and divides an output signal from the voltage control oscillator and outputs the divided signal. Wherein the phase comparator detects a phase difference between an input signal and a signal divided by the frequency divider, and the output signal is obtained by multiplying the frequency of the input signal by N. In a PLL (phase locked loop) circuit, a counter that counts up based on an output signal output from the PLL circuit during one cycle period of the input signal, and when one cycle period of the input signal elapses A circuit for detecting whether or not the count value of the counter in step (b) is equal to the multiple N. A bit of the counter value of the counter and a corresponding bit of a first register storing the multiple N. Are provided for each bit to detect whether or not they match each other, and when they match, a match detection circuit for activating an output signal is provided for the number of bits (M) in which the multiple N is represented in binary, and A first to an M-th latch circuit for latching outputs of the first to the M-th match detection circuits corresponding to the first to the M-th bits based on transition edges of the input signal; Of the first to (M-1) th logic circuits provided in correspondence with the match detection circuits of
The i-th (where i is an integer of 1 to M-1) logic circuit includes an i-th match detection circuit corresponding to an i-th bit (where i is an integer of 1 to M-1) of the counter. An output signal and an output signal of the (i + 1) th latch circuit for latching an output of the (i + 1) th match detection circuit corresponding to the (i + 1) th bit; The i-th output depending on whether the output is active or inactive
The first to M-1 logic circuits are configured to output or mask the output signal of the coincidence detection circuit, and are provided corresponding to the first to Mth latch circuits. A first to M-th current control circuits, wherein the first to M-th current control circuits
An output signal of the latch circuit is input as an activation control signal, and when the control signal is active, a first switch inserted in a charging path between a power supply and an output terminal; and the output terminal and the ground. Are turned off together with the second switch inserted in the discharge path between the first and second switches, and when the activation control signal is inactive, the first and second switches are turned on, and the comparison result from the phase comparator is output. Supply of a constant current from the power supply side to the output terminal based on the signal;
And a first to an M-th current control circuit that performs discharge by a constant current from the output terminal to the ground. The output terminals of the first to the M-th current control circuits are commonly connected, and A PLL circuit supplied as a control current. 11. The phase comparator according to claim 2, wherein said phase comparator comprises a phase-frequency comparator for comparing the phase and frequency of said input signal with the frequency-divided signal of said frequency divider. The lock determination circuit of the PLL circuit according to any one of the above. 12. The phase comparator according to claim 7, wherein said phase comparator comprises a phase-frequency comparator for comparing the phase and frequency of said input signal with the frequency-divided signal of said frequency divider. The PLL circuit according to any one of the above. 13. A multiplication factor of the PLL circuit is variably controlled by a value of an input multiplication factor switching signal, and a value of the first register is varied by the multiplication factor switching signal.
7. The lock determination circuit for a PLL circuit according to claim 6, wherein: 14. The multiplication factor of the PLL circuit is variably controlled by a value of an input multiplication factor switching signal, and the value of the first register is varied by the multiplication factor switching signal. The PLL circuit according to claim 9, wherein: 15. A test method for testing a PLL (Phase Locked Loop) circuit that outputs an output signal obtained by multiplying the frequency of an input signal, wherein the phase-locked loop includes a first counting period defined based on a cycle of the input signal. The number of cycles of the output signal or the signal obtained by dividing the output signal by a predetermined dividing ratio is counted, and the counting result is obtained by multiplying the PLL circuit and the counting period, or the PLL circuit multiplication number and A first value for comparing whether or not the value matches a first value determined from the counting period and the frequency division ratio;
And subtracting from the count result each time the output signal is counted for one cycle over a second count period determined based on a cycle of the input signal after the first count period. A second step of comparing whether the result obtained matches a predetermined second value, and when both of the comparison results of the first and second means show a match, it indicates that the apparatus is in a locked state. And a third step of outputting a judgment signal. 16. A test apparatus for testing, as a device under test, a PLL (Phase Locked Loop) circuit that outputs an output signal obtained by multiplying the frequency of an input signal, wherein the first circuit is determined based on a cycle of the input signal. Over the counting period, the number of cycles of the output signal or the signal obtained by dividing the output signal at a predetermined dividing ratio is counted, and the counting result indicates the multiplication number of the PLL circuit and the counting period or the PLL. A first value for comparing whether or not the value matches a first value determined from the multiplication number of the circuit, the counting period, and the frequency division ratio;
Means for subtracting from the count result each time the output signal is counted for one cycle over a second count period determined based on the cycle of the input signal after the first count period. Second means for comparing whether or not the result obtained matches a predetermined second value; and when both the comparison results of the first and second means show a match, it indicates that the apparatus is in a locked state. And a third means for outputting a judgment signal, wherein the judgment signal is inputted to the test apparatus and used for judging the quality of the PLL circuit.