CN113341232B - High-precision capacitance detection method and detection circuit with self-adaptive measuring range - Google Patents
High-precision capacitance detection method and detection circuit with self-adaptive measuring range Download PDFInfo
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Abstract
The invention discloses a high-precision capacitance detection method and detection circuit with self-adaptive measuring range, wherein the detection circuit comprises: the capacitor detection circuit is used for generating a voltage signal related to the capacitance value of the capacitor to be detected through the constant current characteristic of the reference current source in a certain voltage range; the control circuit is used for generating a clock signal, controlling the periodic charge and discharge of the capacitor to be tested through the frequency division result of the clock signal, converting the voltage signal output by the capacitor detection circuit into a level signal, and providing a quantization starting signal and a quantization ending signal for the quantization circuit; the measuring range detection circuit is used for detecting the signal and the frequency division result output by the control circuit, adjusting the frequency division ratio of the frequency divider and increasing the measuring range of the circuit to finish the measurement of the capacitance to be measured; and the quantization circuit is used for carrying out capacitance quantization based on the time domain and outputting a quantization result. The invention has the characteristics of full integration, high precision and high linearity, and simultaneously combines the measuring range and the measuring precision of the capacitance quantification circuit.
Description
Technical Field
The invention belongs to the technical field of sensing, and relates to a high-precision capacitance detection method and circuit with self-adaptive measuring range.
Background
In recent years, with the continuous development of the internet and the semiconductor industry, the world has gradually moved to the internet of things era of everything interconnection, and by 2018, the internet of things has moved from the industry, and has been popularized to various fields such as home appliances, medical treatment, transportation, and logistics. And the fly-stage capacitive sensor is used as one of the most critical supporting technologies, and is driven by great force required by the market. A capacitive sensor is a type of conversion device that converts a physical quantity to be measured into a change in capacitance. Because of its advantages of simple structure, high sensitivity, etc., it has been widely used in various fields such as capacitive pressure sensors for pressure detection, capacitive fingerprint sensors for biometric identification, and capacitive accelerometers for medical detection.
The traditional capacitance detection mode mainly comprises frequency type, switch capacitance type, resistance discharge type and other detection methods. For the frequency type detection method, the detection precision cannot reach the femtofarad level. For the switched capacitor detection method, when the capacitor is quantized, the conversion from the capacitor to the voltage is firstly completed, and then the ADC is utilized to complete the conversion of the voltage image digital signal; but the accuracy of the switched capacitor circuit and noise etc. limit the resolution of the capacitor to be measured. The resistor discharge type circuit generally charges a capacitor, and finally discharges through an off-chip accurate resistor, and then quantifies discharge time. Although the circuit can reach higher precision, as the capacitor discharges through the resistor to form an exponential waveform, the signal needs to be subjected to linearization processing during quantization, so that the algorithm is complex, the corresponding quantization rate and the integration level of the quantization circuit are low, and the precision requirement of the quantization mode on the time measurement circuit is higher. The drawbacks of the above-described circuits themselves limit the further development of high-precision capacitive sensors. In addition, the circuit has a relationship between the measurement range and the quantization accuracy, and the measurement range is basically fixed under the same quantization accuracy. Once the capacitance to be measured exceeds the preset measuring range, the measuring circuits cannot finish the measurement or the quantization precision needs to be reduced to finish the measurement.
Disclosure of Invention
In order to solve the problems, the embodiment of the invention provides a range self-adaptive high-precision capacitance detection circuit which has the characteristics of full integration, high precision and high linearity, simultaneously takes the measurement range and the measurement precision of a capacitance quantification circuit into consideration, and solves the problems existing in the prior art.
Another object of the embodiment of the invention is to provide a high-precision capacitance detection method with adaptive measuring range.
The invention adopts the technical scheme that the high-precision capacitance detection circuit with the self-adaptive measuring range comprises a capacitance detection circuit, a control circuit, a measuring range detection circuit and a quantization circuit;
the capacitance detection circuit is used for generating a voltage signal related to the capacitance value of the capacitor to be detected, namely a signal S2, through the constant current characteristic of the reference current source in a certain voltage range;
the control circuit is used for generating a clock signal, namely a signal S5, controlling the periodic charge and discharge of the capacitor to be tested through the frequency division result S1 of the clock signal, and converting the voltage signal output by the capacitor detection circuit into a level signal, namely a signal S3; providing a start quantization and end quantization signal to the quantization circuit according to the signal S3;
the measuring range detection circuit is used for detecting a signal S3 and a frequency division result S1 output by the control circuit, judging whether the signal S3 is in a high level temporarily when the frequency division result S1 falls, and quantizing the capacitor to be detected by using the current measuring range if the signal S3 is in the high level; if the signal S3 is low level, indicating that the capacitance to be measured exceeds a preset measuring range, carrying out shift registering on the current output signal S6 of the measuring range detection circuit, outputting the output signal S6, sending the output signal S6 to the IN1 end of the frequency divider, adjusting the frequency dividing ratio of the frequency divider, and increasing the measuring range of the circuit to finish the measurement of the capacitance to be measured;
the quantization circuit is used for generating a quantization signal according to the formulaDetermining a capacitance value of a capacitor to be measured, wherein C represents the capacitance value of the capacitor to be measured, I represents a discharge current generated by a reference current source, deltaV represents a discharge voltage of the capacitor to be measured, and Deltat represents the time for which the capacitor is discharged; and carrying out capacitance quantization based on the time domain and outputting a quantization result.
Further, the capacitance detection circuit comprises a power supply VDD, a selector, a PMOS tube and a reference current source;
the power supply VDD is used for charging the capacitor to be tested, the power supply VDD is connected to two ends of the capacitor to be tested, and one end of the capacitor to be tested, which is connected with the negative electrode of the power supply VDD, is grounded;
the PMOS tube is used for controlling periodic charge and discharge of the capacitor to be tested according to the frequency division result S1; the PMOS tube is connected to a connecting loop of the capacitor to be tested and the power supply VDD, and the frequency division result S1 is input to the gate end of the PMOS tube to control the on and off of the PMOS tube;
the alternative selector is used for determining whether to connect the reference current source to the power supply VDD or connect the reference current source to the capacitor to be tested according to the frequency division result S1; the frequency division result S1 is input to the input terminal of the alternative selector, and the output terminal of the alternative selector outputs the voltage signal S2.
Further, the frequency division result S1 is a periodic square wave, and the time of the high and low levels of the frequency division result S1 is determined by the system clock signal S5 and the frequency division ratio.
Further, the control circuit comprises a clock generation circuit, a comparator, a rising edge detector, a frequency divider and a reference voltage source;
the clock generation circuit is used for generating a system clock signal, namely a signal S5, and inputting the signal S5 to the control end of the rising edge detector and the input end of the frequency divider respectively;
the comparator is used for converting the signal S2 into a signal S3 and inputting the signal S3 into the rising edge detector; the inverting input end of the comparator is connected with the output end of the capacitance detection circuit, and the output end of the comparator is connected with the input end of the rising edge detector;
the rising edge detector is used for detecting the output of the comparator, and when the signal S3 output by the comparator jumps from low level to high level, the rising edge detector outputs a rectangular pulse, namely a signal S4, on the next rising edge of the signal S5 temporarily;
the reference voltage source is used for calibrating a discharge interval of the capacitor to be measured and is connected with the non-inverting input end of the comparator;
the frequency divider comprises delay chain modules formed by cascade connection of delay units, wherein the delay units in the middle are connected end to end except the first delay unit and the last delay unit, the output of each delay unit is connected with the input of the next delay unit, the output section of each delay unit is connected with a D trigger, a signal S3 is input to the input end of the first delay unit of the delay chain module, and a signal S4 is input to the clock end of each D trigger; when the rising edge of the signal S4 comes, the D trigger sends the level output by the corresponding delay unit to the Q end of the signal S4, the Q of the D trigger of the frequency divider is not connected back to the D end, 1 frequency divider is formed, the input signal S5 is subjected to 2 frequency division, and the Q end outputs the frequency division result, namely S1.
Further, during the charging period of the capacitor to be tested, when the signal S2 is the power supply VDD, the signal S3 is at a low level, during the discharging period of the capacitor to be tested, the signal S2 is continuously reduced along with the reduction of the capacitor voltage, and when the signal S2 level is slightly smaller than the VREF, the output signal S3 of the comparator is turned from a low level to a high level, and the end of the discharging of the capacitor to be tested is marked.
Further, the output signal S6 of the range detection circuit is a binary signal with a bit width of M, and is represented by a binary number of [ M-1,0] bits, and when a certain bit is 1, the corresponding bit is high level, and when a certain bit is 0, the corresponding bit is low level; the signal S6 has M bits, M switches can be controlled, a switch is arranged on a delay unit cascade node behind the lowest bit S6[0] of the signal S6, each bit of the signal S6 is connected to a corresponding switch, when one bit of the signal S6 is 0, the corresponding switch is opened, and when the bit of the signal S6 is 1, the corresponding switch is closed; when the circuit is powered on, the preset frequency division ratio is determined by the number of D flip-flops before S6[ 0]; when the circuit is of a preset range, the value of the signal S6 is S6= [00 … ], namely, only the lowest bit S6[0] of the signal S6 is 1, and the corresponding switch is closed; the other bits are all 0, and the corresponding switches are all disconnected; at this time, the D trigger corresponding to the switch controlled by S6[0] outputs the frequency division result S1; and when the circuit adjusts the measuring range, the bit with 1 in the value of the signal S6 is moved forward by one bit, 1D flip-flop is added in frequency division, the frequency division ratio is doubled, and the measuring range of the circuit is doubled.
Further, if the output signal S6 of the span detection circuit has been shifted to the last position and measurement cannot be completed, the output signal S7 of the span detection circuit is 1, which indicates that the capacitance to be measured has exceeded the maximum span of the circuit; otherwise, the output signal S7 of the span detection circuit is always 0.
Further, the quantization circuit comprises a counter, a delay chain module and an operation unit;
the counter has 3 input signals in total, wherein a frequency division result S1 and a signal S3 are control signals of the counter, a signal S5 is an input signal of the counter, when the frequency division result S1 is in a low level, the counter stops counting, when the frequency division result S1 is in a high level and the signal S3 is in a low level, the counter starts counting, and at the moment, the corresponding circuit state is that a capacitor starts discharging, but the capacitor does not discharge to a calibration voltage yet; when the signal S3 is high, indicating that the comparator has flipped, at which time the counter stops counting and outputs the count result N of the clock cycle;
the output of each D trigger of the delay chain module is connected to the input of the operation unit;
the operation unit is configured to calculate, according to a formula Δt=nt-NT, a time Δt during which the capacitor to be measured discharges, where T represents a clock period of the clock generating circuit, n represents a number of "1" levels in all D flip-flops in the delay chain in an interval between rising edges of the signal S3 and the signal S4, and T represents a delay of the delay unit.
Further, the comparator has an accuracy of 0.1mV.
The detection method of the range self-adaptive high-precision capacitance detection circuit adopts the range self-adaptive high-precision capacitance detection circuit, and specifically comprises the following steps of:
step 1: the circuit is powered on with an initial frequency division ratio, and the S6 value is S6= [00 … 1];
step 2: when the capacitor to be measured is quantized for the first time after power-on, the range detection circuit judges whether a temporary signal S3 coming from the falling edge of a frequency division result S1 is of a low level or not, and if not, the capacitor to be measured is quantized by using the current range; if yes, for the shift register of the S6 signal, judging whether the time signal S3 from the falling edge of the frequency division result S1 is at a low level or not after each shift register, if not, quantifying by using the current measuring range; if yes, continuing to shift and register the S6 signal; in the process of shift registering the S6 signal, whether S6 reaches S6= [1 … ] needs to be judged;
step 3: if the current range is reached, S6= [1 … 00] and whether the time signal S3 is at a low level when the falling edge of the frequency division result S1 comes is continuously judged, and if not, the current range is used for quantization; if so, the maximum range is exceeded, a flag signal S7 is given.
The beneficial effects of the invention are as follows:
the high-precision quantization circuit with the self-adaptive measuring range adopts an on-chip integrated reference current source discharging mode, and only needs to carry out simple linear operation when the variable quantity of the capacitor is quantized, so that the problem of complex algorithm of the traditional quantization circuit is solved, and the complexity of the quantization algorithm is reduced; meanwhile, other external elements are not needed, so that the integration level of the capacitance quantization circuit is improved, and the size of the quantization circuit is greatly reduced.
The quantization range of the circuit is determined by the frequency division ratio of the frequency divider and the maximum count value of the counter, the quantization precision is determined by the precision of the delay unit of the delay chain, and the problem of compromise between the measurement range and the precision does not exist in the maximum measurement range, so that the relationship between the quantization range and the quantization precision is solved. The measuring range can be adjusted in a self-adaptive mode, the measuring range of the circuit is not increased at the cost of quantization precision in the adjusting process, and the circuit can still finish measuring the capacitance to be measured even if the measuring range exceeds the preset measuring range of the circuit. Meanwhile, when the capacitor quantization is carried out, the quantization can be rapidly completed due to the simpler quantization algorithm.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic block diagram of a quantization method according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a capacitance detection circuit according to an embodiment of the present invention.
Fig. 3 is a diagram showing a control circuit and a range detection circuit according to an embodiment of the present invention.
Fig. 4 shows a configuration of a frequency divider according to an embodiment of the present invention.
Fig. 5 is a logic block diagram of a conditioning circuit in an embodiment of the present invention.
Fig. 6 is a block diagram of a quantization circuit in an embodiment of the present invention.
FIG. 7 is a timing waveform diagram of each key signal during a single measurement according to an embodiment of the present invention.
Fig. 8a-8d are simulation results of an embodiment of the present invention.
Detailed Description
The technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The basic principle of the circuit is as follows: according to the charge-discharge principle of the capacitor,according to the method, under the condition that the discharge current I of the capacitor is constant, the discharge time delta t of the capacitor and the capacitance value of the capacitor C are linearly related by setting the discharge voltage delta V of the capacitor as a fixed interval, so that the linearity of a quantization result is greatly improved, the complexity of the capacitor in quantization is also reduced, the circuits can be realized in an integrated circuit without external connection with other components, the volume of the quantization circuit is reduced, and the integration level of the quantization circuit is improved. When the circuit quantifies the capacitor to be measured, the current measuring range is detected, and if the quantification cannot be completed, the quantification of the capacitor to be measured is completed by adjusting the measuring range of the circuit.
In the case of example 1,
a range self-adaptive high-precision capacitance detection circuit is shown in fig. 1, and comprises a capacitance detection circuit, a control circuit, a range detection circuit and a quantization circuit.
The capacitance detection circuit is used for detecting the voltage of the capacitor to be detected (Ctest), generating a voltage signal related to the capacitance value of the capacitor to be detected, namely a signal S2, through the constant current characteristic of the reference current source (Iref) in a certain voltage range, and transmitting the voltage signal to the control circuit.
And the control circuit is used for generating a clock signal, a charge and discharge control signal and starting and ending signals of the quantization circuit. The clock generation circuit generates a clock signal, controls the periodic charge and discharge of the capacitor to be detected through the frequency division result S1 of the clock signal, and converts the voltage signal output by the capacitor detection circuit into a level signal, namely a signal S3; the quantization circuit is provided with a start quantization and an end quantization signal in accordance with the signal S3.
The measuring range detection circuit is used for detecting a signal S3 and a frequency division result S1 output by the control circuit, judging whether the signal S3 is in a high level or not in time when the falling edge of the frequency division result S1 comes (namely, when each frequency division period is ended), if so, indicating that the current measuring range can finish the measurement of the capacitance to be measured, and quantifying the capacitance to be measured by using the current measuring range; if the signal S3 is low, it indicates that the capacitor to be measured exceeds the preset range, that is, the reference current source fails to discharge the capacitor to be measured to the calibration voltage, the current output signal S6 of the range detection circuit is output after being shifted and registered, the output signal S6 is sent to the IN1 end of the frequency divider, the frequency division ratio of the frequency divider is adjusted, the discharge time of the capacitor IN the single measurement process is increased, so that the reference current source can discharge the capacitor to be measured to the calibration voltage, and the range of the circuit is increased to complete the measurement of the capacitor to be measured. The frequency divider generates a frequency division result S1 according to the signal S5, and can adjust the frequency division ratio according to the output signal (S6) of the range detection circuit.
Quantization circuit for generating a quantization signal according to a formulaDetermining a capacitance value of a capacitor to be measured, wherein C represents the capacitance value of the capacitor to be measured, I represents a discharge current generated by a reference current source, deltaV represents a discharge voltage of the capacitor to be measured, and Deltat represents the time for which the capacitor is discharged; and finally outputting the quantized result. The time of capacitor discharge is determined by measuring the time interval of two control signals, binary data is output, conversion to digital signals is completed, and DOUT is the final quantized result; the adopted capacitance quantification mode is performed based on the time domain, and the quantityThe range detection circuit is tightly matched with a specific capacitance quantification mode, so that the function of automatic range adjustment is realized.
Referring to fig. 2, the capacitance detection circuit includes a power supply VDD, an alternative selector (MUX 2), a PMOS transistor, and a reference current source (Iref) that generates a reference current of 1uA (microampere).
The power supply VDD is used for charging the capacitor to be tested, the power supply VDD is connected to two ends of the capacitor to be tested, and one end of the capacitor to be tested, which is connected with the negative electrode of the power supply VDD, is grounded;
the PMOS tube is used for controlling periodic charge and discharge of the capacitor to be tested according to the frequency division result S1; the PMOS tube is connected to a connecting loop of the capacitor to be tested and the power supply VDD, and the frequency division result S1 is input to the gate end of the PMOS tube to control the on and off of the PMOS tube;
the alternative selector is used for determining whether to connect the reference current source to the power supply VDD or connect the reference current source to the capacitor to be tested according to the frequency division result S1; the frequency division result S1 is input to the input terminal of the alternative selector, and the output terminal of the alternative selector outputs the voltage signal S2. The A path of the MUX2 is used for connecting a reference current source to a capacitor to be tested, the B path of the MUX2 is used for connecting the reference current source to a power supply VDD, and the frequency division result S1 is connected with a control end (S) of the MUX 2.
The frequency division result S1 is a periodic square wave, which is divided by the system clock signal S5, and the time of the high and low levels is determined by the system clock signal S5 and the frequency division ratio, see fig. 7. When the frequency division result S1 is low level, the PMOS tube is started, the MUX2 selects the VDD end, and the power supply VDD is directly used for completing charging, so the signal S2 is always the voltage of the power supply VDD; when the frequency division result S1 is at a high level, the PMOS tube is turned off, the MUX2 selects a capacitor end to be measured, the signal S2 is output voltage of the capacitor to be measured, the capacitor to be measured is discharged by using a constant current source to ensure that the discharge current of the capacitor to be measured is constant, the voltage on the capacitor to be measured is linearly reduced, that is, the slope of the signal S2 is fixed, and the slopes of the voltage signals are different according to capacitance values of different capacitors. When the capacitor is charged, the reference current source (Iref) is connected to the power supply voltage, although certain static power consumption is increased, the voltage at two ends of the current source cannot be changed when the capacitor to be tested is converted into a discharging state, the working state of the MOS tube in the current source is ensured not to be changed, the constant discharging current is ensured, and the phenomenon that the constant current characteristic of the reference current source is changed due to the working state conversion of the MOS tube is avoided, so that the nonlinearity of a quantification result is introduced is avoided.
Referring to fig. 3, the control circuit includes a clock generation circuit, a comparator, a rising edge detector (CLK), a frequency divider, and a reference voltage source (VREF).
The clock generation circuit is used for generating a system clock signal (a signal S5) and inputting the signal S5 to the control end of the rising edge detector and the input end of the frequency divider respectively.
A comparator for converting the signal S2 into a signal S3 and inputting the signal S3 into the rising edge detector; the inverting input end of the comparator is connected with the output end of the capacitance detection circuit, and the output end of the comparator is connected with the input end of the rising edge detector; during the charging period of the capacitor to be tested, when the signal S2 is the power supply VDD, the signal S3 is low level, during the discharging period of the capacitor to be tested, the signal S2 is continuously reduced along with the reduction of the capacitor voltage, and when the signal S2 level is slightly smaller than VREF, the output signal S3 of the comparator is turned from low level to high level to mark the end of the discharging of the capacitor to be tested. In some embodiments, the accuracy of the comparator is 0.1mV, the discharge interval of the capacitor is guaranteed to be 1V, and the higher the accuracy of the comparator is, the better.
And a rising edge detector for detecting an output of the comparator, wherein when the signal S3 outputted by the comparator jumps from a low level to a high level, a rectangular pulse, i.e. a signal S4, is outputted from the rising edge detector on the next rising edge of the signal S5.
The reference voltage source is used for calibrating the discharge interval of the capacitor to be measured and is connected with the non-inverting input end of the comparator.
The frequency divider comprises delay chain modules formed by cascade connection of delay units, wherein the delay units in the middle are connected end to end except the first delay unit and the last delay unit, the output of each delay unit is connected with the input of the next delay unit, the output section of each delay unit is connected with a D trigger, a signal S3 is input to the input end of the first delay unit of the delay chain module, and a signal S4 is input to the clock end of each D trigger; in the signalS4, when the rising edge comes, the D trigger sends the level output by the corresponding delay unit to the Q end of the D trigger, and the Q of the D trigger of the frequency divider is not connected back to the D end to form 1 frequency divider, so that the function of dividing frequency by two is completed; dividing the input signal S5 by 2, and outputting a frequency division result, namely S1, by a Q end; refer to fig. 4.m cell cascades can realize 2 m And the output of each D trigger of the delay chain module is connected to the input of the operation unit.
The output signal S6 of the range detection circuit is a binary signal with the bit width of M, and is represented by binary numbers of [ M-1,0] bits, when a certain bit is 1, the corresponding bit is high level, and when the certain bit is 0, the corresponding bit is low level; the signal S6 has M bits in total, and can control M switches. Referring to FIG. 4, a switch is provided on a cascade node of delay cells following the lowest bit S6[0] of the signal S6, each bit (0-M-1) of the signal S6 is connected to a corresponding switch, when a certain bit of the signal S6 is 0, the corresponding switch is opened, and when the bit is 1, the corresponding switch is closed; when the circuit is powered on, the preset frequency division ratio is determined by the number of D flip-flops before S6[ 0]; when the circuit is of a preset range, the value of the signal S6 is S6= [00 … ], namely, only the lowest bit S6[0] of the signal S6 is 1, and the corresponding switch is closed; other bits (such as S6[1], S6[2] … S6[ M-1 ]) are all 0, and the corresponding switches are all opened; at this time, the D trigger corresponding to the switch controlled by S6[0] outputs the frequency division result S1; each time the circuit adjusts the measuring range, the bit with 1 in the value of the signal S6 is shifted forward by one bit, and the circuit is supposed to adjust the measuring range only once, that is, the value of S6 is s6= [00 … ] at this time, the D flip-flop corresponding to the switch controlled by S6[1] outputs the signal S1, as can be seen from fig. 4, more than 1D flip-flop participates in frequency division, so the frequency division ratio is doubled, and the measuring range of the circuit is doubled. The output of S6 shifts each time, a D trigger is added to the frequency division, the frequency division ratio is doubled, the high level duration of the signal S1 after the frequency division is longer, the discharging time of the reference current source is longer, the reference power source can discharge a larger capacitor to the calibration voltage, the larger the capacitor which can be measured by the circuit is, and the frequency division module and the range detection circuit jointly complete the function of automatically adjusting the range of the circuit.
In the above process, the signal S7 is always 0, if the value of S6 is s6= [10 … 00], that is, the last bit has been shifted, and measurement cannot be completed, the output signal S7 is 1, which indicates that the capacitance to be measured has exceeded the maximum range of the circuit; if the capacitance to be measured exceeds the preset range, the reference current source can not discharge the capacitance to the calibration voltage at the moment when the frequency division signal falls, and the output of the comparator can not be turned from low to high.
Referring to fig. 6, the quantization circuit includes a Counter (Counter), a Delay chain module (Delay line), and an arithmetic unit (ALU).
The counter has 3 input signals in total, wherein a frequency division result S1 and a signal S3 are control signals of the counter, a signal S5 is an input signal of the counter, when the frequency division result S1 is in a low level, the counter stops counting, when the frequency division result S1 is in a high level and the signal S3 is in a low level, the counter starts counting, and at the moment, the corresponding circuit state is that a capacitor starts discharging, but the capacitor does not discharge to a calibration voltage yet; when the signal S3 is at a high level, it indicates that the comparator has flipped, and at this time, the counter stops counting and outputs a count result N of the clock period, and the count result is multiplied by the period of the clock signal S5, so that the rough time elapsed from the start of discharging to the end of discharging of the whole capacitor can be obtained, and the rough quantization is completed. Since the period of the clock generation circuit is fixed, each period of the signal S5 is also fixed. However, the output rising edge of the comparator is not substantially aligned with the edge of S5 at all times, and thus employing only the counter output as the quantization result brings about a significant error.
The output of each D trigger of the delay chain module is connected to the input of an operation unit, and the operation unit reads the counting result of the counter and the result of the delay unit and then carries out operation;
and the operation unit is used for calculating the time deltat of the discharge of the capacitor to be measured according to a formula deltat=nt-NT, wherein T represents the clock period of the clock generation circuit, n represents the number of the level of 1 in all D triggers in the delay chain in the interval between the rising edges of the signal S3 and the signal S4, and T represents the delay of the delay unit.
Referring to fig. 7, S1 is a frequency division result of S5, when S1 is low, the capacitor is charged to VDD, S1 becomes high at time t1, the capacitor starts to discharge, and the counter starts to count. At time t2, the capacitor discharges to 0.8V, the output result of the comparator (S3) is inverted, and at this time, the counter is controlled to stop counting, and as can be seen from fig. 7, the quantization result of the counter is the time period of t1-t3, but the actual discharge time of the capacitor to be measured is the time period of t1-t2, so the time period of t2-t3 is the quantization error introduced by coarse quantization.
After the rising edge of S3, the signal S3 is transmitted inside the delay chain, and the output of one delay unit is high level every time the time interval of one delay unit passes. During the time interval between the rising edges of the signal S3 and the signal S4, the output of only a limited number of delay cells will go high, and the output of the other delay cells will remain 0. After the rising edge of the signal S4 comes, the arithmetic unit ALU reads out the output of the D flip-flop. The time interval between the rising edges of the signal S3 and the signal S4 can be obtained by counting the number of the level "1" in all the D flip-flops.
As can be seen from fig. 7, the result of subtracting the time period t2-t3 from the quantized result (time period t1-t 3) of the counter is the actual discharge time of the capacitor. At time t2, the rising edge of the S3 signal comes, which starts to propagate in the delay chain. At time t3, the rising edge detector in the control module outputs a rectangular pulse, namely the waveform of a signal S4, the rising edge of the signal is used as a control signal of a D trigger of a delay chain, the number of '1' in multi-bit output of the delay chain is read out at time t3 and is n, t represents the delay of a delay unit, and then the time period t2-t3 is as follows:
t3-t2＝nt
assuming that the capacitor is charged to 1.8V during charging, the comparator has a non-inverting input voltage of 0.8V and the discharge current generated by the reference current source is 1uA. The quantization result is:
wherein F represents the unit Farad of the capacitance.
The delay chain module is internally formed by a delay unit and a D trigger, and is used for finishing the measurement of the rising edge time interval of the S3 and S4 signals, and DOUT is the final capacitance quantization result. The quantization circuit adopts a mode of combining fine quantization and coarse quantization, the coarse quantization is completed by a counter, the fine quantization is completed by a delay chain module, and the quantization range and the quantization precision can be considered; the operation unit completes binary conversion according to the coarse quantization and the fine quantization results, and finally completes the function of converting the capacitance value of the capacitor to be tested into binary numbers. The shorter the delay of the delay unit, the higher the accuracy can be achieved, the quantization range is determined by the time that S1 is in high level, and the longer the duration of the high level is, the longer the discharge time of the constant current source is, and the larger the quantization range of the circuit is. The accuracy of the circuit is determined by the delay of the delay unit, and the quantization range of the circuit is determined by the time when S1 is high, so that the two parameters are not in a mutually restricted relation, and the quantization range and the quantization accuracy can be simultaneously achieved.
Referring to FIGS. 8a-8d, abscissa C test The capacitance value of the capacitor to be measured is the ordinate C mear And the simulation result corresponding to the quantization circuit is obtained. Fig. 8a is a simulation result of each increase of 1fF in the capacitance value of the capacitor to be measured when the body value of the capacitor to be measured is 310 fF. Fig. 8b is a simulation result of each increase of 1fF in the capacitance value of the capacitor to be measured when the body value of the capacitor to be measured is 1005 fF. Fig. 8c is a simulation result of each increase of the capacitance value of the capacitor to be measured by 10fF when the body value of the capacitor to be measured is 300 fF. Fig. 8d shows simulation results of each increase of 100fF in the capacitance value of the capacitor to be measured when the body value of the capacitor to be measured is 300 fF. From the simulation result, the quantization circuit can still reach the quantization precision of 1fF even if the body values of the capacitors to be measured are different. Meanwhile, as can be seen from the simulation results of fig. 8c and 8d, the circuit can accurately complete measurement even if the capacitance value of the capacitor to be measured is greatly changed. In consideration of non-ideal factors, the simulation result in the graph has extremely small quantization offset with the actual value of the capacitor to be measured, the offset does not influence the quantization linearity, and in the use of a later product, the translation calibration with the actual value can be realized through single-point calibration in the initialization process. In conclusion, when the quantization circuit is used for capacitance measurement, the quantization accuracy of 1fF can be achieved, and the quantization circuit can simultaneously measureThe result of the chemical conversion has better linearity in a large range.
The maximum range of the frequency divider is determined by the number of frequency dividers which are additionally added after the frequency divider circuit ensures initial frequency division, and the maximum range is doubled every time the frequency divider is added, and the maximum range is 12pF; while ensuring that the quantization accuracy is in the range of 0-1.5pF. The range of the existing detection circuit is 0-1.5pF, and the quantization accuracy is 1fF.
In the case of example 2,
as shown in FIG. 5, the detection circuit is adopted, and the method specifically comprises the following steps:
step 1: the circuit is powered on with an initial frequency division ratio, and the S6 value is S6= [00 … 1];
step 2: when the capacitor to be measured is quantized for the first time after power-on, the range detection circuit judges whether a temporary signal S3 coming from the falling edge of a frequency division result S1 is of a low level or not, and if not, the capacitor to be measured is quantized by using the current range; if yes, for the shift register of the S6 signal, judging whether the time signal S3 from the falling edge of the frequency division result S1 is at a low level or not after each shift register, if not, quantifying by using the current measuring range; if yes, continuing to shift and register the S6 signal; in the process of shift registering the S6 signal, whether S6 reaches S6= [1 … ] needs to be judged;
step 3: if the current range is reached, S6= [1 … 00] and whether the time signal S3 is at a low level when the falling edge of the frequency division result S1 comes is continuously judged, and if not, the current range is used for quantization; if so, the maximum range is exceeded, a flag signal S7 is given.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.
Claims (9)
1. The high-precision capacitance detection circuit with the self-adaptive range is characterized by comprising a capacitance detection circuit, a control circuit, a range detection circuit and a quantization circuit;
the capacitance detection circuit is used for generating a voltage signal related to the capacitance value of the capacitor to be detected, namely a signal S2, through the constant current characteristic of the reference current source in a certain voltage range;
the control circuit is used for generating a clock signal, namely a signal S5, controlling the periodic charge and discharge of the capacitor to be tested through the frequency division result S1 of the clock signal, and converting the voltage signal output by the capacitor detection circuit into a level signal, namely a signal S3; providing a start quantization and end quantization signal to the quantization circuit according to the signal S3;
the measuring range detection circuit is used for detecting a signal S3 and a frequency division result S1 output by the control circuit, judging whether the signal S3 is in a high level temporarily when the frequency division result S1 falls, and quantizing the capacitor to be detected by using the current measuring range if the signal S3 is in the high level; if the signal S3 is low level, indicating that the capacitance to be measured exceeds a preset measuring range, carrying out shift registering on the current output signal S6 of the measuring range detection circuit, outputting the output signal S6, sending the output signal S6 to the IN1 end of the frequency divider, adjusting the frequency dividing ratio of the frequency divider, and increasing the measuring range of the circuit to finish the measurement of the capacitance to be measured;
the quantization circuit is used for generating a quantization signal according to the formulaDetermining the capacitance value of the capacitor to be measured, wherein C represents the capacitance value of the capacitor to be measured,Irepresents the discharge current, delta, generated by the reference current sourceVRepresents the discharge voltage delta of the capacitor to be measuredtRepresenting the time that the capacitor has elapsed to discharge; carrying out capacitance quantization based on a time domain and outputting a quantization result;
the capacitance detection circuit includes:
the PMOS tube is used for controlling periodic charge and discharge of the capacitor to be tested according to the frequency division result S1;
the alternative selector is used for determining whether to connect the reference current source to the power supply VDD or connect the reference current source to the capacitor to be tested according to the frequency division result S1; the frequency division result S1 is input to the input end of the alternative selector, and the output end of the alternative selector outputs a voltage signal S2;
the control circuit comprises a clock generation circuit, a comparator, a rising edge detector, a frequency divider and a reference voltage source;
the clock generation circuit is used for generating a system clock signal, namely a signal S5, and inputting the signal S5 to the control end of the rising edge detector and the input end of the frequency divider respectively;
the comparator is used for converting the signal S2 into a signal S3 and inputting the signal S3 into the rising edge detector; the inverting input end of the comparator is connected with the output end of the capacitance detection circuit, and the output end of the comparator is connected with the input end of the rising edge detector;
the rising edge detector is used for detecting the output of the comparator, and when the signal S3 output by the comparator jumps from low level to high level, the rising edge detector outputs a rectangular pulse, namely a signal S4, on the next rising edge of the signal S5 temporarily;
the reference voltage source is used for calibrating a discharge interval of the capacitor to be measured and is connected with the non-inverting input end of the comparator;
the frequency divider comprises delay chain modules formed by cascade connection of delay units, wherein the delay units in the middle are connected end to end except the first delay unit and the last delay unit, the output of each delay unit is connected with the input of the next delay unit, the output end of each delay unit is connected with a D trigger, a signal S3 is input to the input end of the first delay unit of the delay chain module, and a signal S4 is input to the clock end of each D trigger; when the rising edge of the signal S4 comes, the D trigger sends the level output by the corresponding delay unit to the Q end of the signal S4, the Q of the D trigger of the frequency divider is not connected back to the D end to form 1 frequency divider, the input signal S5 is subjected to 2 frequency division, and the Q end outputs a frequency division result S1;
the quantization circuit comprises an operation unit for calculating the time Δt that the capacitor to be measured discharges according to the formula Δt=nt-NT, wherein T represents the clock period of the clock generation circuit, n represents the number of "1" levels in all D flip-flops in the delay chain in the interval between the rising edges of the signal S3 and the signal S4, and T represents the delay of the delay unit.
2. The range-adaptive high-precision capacitance detection circuit according to claim 1, further comprising a power supply VDD; the power supply VDD is used for charging the capacitor to be tested, the power supply VDD is connected to two ends of the capacitor to be tested, and one end of the capacitor to be tested, which is connected with the negative electrode of the power supply VDD, is grounded;
the PMOS tube is connected to the connecting loop of the capacitor to be tested and the power supply VDD, and the frequency division result S1 is input to the gate end of the PMOS tube to control the on and off of the PMOS tube.
3. The range-adaptive high-precision capacitance detecting circuit according to claim 1, wherein the frequency dividing result S1 is a periodic square wave, and the time of the high and low levels of the frequency dividing result S1 is determined by the system clock signal S5 and the frequency dividing ratio.
4. The range-adaptive high-precision capacitance detection circuit according to claim 1, wherein the signal S3 is low when the signal S2 is the power supply VDD during the charging period of the capacitor to be detected, the signal S2 is continuously reduced as the voltage of the capacitor to be detected is reduced during the discharging period of the capacitor to be detected, and the output signal S3 of the comparator is turned from low to high when the level of the signal S2 is smaller than VREF, thereby indicating the end of the discharging period of the capacitor to be detected.
5. The range-adaptive high-precision capacitance detection circuit according to claim 1, wherein the output signal S6 of the range detection circuit is a binary signal with a bit width of M, and is represented by a binary number of [ M-1,0] bits, and when a certain bit is 1, the corresponding bit is high, and when a certain bit is 0, the corresponding bit is low; the signal S6 has M bits, M switches can be controlled, a switch is arranged on a delay unit cascade node behind the lowest bit S6[0] of the signal S6, each bit of the signal S6 is connected to a corresponding switch, and when one bit of the signal S6 is 0, the corresponding switch is disconnected; when the voltage is 1, the corresponding switch is closed; when the circuit is powered on, the preset frequency division ratio is determined by the number of D flip-flops before S6[ 0]; when the circuit is of a preset range, the value of the signal S6 is S6= [00 … ], namely, only the lowest bit S6[0] of the signal S6 is 1, and the corresponding switch is closed; the other bits are all 0, and the corresponding switches are all disconnected; at this time, the D trigger corresponding to the switch controlled by S6[0] outputs the frequency division result S1; and when the circuit adjusts the measuring range, the bit with 1 in the value of the signal S6 is moved forward by one bit, 1D flip-flop is added in frequency division, the frequency division ratio is doubled, and the measuring range of the circuit is doubled.
6. The adaptive ranging high-precision capacitance detecting circuit according to claim 5, wherein the output signal S6 of the ranging detection circuit has been shifted to the last position and the measurement cannot be completed, the output signal S7 of the ranging detection circuit is 1, which indicates that the capacitance to be detected has exceeded the maximum range of the circuit; otherwise, the output signal S7 of the span detection circuit is always 0.
7. The range-adaptive high-precision capacitance detection circuit according to claim 1, wherein the quantization circuit further comprises a counter and a delay chain module;
the counter has 3 input signals in total, wherein a frequency division result S1 and a signal S3 are control signals of the counter, a signal S5 is an input signal of the counter, when the frequency division result S1 is in a low level, the counter stops counting, when the frequency division result S1 is in a high level and the signal S3 is in a low level, the counter starts counting, and at the moment, the corresponding circuit state is that a capacitor starts discharging, but the capacitor does not discharge to a calibration voltage yet; when the signal S3 is high, indicating that the comparator has flipped, at which time the counter stops counting and outputs the count result N of the clock cycle;
the output of each D trigger of the delay chain module is connected to the input of the operation unit.
8. The range-adaptive high-precision capacitance detection circuit according to claim 1, wherein the comparator has a precision of 0.1mV.
9. A detection method of a range-adaptive high-precision capacitance detection circuit, which is characterized by adopting the range-adaptive high-precision capacitance detection circuit according to any one of claims 1-8, and specifically comprising the following steps:
step 1: the circuit is powered on with an initial frequency division ratio, and the S6 value is S6= [00 … 1];
step 2: when the capacitor to be measured is quantized for the first time after power-on, the range detection circuit judges whether a temporary signal S3 coming from the falling edge of a frequency division result S1 is of a low level or not, and if not, the capacitor to be measured is quantized by using the current range; if yes, for the shift register of the S6 signal, judging whether the time signal S3 from the falling edge of the frequency division result S1 is at a low level or not after each shift register, if not, quantifying by using the current measuring range; if yes, continuing to shift and register the S6 signal; in the process of shift registering the S6 signal, whether S6 reaches S6= [1 … ] needs to be judged;
step 3: if the current range is reached, S6= [1 … 00] and whether the time signal S3 is at a low level when the falling edge of the frequency division result S1 comes is continuously judged, and if not, the current range is used for quantization; if so, the maximum range is exceeded, a flag signal S7 is given.
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