CN113341232B - High-precision capacitance detection method and detection circuit with self-adaptive measuring range - Google Patents

Abstract

The invention discloses a high-precision capacitance detection method and detection circuit with self-adaptive measuring range, wherein the detection circuit comprises: the capacitor detection circuit is used for generating a voltage signal related to the capacitance value of the capacitor to be detected through the constant current characteristic of the reference current source in a certain voltage range; the control circuit is used for generating a clock signal, controlling the periodic charge and discharge of the capacitor to be tested through the frequency division result of the clock signal, converting the voltage signal output by the capacitor detection circuit into a level signal, and providing a quantization starting signal and a quantization ending signal for the quantization circuit; the measuring range detection circuit is used for detecting the signal and the frequency division result output by the control circuit, adjusting the frequency division ratio of the frequency divider and increasing the measuring range of the circuit to finish the measurement of the capacitance to be measured; and the quantization circuit is used for carrying out capacitance quantization based on the time domain and outputting a quantization result. The invention has the characteristics of full integration, high precision and high linearity, and simultaneously combines the measuring range and the measuring precision of the capacitance quantification circuit.

Description

A range-adaptive high-precision capacitance detection method and detection circuit

technical field

The invention belongs to the field of sensor technology, and relates to a range-adaptive high-precision capacitance detection method and a detection circuit.

Background technique

In recent years, with the continuous development of the Internet and the semiconductor industry, the world has gradually entered the era of the Internet of Things, where everything is interconnected. By 2018, the Internet of Things has gone out of the industrial world and has been extended to various fields such as home appliances, medical care, transportation, and logistics. field. Femtofarad capacitive sensors, as one of the most critical supporting technologies, have been strongly driven by market demand. A capacitive sensor is a conversion device that converts the physical quantity to be measured into a change in capacitance. Due to its simple structure and high sensitivity, it has been widely used in various fields, such as capacitive pressure sensors for pressure detection, capacitive fingerprint sensors for biometric identification, and capacitive accelerometers for medical testing. wait.

Traditional capacitance detection methods mainly include detection methods such as frequency type, switched capacitor type, and resistance discharge type. For the frequency detection method, its detection accuracy cannot reach the femtomethod level. For the switched capacitor detection method, when quantifying the capacitance, it must first complete the conversion of the capacitance to the voltage, and then use the ADC to complete the conversion of the voltage into a digital signal; however, the accuracy and noise of the switched capacitor circuit limit the resolution of the measured capacitance. Rate. Resistive discharge circuits generally charge the capacitor first, and finally discharge through an off-chip precise resistor, and then quantify the discharge time. Although the circuit can achieve high precision, since the discharge of the capacitor through the resistance is an exponential waveform, the signal needs to be linearized before quantization, and the resulting algorithm is more complicated, and the corresponding quantization rate and quantization circuit The integration level is also low, and this quantization method has higher requirements on the accuracy of the time measurement circuit. The shortcomings of the above circuit itself limit the further development of high-precision capacitive sensors. In addition, most of the above-mentioned circuits have a mutual restrictive relationship between the range and the quantization accuracy. Under the same quantization accuracy, the measurement range is basically fixed. Once the capacitance to be measured exceeds its preset range, the above-mentioned measurement circuits cannot complete the measurement or need to reduce the quantization accuracy to complete the measurement.

Contents of the invention

In order to solve the above problems, the embodiment of the present invention provides a range-adaptive high-precision capacitance detection circuit, which has the characteristics of full integration, high precision, and high linearity, and at the same time takes into account the measurement range and measurement accuracy of the capacitance quantization circuit. There are technical problems.

Another object of the embodiments of the present invention is to provide a high-precision capacitance detection method with adaptive range.

The technical solution adopted in the present invention is a range-adaptive high-precision capacitance detection circuit, including a capacitance detection circuit, a control circuit, a range detection circuit and a quantization circuit;

The capacitance detection circuit is used to generate a voltage signal related to the capacitance value of the capacitance to be measured through the constant current characteristic of the reference current source within a certain voltage range, that is, the signal S2;

The control circuit is used to generate a clock signal, that is, signal S5, and control the periodic charge and discharge of the capacitor to be tested through the frequency division result S1 of the clock signal, and convert the voltage signal output by the capacitance detection circuit into a level signal, that is, signal S3; According to the signal S3, the quantization circuit is provided with a start quantization and an end quantization signal;

The range detection circuit is used to detect the signal S3 and the frequency division result S1 output by the control circuit, and judge whether the signal S3 is at a high level when the falling edge of the frequency division result S1 comes, and if it is a high level, use the current range to measure the capacitance Quantification; if the signal S3 is low level, it indicates that the capacitance to be measured exceeds the preset range, and the current output signal S6 of the range detection circuit is shifted and registered for output, and the output signal S6 is sent to the IN1 terminal of the frequency divider. Adjust the frequency division ratio of the frequency divider and increase the range of the circuit to complete the measurement of the capacitance under test;

The quantization circuit is used according to the formula Determine the capacitance value of the capacitor to be tested, where C represents the capacitance value of the capacitor to be measured, I represents the discharge current generated by the reference current source, ΔV represents the discharge voltage of the capacitor to be measured, and Δt represents the time elapsed for the capacitor to discharge; based on the time domain Carry out capacitance quantization and output the quantization result.

Further, the capacitance detection circuit includes a power supply VDD, a selector, a PMOS transistor, and a reference current source;

The power supply VDD is used to charge the capacitor to be tested, the power supply VDD is connected to both ends of the capacitor to be tested, and one end of the capacitor to be tested connected to the negative pole of the power supply VDD is grounded;

The PMOS tube is used to control the periodic charge and discharge of the capacitor under test according to the frequency division result S1; the PMOS tube is connected to the connection circuit between the capacitor under test and the power supply VDD, and the frequency division result S1 is input to the gate terminal of the PMOS tube to control the PMOS tube tube opening and closing;

The one-of-two selector is used to decide to connect the reference current source to the power supply VDD or to connect the reference current source to the capacitor to be measured according to the frequency division result S1; the frequency division result S1 is input to the input terminal of the one-two selector, The output terminal of the one-of-two selector outputs a voltage signal S2.

Further, the frequency division result S1 is a periodic square wave, and the high and low levels of the frequency division result S1 are determined by the system clock signal S5 and the frequency division ratio.

Further, the control circuit includes a clock generation circuit, a comparator, a rising edge detector, a frequency divider and a reference voltage source;

The clock generating circuit is used to generate a system clock signal, namely signal S5, and input signal S5 to the control terminal of the rising edge detector and the input terminal of the frequency divider respectively;

The comparator is used to convert the signal S2 into a signal S3, and input the signal S3 into the rising edge detector; the inverting input terminal of the comparator is connected to the output terminal of the capacitance detection circuit, and the output terminal of the comparator is connected to the rising edge detector the input terminal;

The rising edge detector is used to detect the output of the comparator. When the signal S3 output by the comparator jumps from a low level to a high level, the rising edge detector outputs a rectangular pulse when the next rising edge of the signal S5 comes. , namely signal S4;

The reference voltage source is used to calibrate the discharge interval of the capacitor to be measured, and the reference voltage source is connected to the non-inverting input terminal of the comparator;

The frequency divider comprises a delay unit cascaded to form a delay chain module. Except for the first and last delay units, the intermediate delay units are all connected end to end, and the output of each delay unit is connected to the next delay unit. The input of the time unit, the output section of each delay unit is connected with a D flip-flop, the signal S3 is input to the input end of the first delay unit of the delay chain module, and the signal S4 is input to each D flip-flop Clock terminal; when the rising edge of the signal S4 comes, the D flip-flop sends the output level of the corresponding delay unit to its Q terminal, and the Q of the D flip-flop of the frequency divider is connected back to the D terminal to form a two-frequency division The device divides the frequency of the input signal S5 by 2, and the Q terminal outputs the frequency division result, that is, S1.

Further, during the charging of the capacitor under test, when the signal S2 is the power supply VDD, the signal S3 is at a low level. During the discharge of the capacitor under test, as the capacitor voltage decreases, the signal S2 keeps decreasing. When the level is slightly smaller than VREF, the output signal S3 of the comparator turns from low level to high level, which marks the end of the discharge of the capacitor under test.

Further, the output signal S6 of the range detection circuit is a binary signal with a bit width of M, represented by a binary number of [M-1,0] bits, when a certain bit is 1, the corresponding bit is high level, When a certain bit is 0, the corresponding bit is low level; the signal S6 has M bits in total, and can control M switches. The delay unit cascade node after the lowest bit S6[0] of the signal S6 is provided with a switch, and the signal S6 Each bit of S6 is connected to the corresponding switch. When a certain bit of the signal S6 is 0, the corresponding switch is turned off, and when it is 1, the corresponding switch is closed; when the circuit is powered on, the preset frequency division ratio is determined by S6[0 The number of D flip-flops before ] is determined; when the circuit is in the preset range, the value of the signal S6 is S6=[00...1], that is, only the lowest bit S6[0] of the signal S6 is 1, and the corresponding switch is closed ;The other bits are all 0, and the corresponding switches are all turned off; at this time, the D flip-flop corresponding to the switch controlled by S6[0] outputs the frequency division result S1; every time the circuit adjusts the range, the value of the signal S6 The one that is 1 is moved forward by one bit, and one more D flip-flop participates in frequency division, the frequency division ratio is doubled, and the range of the circuit is doubled.

Further, the output signal S6 of the range detection circuit has been moved to the last digit, and the measurement still cannot be completed, then the output signal S7 of the range detection circuit is 1, indicating that the capacitance to be measured has exceeded the maximum range of the circuit; otherwise the range detection The output signal S7 of the circuit is always 0.

Further, the quantization circuit includes a counter, a delay chain module, and an arithmetic unit;

The counter has a total of 3 input signals, wherein the frequency division result S1 and signal S3 are the control signals of the counter, and the signal S5 is the input signal of the counter. When the frequency division result S1 is low level, the counter stops counting. When the frequency division result When S1 is high level and signal S3 is low level, the counter starts counting. At this time, the corresponding circuit state is that the capacitor starts to discharge, but it has not yet discharged to the calibrated voltage; when the signal S3 is high level, it indicates that the comparator has flipped. At this time, the counter stops counting and outputs the counting result N of the clock cycle;

The output of each D flip-flop of the delay chain module is connected to the input of the arithmetic unit;

The operation unit is used to calculate the time Δt experienced by the discharge of the capacitor to be measured according to the formula Δt=NT-nt, wherein T represents the clock period of the clock generating circuit, and n represents the delay between the rising edges of the signal S3 and the signal S4 The number of "1" levels in all D flip-flops in the time chain, and t represents the delay of the delay unit.

Further, the precision of the comparator is 0.1mV.

A detection method for a range-adaptive high-precision capacitance detection circuit, using the above-mentioned range-adaptive high-precision capacitance detection circuit, specifically according to the following steps:

Step 1: When the circuit is powered on, it is the initial frequency division ratio, and the value of S6 is S6=[00...1];

Step 2: When quantizing for the first time after power-on, the range detection circuit judges whether the signal S3 is low when the falling edge of the frequency division result S1 comes, if not, use the current range to quantify the capacitance to be measured; if yes, shift the S6 signal Register, after each shift and register, it is necessary to judge whether the signal S3 is at low level when the falling edge of the frequency division result S1 comes, if not, use the current range for quantization; if so, continue to shift and register the S6 signal; In the process of shifting and registering, it is necessary to judge whether S6 has reached S6=[1...00];

Step 3: If S6=[1...00] is reached, continue to judge whether the signal S3 is low level when the falling edge of the frequency division result S1 comes, if not, use the current range for quantization; if yes, exceed the maximum range, give Flag signal S7.

The beneficial effects of the present invention are:

The range-adaptive high-precision quantization circuit of the present invention adopts the on-chip integrated reference current source discharge mode, and only needs to perform simple linear operations when quantifying the variation of capacitance, which solves the problem of complex algorithms in traditional quantization circuits , which reduces the complexity of the quantization algorithm; at the same time, because no other external components are required, the integration of the capacitance quantization circuit is improved, and the volume of the quantization circuit is greatly reduced.

The quantization range of the circuit is determined by the frequency division ratio of the frequency divider and the maximum count value of the counter, and the quantization accuracy is determined by the accuracy of the delay unit of the delay chain. Within the maximum range, there is no compromise between range and accuracy. The problem solves the mutual restriction relationship between the quantization range and the quantization precision. The range can be adjusted adaptively, and the adjustment process does not increase its own measurement range at the expense of quantization accuracy. Even if it exceeds the preset range of the circuit, the circuit can still complete the measurement of the capacitance to be measured. At the same time, when performing capacitance quantization, since the quantization algorithm is relatively simple, the quantization can be completed quickly.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a functional block diagram of a quantization method according to an embodiment of the present invention.

FIG. 2 shows the composition of the capacitance detection circuit of the embodiment of the present invention.

Fig. 3 shows the composition of the control circuit and the range detection circuit of the embodiment of the present invention.

Fig. 4 shows the composition of the frequency divider in the embodiment of the present invention.

Fig. 5 is a logic block diagram of the regulating circuit in the embodiment of the present invention.

Fig. 6 is a block diagram of a quantization circuit in an embodiment of the present invention.

FIG. 7 is a schematic diagram of timing waveforms of key signals in a single measurement process according to an embodiment of the present invention.

8a-8d are the simulation results of the embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The basic principle of the circuit is as follows: According to the principle of capacitor charging and discharging, It can be concluded that, under the condition that the discharge current I of the capacitor is kept constant, by setting the discharge voltage ΔV of the capacitor as a fixed interval, it can be obtained that the discharge time Δt of the capacitor has a linear relationship with the capacitance of the capacitor C, so the extremely large The linearity of the quantization result is improved, and the complexity of quantizing the capacitance is also reduced. The above-mentioned circuits can be implemented inside the integrated circuit without external components, which reduces the volume of the quantization circuit and improves its integration. When the circuit quantifies the capacitance to be measured, it will detect the current range. If the quantization cannot be completed, it will complete the quantization of the capacitance to be measured by adjusting its own range.

Example 1,

A range-adaptive high-precision capacitance detection circuit, as shown in FIG. 1 , includes a capacitance detection circuit, a control circuit, a range detection circuit and a quantization circuit.

The capacitance detection circuit is used to detect the voltage of the capacitance to be tested (Ctest), and generates a voltage signal related to the capacitance value of the capacitance to be tested through the constant current characteristic of the reference current source (Iref) within a certain voltage range, that is, the signal S2, and transmitted to the control circuit.

The control circuit is used to generate the clock signal, the charge and discharge control signal, and the start and end signals of the quantization circuit. The clock generation circuit generates a clock signal, controls the periodic charge and discharge of the capacitor to be tested through the frequency division result S1 of the clock signal, and converts the voltage signal output by the capacitance detection circuit into a level signal, that is, the signal S3; provides a starting point for the quantization circuit according to the signal S3 Quantize and end quantize the signal.

The range detection circuit is used to detect the signal S3 output by the control circuit and the frequency division result S1. When the falling edge of the frequency division result S1 comes (that is, at the end of each frequency division cycle), it is judged whether the signal S3 is at a high level. Level, indicating that the current range can complete the measurement of the capacitance to be measured, and use the current range to quantify the capacitance to be measured; if the signal S3 is low, it indicates that the capacitance to be measured exceeds the preset range, that is, the reference current source cannot measure the capacitance to be measured Discharge to the calibrated voltage, shift and register the current output signal S6 of the range detection circuit, and then output it. The output signal S6 is sent to the IN1 terminal of the frequency divider to adjust the frequency division ratio of the frequency divider and increase the capacitance during a single measurement. The discharge time allows the reference current source to discharge the capacitor under test to the nominal voltage, thereby increasing the range of the circuit to complete the measurement of the capacitor under test. The frequency divider generates a frequency division result S1 according to the signal S5, and at the same time, the frequency divider can adjust its own frequency division ratio according to the output signal (S6) of the range detection circuit.

Quantization circuit for use according to the formula Determine the capacitance value of the capacitor to be tested, where C represents the capacitance value of the capacitor to be measured, I represents the discharge current generated by the reference current source, ΔV represents the discharge voltage of the capacitor to be measured, and Δt represents the time elapsed for the capacitor to discharge; the final output is quantified result. The time of capacitor discharge is determined by measuring the time interval between two control signals, output binary data, and complete the conversion to digital signal, DOUT is the final quantization result; the capacitance quantization method adopted is based on the time domain, and the range detection circuit Working closely with the specific capacitance quantization method, the function of automatic range adjustment is realized.

Referring to FIG. 2 , the capacitance detection circuit includes a power supply VDD, an alternative selector (MUX2), a PMOS transistor, and a reference current source (Iref). The reference current source generates a reference current of 1uA (microampere).

The power supply VDD is used to charge the capacitor to be tested, the power supply VDD is connected to both ends of the capacitor to be tested, and the end of the capacitor to be tested connected to the negative pole of the power supply VDD is grounded;

PMOS tube, used to control the periodic charge and discharge of the capacitor under test according to the frequency division result S1; on and off;

One of the two selectors is used to decide to connect the reference current source to the power supply VDD or connect the reference current source to the capacitor under test according to the frequency division result S1; the frequency division result S1 is input to the input terminal of the one of two selectors, An output terminal of a selector outputs a voltage signal S2. The A channel of MUX2 is used to connect the reference current source to the capacitor under test, the B channel of MUX2 is used to connect the reference current source to the power supply VDD, and the frequency division result S1 is connected to the control terminal (S) of MUX2.

The frequency division result S1 is a periodic square wave, which is obtained by frequency division of the system clock signal S5, and its high and low level time is determined by the system clock signal S5 and the frequency division ratio, as shown in Figure 7. When the frequency division result S1 is low level, the PMOS tube is turned on, MUX2 selects the VDD terminal, and directly uses the power supply VDD to complete charging, so the signal S2 is always the voltage of the power supply VDD; when the frequency division result S1 is high level, the PMOS tube is turned off , MUX2 selects the terminal of the capacitor to be tested, the signal S2 is the output voltage of the capacitor to be tested, and a constant current source is used to discharge the capacitor to be tested to ensure that the discharge current of the capacitor is constant, and the voltage on the capacitor to be tested decreases linearly, that is, the slope of the signal S2 Fixed, different capacitance values, the slope of the voltage signal is different. When the capacitor is charged, the reference current source (Iref) is connected to the power supply voltage. Although a certain amount of static power consumption will be increased, the voltage across the current source will not change rapidly during the transition from charging to discharging state of the capacitor under test. , to ensure that the working state of the MOS tube inside the current source will not change, thereby ensuring the constant discharge current, and avoiding the change of the constant current characteristic of the reference current source due to the switching of the working state of the MOS tube, thereby introducing nonlinearity in the quantization result.

Referring to FIG. 3, the control circuit includes a clock generation circuit, a comparator, a rising edge detector (CLK), a frequency divider and a reference voltage source (VREF).

The clock generation circuit is used to generate a system clock signal (signal S5), and input the signal S5 to the control terminal of the rising edge detector and the input terminal of the frequency divider respectively.

A comparator for converting the signal S2 into a signal S3 and inputting the signal S3 into the rising edge detector; the inverting input terminal of the comparator is connected to the output terminal of the capacitance detection circuit, and the output terminal of the comparator is connected to the input of the rising edge detector terminal; during the charging of the capacitor under test, when the signal S2 is the power supply VDD, the signal S3 is at low level, during the discharge of the capacitor under test, with the decrease of the capacitor voltage, the signal S2 keeps decreasing, when the signal S2 level is higher than When VREF is slightly smaller, the output signal S3 of the comparator turns from low level to high level, which marks the end of the discharge of the capacitor under test. In some embodiments, the accuracy of the comparator is 0.1 mV, and the discharge interval of the capacitor is guaranteed to be 1 V. The higher the accuracy of the comparator, the better.

The rising edge detector is used to detect the output of the comparator. When the signal S3 output by the comparator jumps from low level to high level, the rising edge detector outputs a rectangular pulse when the next rising edge of the signal S5 comes, namely Signal S4.

The reference voltage source is used to calibrate the discharge interval of the capacitor to be measured, and the reference voltage source is connected to the non-inverting input terminal of the comparator.

The frequency divider, including the delay unit, is cascaded to form a delay chain module. Except for the first and last delay unit, all the delay units in the middle are connected end to end, and the output of each delay unit is connected to the next delay unit. The output section of each delay unit is connected to a D flip-flop, the signal S3 is input to the input end of the first delay unit of the delay chain module, and the signal S4 is input to the clock terminal of each D flip-flop ; When the rising edge of the signal S4 comes, the D flip-flop sends the level output by the corresponding delay unit to its Q terminal, and the Q of the D flip-flop of the frequency divider is connected back to the D terminal to form a two-frequency divider. Complete the function of frequency division by two; divide the frequency by 2 on the input signal S5, and output the frequency division result at the Q terminal, that is, S1; refer to Figure 4. The cascade connection of m units can realize the function of 2 ^m frequency division, and the output of each D flip-flop of the delay chain module is connected to the input of the operation unit.

The output signal S6 of the range detection circuit is a binary signal with a bit width of M, represented by a binary number of [M-1,0] bits, when a certain bit is 1, the corresponding bit is high level, and when a certain bit is 0 , the corresponding bit is low level; the signal S6 has M bits in total and can control M switches. Referring to Fig. 4, a switch is provided on the cascade node of the delay unit after the lowest bit S6[0] of the signal S6, and each bit (0~M-1) of the signal S6 is connected to the corresponding switch, when a certain bit of the signal S6 When one bit is 0, the corresponding switch is off, and when it is 1, the corresponding switch is closed; when the circuit is powered on, the preset frequency division ratio is determined by the number of D flip-flops before S6[0]; the circuit is a preset range , the value of the signal S6 is S6=[00...1], that is, only the lowest bit S6[0] of the signal S6 is 1, and the corresponding switch is closed; other bits (such as S6[1], S6[2]...S6 [M-1]) are all 0, and the corresponding switches are all turned off; at this time, the D flip-flop corresponding to the switch controlled by S6[0] outputs the frequency division result S1; each time the circuit adjusts the range, the signal S6 The value of 1 is moved forward one bit, assuming that the circuit has only adjusted the range once, that is, the value of S6 is S6=[00...10], at this time, the D trigger corresponding to the switch controlled by S6[1] It can be known from Figure 4 that one more D flip-flop participates in the frequency division, so the frequency division ratio is doubled, and the range of the circuit is also doubled. Every time the output of S6 is shifted, one more D flip-flop will participate in the frequency division, and the frequency division ratio will be doubled. long, the reference power supply can discharge a larger capacitance to the calibrated voltage, which means the larger the capacitance that the circuit can measure, the frequency division module and the range detection circuit together complete the function of automatically adjusting the range of the circuit.

In the above process, the S7 signal is always 0. If the value of S6 is S6=[10...00], that is, it has moved to the last digit and the measurement cannot be completed, the output signal S7 is 1, indicating that the capacitance to be measured has exceeded the circuit If the capacitor to be measured exceeds the preset range, the reference current source cannot discharge the capacitor to the calibrated voltage when the falling edge of the frequency division signal comes, and the output of the comparator will not turn from low to high.

Referring to FIG. 6 , the quantization circuit includes a counter (Counter), a delay chain module (Delay line), and an arithmetic unit (ALU).

The counter has 3 input signals. The frequency division result S1 and signal S3 are the control signals of the counter, and the signal S5 is the input signal of the counter. When the frequency division result S1 is low level, the counter stops counting. When the frequency division result S1 is When the signal S3 is high and the signal S3 is low, the counter starts counting. At this time, the corresponding circuit state is that the capacitor starts to discharge, but it has not yet discharged to the calibration voltage; when the signal S3 is high, it indicates that the comparator has been reversed. At this time , the counter stops counting and outputs the counting result N of the clock cycle, and the counting result is multiplied by the cycle of the clock signal S5 to obtain the rough time that the entire capacitor has experienced from the start of discharge to the end of discharge, and complete the rough quantization. Since the cycle of the clock generating circuit is fixed, each cycle of the signal S5 is also fixed. However, the rising edge of the output of the comparator cannot always be aligned with the edge of S5, so only using the counter output as the quantization result will bring a huge error.

The output of each D flip-flop of the delay chain module is connected to the input of the operation unit, and the operation unit reads the counting result of the counter and the result of the delay unit to perform calculation;

The arithmetic unit is used to calculate the time Δt experienced by the capacitor discharge under test according to the formula Δt=NT-nt, wherein T represents the clock period of the clock generating circuit, and n represents the delay chain in the interval between the rising edges of the signal S3 and the signal S4 The number of all D flip-flops whose level is "1", t represents the delay of the delay unit.

Referring to Figure 7, S1 is the frequency division result of S5. When S1 is low level, the capacitor is charged to VDD. At time t1, S1 becomes high level, the capacitor starts to discharge, and the counter starts counting at the same time. At time t2, the capacitor discharges to 0.8V, and the output result of the comparator (S3) is reversed. At this time, the control counter stops counting. It can be seen from Figure 7 that the quantization result of the counter is the time period of t1-t3, but the capacitor under test is actually discharged The time is the t1-t2 time period, so the t2-t3 time period is the quantization error introduced by the coarse quantization.

After the rising edge of S3 comes, the signal S3 is transmitted inside the delay chain, and every time a time interval of a delay unit passes, the output of a delay unit is high level. During the time interval between the rising edges of the signal S3 and the signal S4, only the outputs of a limited number of delay units will become high level, and the outputs of other delay units remain at 0. After the rising edge of the signal S4 arrives, the arithmetic unit ALU reads out the output of the D flip-flop. The time interval between the rising edges of the signal S3 and the signal S4 can be obtained by calculating the number of “1” in all D flip-flops.

It can be seen from FIG. 7 that the result of subtracting the quantization result of the counter (t1-t3 time period) from the t2-t3 time period is the actual discharge time of the capacitor. At time t2, the rising edge of the S3 signal arrives, and the rising edge starts to be transmitted in the delay chain. At time t3, the rising edge detector in the control module outputs a rectangular pulse, which is the waveform of signal S4, and the rising edge of the signal is used as the control signal of the D flip-flop of the delay chain, and the delay chain is read out at time t3 The number of "1" in the multi-bit output is n, and t represents the delay of the delay unit, then the t2-t3 time period is:

t3-t2=nt

Assume that the capacitor is charged to 1.8V during charging, the voltage at the non-inverting input of the comparator is 0.8V, and the discharge current generated by the reference current source is 1uA. Then the quantitative result is:

Among them, F represents the unit farad of capacitance.

The delay chain module is composed of a delay unit and a D flip-flop. The delay chain module is used to complete the measurement of the rising edge time interval of the S3 and S4 signals, and DOUT is the final capacitance quantization result. The quantization circuit adopts a combination of fine quantization and coarse quantization. The coarse quantization is completed by the counter, and the fine quantization is completed by the delay chain module, which can take into account both the quantization range and the quantization accuracy. Finally, the function of converting the capacitance value of the capacitor to be measured to a binary number is completed. The shorter the delay of the delay unit, the higher the accuracy that this application can achieve, and the quantization range is determined by the time when S1 is at a high level. The longer the high level lasts, the longer the discharge time of the constant current source is. The quantization range of the circuit is larger. It can be concluded that the accuracy of the circuit is determined by the delay of the delay unit, and the quantization range of the circuit is determined by the time when S1 is at a high level. There is no mutual restriction between the two parameters, so the quantization range and quantization accuracy can be considered .

Referring to FIGS. 8a-8d, the abscissa C _test is the capacitance of the capacitor to be tested, and the ordinate C _mear is the simulation result corresponding to the quantization circuit. Fig. 8a is the simulation result of the capacitance value of the capacitor under test increasing by 1 fF when the bulk value of the capacitor under test is 310 fF. FIG. 8 b shows the simulation results of the capacitance value of the capacitor under test increasing by 1 fF when the bulk value of the capacitor under test is 1005 fF. Fig. 8c is a simulation result of the capacitance value of the capacitor under test increasing by 10 fF when the bulk value of the capacitor under test is 300 fF. Fig. 8d is a simulation result of the capacitance value of the capacitor under test increasing by 100 fF when the bulk value of the capacitor under test is 300 fF. It can be seen from the simulation results that even if the bulk values of the capacitors to be measured are different, the quantization circuit can still achieve the quantization accuracy of 1fF. At the same time, it can be concluded from the simulation results of FIG. 8c and FIG. 8d that even if the capacitance of the capacitor to be measured changes greatly, the circuit can still complete the measurement accurately. Considering non-ideal factors, the simulation results in the figure have a very small quantization offset from the actual value of the capacitance to be measured. This offset does not affect the quantization linearity. In the later product use, it can be achieved by single-point calibration during the initialization process. translation calibration. In summary, when the quantization circuit is used for capacitance measurement, it can achieve a quantization accuracy of 1 fF, and at the same time, the quantization results have good linearity in a large range.

The maximum range of this application depends on the number of additional frequency dividers added by the frequency division circuit after the initial frequency division. For each additional frequency divider, the maximum range will be doubled, and the maximum range is 12pF; while ensuring the quantization accuracy The range is 0-1.5pF. The measuring range of the existing detection circuit is 0-1.5pF, and the quantization precision is 1fF.

Example 2,

A high-precision capacitance detection method with adaptive range, as shown in Figure 5, adopts the above-mentioned detection circuit, and specifically performs the following steps:

Step 1: When the circuit is powered on, it is the initial frequency division ratio, and the value of S6 is S6=[00...1];

Step 2: When quantizing for the first time after power-on, the range detection circuit judges whether the signal S3 is low when the falling edge of the frequency division result S1 comes, if not, use the current range to quantify the capacitance to be measured; if yes, shift the S6 signal Register, after each shift and register, it is necessary to judge whether the signal S3 is at low level when the falling edge of the frequency division result S1 comes, if not, use the current range for quantization; if so, continue to shift and register the S6 signal; In the process of shifting and registering, it is necessary to judge whether S6 has reached S6=[1...00];

Step 3: If S6=[1...00] is reached, continue to judge whether the signal S3 is low level when the falling edge of the frequency division result S1 comes, if not, use the current range for quantization; if yes, exceed the maximum range, give Flag signal S7.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present invention are included in the protection scope of the present invention.

Claims (9)

1. The high-precision capacitance detection circuit with the self-adaptive range is characterized by comprising a capacitance detection circuit, a control circuit, a range detection circuit and a quantization circuit;

the capacitance detection circuit is used for generating a voltage signal related to the capacitance value of the capacitor to be detected, namely a signal S2, through the constant current characteristic of the reference current source in a certain voltage range;

the control circuit is used for generating a clock signal, namely a signal S5, controlling the periodic charge and discharge of the capacitor to be tested through the frequency division result S1 of the clock signal, and converting the voltage signal output by the capacitor detection circuit into a level signal, namely a signal S3; providing a start quantization and end quantization signal to the quantization circuit according to the signal S3;

the measuring range detection circuit is used for detecting a signal S3 and a frequency division result S1 output by the control circuit, judging whether the signal S3 is in a high level temporarily when the frequency division result S1 falls, and quantizing the capacitor to be detected by using the current measuring range if the signal S3 is in the high level; if the signal S3 is low level, indicating that the capacitance to be measured exceeds a preset measuring range, carrying out shift registering on the current output signal S6 of the measuring range detection circuit, outputting the output signal S6, sending the output signal S6 to the IN1 end of the frequency divider, adjusting the frequency dividing ratio of the frequency divider, and increasing the measuring range of the circuit to finish the measurement of the capacitance to be measured;

the quantization circuit is used for generating a quantization signal according to the formulaDetermining the capacitance value of the capacitor to be measured, wherein C represents the capacitance value of the capacitor to be measured,Irepresents the discharge current, delta, generated by the reference current sourceVRepresents the discharge voltage delta of the capacitor to be measuredtRepresenting the time that the capacitor has elapsed to discharge; carrying out capacitance quantization based on a time domain and outputting a quantization result;

the capacitance detection circuit includes:

the PMOS tube is used for controlling periodic charge and discharge of the capacitor to be tested according to the frequency division result S1;

the alternative selector is used for determining whether to connect the reference current source to the power supply VDD or connect the reference current source to the capacitor to be tested according to the frequency division result S1; the frequency division result S1 is input to the input end of the alternative selector, and the output end of the alternative selector outputs a voltage signal S2;

the control circuit comprises a clock generation circuit, a comparator, a rising edge detector, a frequency divider and a reference voltage source;

the clock generation circuit is used for generating a system clock signal, namely a signal S5, and inputting the signal S5 to the control end of the rising edge detector and the input end of the frequency divider respectively;

the comparator is used for converting the signal S2 into a signal S3 and inputting the signal S3 into the rising edge detector; the inverting input end of the comparator is connected with the output end of the capacitance detection circuit, and the output end of the comparator is connected with the input end of the rising edge detector;

the rising edge detector is used for detecting the output of the comparator, and when the signal S3 output by the comparator jumps from low level to high level, the rising edge detector outputs a rectangular pulse, namely a signal S4, on the next rising edge of the signal S5 temporarily;

the reference voltage source is used for calibrating a discharge interval of the capacitor to be measured and is connected with the non-inverting input end of the comparator;

the frequency divider comprises delay chain modules formed by cascade connection of delay units, wherein the delay units in the middle are connected end to end except the first delay unit and the last delay unit, the output of each delay unit is connected with the input of the next delay unit, the output end of each delay unit is connected with a D trigger, a signal S3 is input to the input end of the first delay unit of the delay chain module, and a signal S4 is input to the clock end of each D trigger; when the rising edge of the signal S4 comes, the D trigger sends the level output by the corresponding delay unit to the Q end of the signal S4, the Q of the D trigger of the frequency divider is not connected back to the D end to form 1 frequency divider, the input signal S5 is subjected to 2 frequency division, and the Q end outputs a frequency division result S1;

the quantization circuit comprises an operation unit for calculating the time Δt that the capacitor to be measured discharges according to the formula Δt=nt-NT, wherein T represents the clock period of the clock generation circuit, n represents the number of "1" levels in all D flip-flops in the delay chain in the interval between the rising edges of the signal S3 and the signal S4, and T represents the delay of the delay unit.

2. The range-adaptive high-precision capacitance detection circuit according to claim 1, further comprising a power supply VDD; the power supply VDD is used for charging the capacitor to be tested, the power supply VDD is connected to two ends of the capacitor to be tested, and one end of the capacitor to be tested, which is connected with the negative electrode of the power supply VDD, is grounded;

the PMOS tube is connected to the connecting loop of the capacitor to be tested and the power supply VDD, and the frequency division result S1 is input to the gate end of the PMOS tube to control the on and off of the PMOS tube.

3. The range-adaptive high-precision capacitance detecting circuit according to claim 1, wherein the frequency dividing result S1 is a periodic square wave, and the time of the high and low levels of the frequency dividing result S1 is determined by the system clock signal S5 and the frequency dividing ratio.

4. The range-adaptive high-precision capacitance detection circuit according to claim 1, wherein the signal S3 is low when the signal S2 is the power supply VDD during the charging period of the capacitor to be detected, the signal S2 is continuously reduced as the voltage of the capacitor to be detected is reduced during the discharging period of the capacitor to be detected, and the output signal S3 of the comparator is turned from low to high when the level of the signal S2 is smaller than VREF, thereby indicating the end of the discharging period of the capacitor to be detected.

5. The range-adaptive high-precision capacitance detection circuit according to claim 1, wherein the output signal S6 of the range detection circuit is a binary signal with a bit width of M, and is represented by a binary number of [ M-1,0] bits, and when a certain bit is 1, the corresponding bit is high, and when a certain bit is 0, the corresponding bit is low; the signal S6 has M bits, M switches can be controlled, a switch is arranged on a delay unit cascade node behind the lowest bit S6[0] of the signal S6, each bit of the signal S6 is connected to a corresponding switch, and when one bit of the signal S6 is 0, the corresponding switch is disconnected; when the voltage is 1, the corresponding switch is closed; when the circuit is powered on, the preset frequency division ratio is determined by the number of D flip-flops before S6[ 0]; when the circuit is of a preset range, the value of the signal S6 is S6= [00 … ], namely, only the lowest bit S6[0] of the signal S6 is 1, and the corresponding switch is closed; the other bits are all 0, and the corresponding switches are all disconnected; at this time, the D trigger corresponding to the switch controlled by S6[0] outputs the frequency division result S1; and when the circuit adjusts the measuring range, the bit with 1 in the value of the signal S6 is moved forward by one bit, 1D flip-flop is added in frequency division, the frequency division ratio is doubled, and the measuring range of the circuit is doubled.

6. The adaptive ranging high-precision capacitance detecting circuit according to claim 5, wherein the output signal S6 of the ranging detection circuit has been shifted to the last position and the measurement cannot be completed, the output signal S7 of the ranging detection circuit is 1, which indicates that the capacitance to be detected has exceeded the maximum range of the circuit; otherwise, the output signal S7 of the span detection circuit is always 0.

7. The range-adaptive high-precision capacitance detection circuit according to claim 1, wherein the quantization circuit further comprises a counter and a delay chain module;

the counter has 3 input signals in total, wherein a frequency division result S1 and a signal S3 are control signals of the counter, a signal S5 is an input signal of the counter, when the frequency division result S1 is in a low level, the counter stops counting, when the frequency division result S1 is in a high level and the signal S3 is in a low level, the counter starts counting, and at the moment, the corresponding circuit state is that a capacitor starts discharging, but the capacitor does not discharge to a calibration voltage yet; when the signal S3 is high, indicating that the comparator has flipped, at which time the counter stops counting and outputs the count result N of the clock cycle;

the output of each D trigger of the delay chain module is connected to the input of the operation unit.

8. The range-adaptive high-precision capacitance detection circuit according to claim 1, wherein the comparator has a precision of 0.1mV.

9. A detection method of a range-adaptive high-precision capacitance detection circuit, which is characterized by adopting the range-adaptive high-precision capacitance detection circuit according to any one of claims 1-8, and specifically comprising the following steps:

step 1: the circuit is powered on with an initial frequency division ratio, and the S6 value is S6= [00 … 1];

step 2: when the capacitor to be measured is quantized for the first time after power-on, the range detection circuit judges whether a temporary signal S3 coming from the falling edge of a frequency division result S1 is of a low level or not, and if not, the capacitor to be measured is quantized by using the current range; if yes, for the shift register of the S6 signal, judging whether the time signal S3 from the falling edge of the frequency division result S1 is at a low level or not after each shift register, if not, quantifying by using the current measuring range; if yes, continuing to shift and register the S6 signal; in the process of shift registering the S6 signal, whether S6 reaches S6= [1 … ] needs to be judged;

step 3: if the current range is reached, S6= [1 … 00] and whether the time signal S3 is at a low level when the falling edge of the frequency division result S1 comes is continuously judged, and if not, the current range is used for quantization; if so, the maximum range is exceeded, a flag signal S7 is given.