CN101655524A - Capacitance value measurement circuit and method thereof - Google Patents

Abstract

The invention provides a capacitance value measurement circuit and a capacitance value measurement method. The method comprises the steps of: firstly, in response to a first group of frequency signals, switching the voltage of one end of each of a capacitor to be measured and a capacitance value adjustable circuit to adjust an integral voltage into the sum of the integral voltage and a first differential voltage; then, judging whether a first control event is received, if so, performing integral operation to switch a voltage of at least one end of a known capacitor to adjust the integral voltage into the sum of the integral voltage and a second differential voltage, otherwise, performing the previous step; and then judging whether an integral period is terminated, if so, obtaining a capacitance value of the capacitor to be measured through the operation according to the number of the integral operation performed in the integral period and a capacitance value of the known capacitor, andotherwise, performing the first step again, and.

Description

Capacitance measurement circuit and method thereof

Technical field

The present invention relates to a kind of capacitance testing circuit, and relate in particular to and a kind ofly carry out the reaction time of charge and discharge charge and discharge when operating, obtain the capacitance sensing circuit of the capacitance of testing capacitance by observing the difference that to adjust the capacitance of circuit to testing capacitance and capacitance.The invention still further relates to the measured capacitance value method.

Background technology

Traditionally, realize user's control interface device with mechanical switch mostly.Because conventional mechanical switch needs directly to contact with the user, could operate the recurring structure damage in user's operating process easily of traditional mechanical formula device in response to user's steering order.

In the epoch now that development in science and technology is maked rapid progress, the touch switch exists.Traditionally, the touch switch for example is a capacitance-type switch, and it is to control with user's whether approaching variation by the capacitance of induction testing capacitance.Yet, how to design the capacitance testing circuit of the capacitance variation that can detect testing capacitance effectively, promote capacitance-type switch and be one of direction that industry constantly endeavours.

Summary of the invention

The present invention relates to a kind of capacitance testing circuit, compare with traditional capacitance value testing circuit, the capacitance testing circuit of present embodiment can carry out capacitance to testing capacitance more accurately and detect.

Propose a kind of capacitance measurement circuit according to the present invention, comprise integrator circuit, first, second control circuit and processor circuit.Integrator circuit has the first input end and first output terminal, has integral voltage on first output terminal, and integrator circuit is used for being set at the start bit standard in response to activation position brigadier's integral voltage of first control signal.First control circuit comprises second output terminal, testing capacitance and capacitance adjustable variable road, and second output terminal is electrically connected to first input end.Capacitance adjustable variable road is in response to the equivalent capacitance value of the signal numerical value of setting signal decision near the capacitance of testing capacitance.First control circuit is used in response to the voltage level at least one end on first class frequency signal switching testing capacitance and capacitance adjustable variable road, carry out first and adjust operation, with integral voltage be adjusted into the present position of integral voltage accurate with the first difference voltage sum, the capacitance of first difference voltage and testing capacitance is relevant with the difference of equivalent capacitance value.Second control circuit comprises the 3rd output terminal and known capacitance, and the 3rd output terminal is electrically connected to first input end.Second control circuit is used for carrying out second and adjusting operation in response to the voltage level at least one end of second class frequency signal switching known capacitance, integrator voltage is adjusted into the accurate and second difference voltage sum in present position of integral voltage.Processor circuit be used to provide first group and the second class frequency signal drive respectively first and second control circuit carry out respectively first and second adjust operation, calculate during first integral in second control circuit carry out second and adjust the number of operations of operating, and obtain the capacitance of testing capacitance according to the capacitance computing of number of operations and known capacitance.

Capacitance measurement circuit of the present invention, wherein, this first control circuit also comprises: first on-off circuit, in order to activation position standard in response to the first positive frequencies signal in the described first class frequency signal, first end of first voltage to described testing capacitance is provided, and, make first end of this testing capacitance be coupled to described integrator circuit in response to the activation position standard of the first anti-phase frequency signal in the described first class frequency signal; Wherein, this first forward and this first anti-phase frequency signal inversion signal each other.

Capacitance measurement circuit of the present invention, in one embodiment, this first control circuit also comprises: the second switch circuit, in order to activation position standard in response to this first positive frequencies signal, first end of second voltage to described capacitance adjustable variable road is provided, and, make first end on this capacitance adjustable variable road be coupled to described integrator circuit in response to the activation position standard of this first anti-phase frequency signal; Wherein, second end on second end of this testing capacitance and this capacitance adjustable variable road is to receive tertiary voltage.

Capacitance measurement circuit of the present invention, in one embodiment, this first control circuit also comprises: the second switch circuit, in order to activation position standard in response to the described first positive frequencies signal, make first end and second end on this capacitance adjustable variable road receive second voltage and this first voltage respectively, and, make first end on this capacitance adjustable variable road and second end be coupled to this integrator circuit respectively and receive this second voltage in response to the activation position standard of this first anti-phase frequency signal.

Capacitance measurement circuit of the present invention, wherein, this integrator circuit comprises: operational amplifier (Operational Amplifier), positive input terminal and negative input end receive the 4th voltage respectively and be coupled to this first and this second control circuit, described output terminal is coupled to this processor circuit; First integral electric capacity, the two ends of this integrating capacitor are coupled to negative input end and this output terminal of this operational amplifier respectively; And the 4th on-off circuit, first end and second end are coupled to negative input end and this output terminal of this operational amplifier respectively, described the 4th on-off circuit is used in response to the accurate conducting in activation position of first control signal, come short circuit to connect negative input end and this output terminal of this operational amplifier, and set the negative input end of this operational amplifier and the voltage of this output terminal is the 4th voltage.

Capacitance measurement circuit of the present invention, in one embodiment, this integrator circuit also comprises second integral electric capacity and the 5th on-off circuit, this second integral electric capacity and the 5th on-off circuit are connected in series in the negative input end of this operational amplifier and this output terminal, the 5th on-off circuit is used for the conducting in response to the activation position standard of second control signal, make this first and this second integral electric capacity for being connected in parallel.

Capacitance measurement circuit of the present invention, this processor circuit comprises: comparator circuit, be used for the accurate height in position of more described integral voltage and the 4th voltage, export the 3rd control signal; First logical circuit judges whether described the 3rd control signal satisfies trigger condition in being used for during described first integral, and when the 3rd control signal satisfies trigger condition, triggers control event; Second logical circuit produces this first class frequency signal in being used for during described first integral and drives this first control circuit, and is used for producing this second class frequency signal in response to this control event, drives this second control circuit; Counter circuit is used for during this first integral, in response to this control event count value is increased progressively 1, during this first integral after, this counter circuit is as this number of operations output with this count value; And breech lock (Latch) circuit, the activation position standard in order in response to the breech lock control signal writes down this number of operations.

Capacitance measurement circuit of the present invention, in one embodiment, this first logical circuit also is used for during voltage is set, and this first control signal of activation drives this integrator circuit and sets this integral voltage and be this start bit standard; Wherein, this counter circuit also is used in response to accurate this count value of resetting in the activation position of this first control signal.

Capacitance measurement circuit of the present invention, in one embodiment, first logical circuit also is used for determining during capacitance is set this signal numerical value of this setting signal, makes this capacitance adjustable variable road have this equivalence capacitance; Wherein, this first logical circuit also is used for this capacitance set during disabled second control signal, close the 5th on-off circuit in this integrator circuit.

Capacitance measurement circuit of the present invention, in one embodiment, this processor circuit also comprises: pierce circuit, being used for vibration produces the 3rd frequency signal and the 4th frequency signal, the the 3rd and the 4th frequency signal is for anti-phase basically, and this second logical circuit also produces this first group and this second class frequency signal in response to the 3rd and the 4th frequency signal.

Capacitance measurement circuit of the present invention, in one embodiment, this processor circuit comprises: comparator circuit, be used for the relatively accurate height in position of this integral voltage and the 4th voltage, export the 3rd control signal; First logical circuit, with the initial time point that decides during this first integral, and be used for judging whether the 3rd control signal satisfies trigger condition, when the 3rd control signal satisfies trigger condition, this first logical circuit decides the termination time point during the described first integral, and triggers control event; Second logical circuit, produce this first class frequency signal in being used for during second integral and drive this first control circuit, and be used for driving this second control circuit by this second class frequency signal of generation during this first integral of this initial and described termination time point definition; Counter circuit is used for during this first integral, every this second group of control signal sequential cycle count value is increased progressively 1, calculates this number of operations; And breech lock (Latch) circuit, be used for activation position standard in response to the breech lock control signal, write down this number of operations.

The present invention proposes a kind of measured capacitance value method, comprise the following steps: that (a) carries out the first adjustment operation in response to the voltage that the first class frequency signal switches at least one end on testing capacitance and capacitance adjustable variable road, is adjusted into the integral voltage on the end of integrating capacitor the present position standard and the first difference voltage sum of integral voltage.First difference voltage is relevant with the difference of the equivalent capacitance value that the capacitance and the capacitance adjustable variable of testing capacitance hold.(b) repeat previous step N time, integral voltage is adjusted into second standard from first standard, N is a natural number.(c) in response to the second class frequency signal, the voltage that switches at least one end of known capacitance is carried out the second adjustment operation, integral voltage is adjusted into the present position standard and the second difference voltage sum of integral voltage.(d) judge whether to receive first control event, if not, repeated execution of steps (c); If, execution in step (e), (e) between the decision integration period, and the frequency period of the second class frequency signal that comprises in calculating between integration period counts M, and calculates the capacitance of this testing capacitance according to the capacitance of numerical value M, N and known capacitance.

Measured capacitance value method of the present invention, in one embodiment, in step (a) before, also comprise: the position standard of setting this integral voltage equals the start bit standard.

Measured capacitance value method of the present invention in one embodiment, in step (a) before, also comprises: (g) provide setting signal to set this equivalence capacitance on this capacitance adjustable variable road; (h) in response to the 3rd class frequency signal, switch the voltage of at least one end at least one end of this testing capacitance and this capacitance adjustable variable road, carry out the 3rd and adjust operation, with be stored in this integral voltage on the end of this integrating capacitor be adjusted into the present position of this integral voltage accurate with this first difference voltage sum, the difference of the capacitance of this first difference voltage and this testing capacitance and the equivalent capacitance value of this capacitance adjustable variable appearance is relevant; (i) repeat L step previous step (h), so that this integral voltage is adjusted into second standard from first standard, L is a natural number; Judge whether this integral voltage satisfies critical condition, if not, execution in step (k), if, execution in step (l); (k) adjust the numerical value of this setting signal, and repeated execution of steps (h); Reach this equivalence capacitance that (l) determines this capacitance adjustable variable road with the numerical value of this present setting signal.

Measured capacitance value method of the present invention wherein, in step (g) and (h), also comprises: (m) in response to control signal, reduce the equivalent capacitance value of described integrating capacitor.

The present invention proposes a kind of measured capacitance value method, comprises the following steps.(a) voltage that switches at least one end of known capacitance in response to the first class frequency signal is carried out first and is adjusted operation, with the integral voltage on the end of integrating capacitor be adjusted into the present position of integral voltage accurate with the first difference voltage sum.(b) repeat previous step N time, integral voltage is adjusted into second standard from first standard, N is a natural number.(c) voltage that switches at least one end on testing capacitance and capacitance adjustable variable road in response to the second class frequency signal is carried out second and is adjusted operation, integral voltage is adjusted into the accurate and second difference voltage sum in present position of integral voltage, second difference voltage is relevant with the difference of the equivalent capacitance value that the capacitance and the capacitance adjustable variable of testing capacitance hold, (d) judge whether to receive first control event, if not, repeated execution of steps (c); If, execution in step (e), (e) between the decision integration period, and calculated product divide during in the frequency period of the second class frequency signal that comprises count M, and calculate the capacitance of testing capacitance according to the capacitance of numerical value M, N and known capacitance.

Measured capacitance value method of the present invention in step (a) before, also comprises: the position standard of (f) setting this integral voltage equals the start bit standard.

Measured capacitance value method of the present invention in step (a) before, also comprises: (g) provide setting signal to set this equivalence capacitance on this capacitance adjustable variable road; (h) in response to the 3rd class frequency signal, switch the voltage of at least one end at least one end of this testing capacitance and this capacitance adjustable variable road, carry out the 3rd and adjust operation, with be stored in this integral voltage on the end of this integrating capacitor be adjusted into the present position of this integral voltage accurate with this first difference voltage sum, the difference of the capacitance of this first difference voltage and this testing capacitance and the equivalent capacitance value of this capacitance adjustable variable appearance is relevant; (i) repeat L step (h), so that this integral voltage is adjusted into second standard from first standard, L is a natural number; (j) judge whether this integral voltage satisfies critical condition, if not, execution in step (k), if, execution in step (l); (k) adjust the numerical value of this setting signal, and repeated execution of steps (h); Reach this equivalence capacitance that (l) determines this capacitance adjustable variable road with the numerical value of this present setting signal.

Measured capacitance value method of the present invention wherein, in step (g) and (h), also comprises: (m) in response to control signal, reduce the equivalent capacitance value of this integrating capacitor.

Propose a kind of measured capacitance value method according to the present invention, be used between integration period the capacitance to testing capacitance to measure, it comprises the following steps.(a) voltage that switches at least one end on testing capacitance and capacitance adjustable variable road in response to the first class frequency signal is carried out first and is adjusted operation, with be stored in integral voltage on the end of integrating capacitor be adjusted into the present position of integral voltage accurate with the first difference voltage sum, first difference voltage is relevant with the difference of the equivalent capacitance value of testing capacitance and capacitance adjustable variable appearance.(b) judge whether to receive first control event; If not, repeat previous step; (c) if, carry out next procedure, count value is increased progressively 1, (d) switch the voltage of at least one end of known capacitance and in an operating period, carry out second and adjust operation, with integral voltage be adjusted into the present position of integral voltage accurate with second difference voltage and, second difference voltage is relevant with the capacitance of known capacitance.(e) judge between integration period whether stop, if not, repeat first step; (f) if, carry out next procedure, obtain between integration period according to count value in second control circuit carry out second and adjust the number of operations of operating, and obtain the capacitance of testing capacitance according to the capacitance computing of number of operations and known capacitance.

Measured capacitance value method of the present invention in one embodiment, does not receive this first control event if judge in step (b), then execution in step (e) judges between described integration period whether stop, if not, execution in step (a), if, execution in step (f).

Measured capacitance value method of the present invention in one embodiment, receives this first control event if judge in step (b), then execution in step (e) judges between described integration period whether stop, if not, execution in step (c), if, execution in step (f).

Measured capacitance value method of the present invention in one embodiment, in step (c) execution in step (e) afterwards, judges between this integration period whether stop, if not, and execution in step (d), if, execution in step (f).

Measured capacitance value method of the present invention in one embodiment, in step (d) execution in step (e) afterwards, judges between this integration period whether stop, if not, and execution in step (a), if, execution in step (f).

Measured capacitance value method of the present invention, in one embodiment, (a) also comprises before in step: the position standard of (g) setting this integral voltage equals the start bit standard.

Measured capacitance value method of the present invention in one embodiment, in step (a) before, also comprises: (h) provide setting signal to set this equivalence capacitance on this capacitance adjustable variable road; (i) in response to the 3rd class frequency signal, switch the voltage of at least one end at least one end of this testing capacitance and this capacitance adjustable variable road, carry out the 3rd and adjust operation, with be stored in this integral voltage on the end of this integrating capacitor be adjusted into the present position of this integral voltage accurate with this first difference voltage sum, the difference of the capacitance of this first difference voltage and this testing capacitance and the equivalent capacitance value of this capacitance adjustable variable appearance is relevant; (j) repeat L step (i), so that this integral voltage is adjusted into second standard from first standard, L is a natural number; (k) judge whether this integral voltage satisfies critical condition, if not, execution in step (l), if, execution in step (m); (l) adjust the numerical value of this setting signal, and repeated execution of steps (h); Reach this equivalence capacitance that (m) determines this capacitance adjustable variable road with this present setting signal specified number value.

Measured capacitance value method of the present invention in one embodiment, in step (h) and (i), also comprises: (n) in response to control signal, reduce the equivalent capacitance value of this integrating capacitor.

Measured capacitance value method of the present invention, in one embodiment, in step (c), also comprise: (c1) in described operating period, switch the voltage of at least one end at least one end of this testing capacitance and this capacitance adjustable variable road in response to this first class frequency signal, carry out this adjustment operation, this integral voltage is adjusted into accurate and this first difference voltage sum in present position of this integral voltage; And (c2) in this operating period, switch the voltage of at least one end of this known capacitance in response to the second class frequency signal, carry out the 3rd and adjust operation, with this integral voltage be adjusted into the present position of described integral voltage accurate with the 3rd difference voltage sum; Wherein, this second difference voltage is substantially equal to this first and the 3rd difference voltage sum.

For foregoing of the present invention can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:

Description of drawings

Fig. 1 shows the block scheme according to the capacitance measurement circuit of first embodiment of the invention.

Fig. 2 shows the coherent signal sequential chart of the capacitance measurement circuit 10 of Fig. 1.

Fig. 3 shows the more detailed block diagram of the processor circuit 18 of Fig. 1.

Fig. 4 shows the more detailed block diagram of the logical block 18a2 of Fig. 3.

Fig. 5 shows the process flow diagram according to the measured capacitance value method of first embodiment of the invention.

Fig. 6 shows the opposing party's block diagram according to the capacitance measurement circuit of first embodiment of the invention.

Fig. 7 shows the coherent signal sequential chart of the capacitance measurement circuit 20 of Fig. 6.

Fig. 8 A and 8B show the part more detailed block diagram according to the capacitance measurement circuit of second embodiment of the invention.

Fig. 9 shows the more detailed block diagram of logical block 38a2 among Fig. 8 B.

Figure 10 shows the coherent signal sequential chart of the capacitance measurement circuit 30 of Fig. 8 A and 8B.

Figure 11 A-11C shows the process flow diagram according to the measured capacitance value method of second embodiment of the invention.

Figure 12 shows the opposing party's block diagram according to the capacitance measurement circuit of second embodiment of the invention.

The coherent signal sequential chart that Figure 13 shows capacitance measurement circuit according to the embodiment of the invention when carrying out the capacitance setting operation.

Figure 14 shows the dependence diagram according to the capacitance establishing method of the embodiment of the invention.

Embodiment

The capacitance testing circuit of present embodiment is to come the voltage on one section is carried out integration operation by testing capacitance, capacitance adjustable variable road and known capacitance, and the ratio of the running time that corresponds to charging operations and discharge operation and the capacitance of known capacitance calculate the capacitance of testing capacitance.

First embodiment

The capacitance measurement circuit of present embodiment is to carry out the capacitance variation amount that diclinic rate (Dual-slope) algorithm computation obtains testing capacitance.Please refer to Fig. 1, it shows the block scheme according to the capacitance measurement circuit of first embodiment of the invention.Capacitance measurement circuit 10 comprises control circuit 12,14, integrator circuit 16 and processor circuit 18.Control circuit 12 and 14 is used for controlling integrator circuit 16 respectively integral voltage Vx is set at the stop bit standard from the start bit standard, and its self termination position standard is set at the start bit standard.For example, the start bit standard equals reference voltage VR, and the position standard of stop bit standard is higher than the start bit standard.Processor circuit 18 is used for producing corresponding signal Drive and Control Circuit 12,14 and integrator circuit 16 is carried out aforementioned operation, and is used in response to the accurate computing that changes the capacitance that carries out testing capacitance Cx in the position of integral voltage Vx.Next, the operation to each element in the capacitance measurement circuit 10 is described further.

Integrator circuit 16 comprises input end ndi, output terminal ndo, switch S c1, integrating capacitor Ci and operational amplifier (Operational Amplifier) OP1, and the voltage on the output terminal ndo is integral voltage Vx.Comprise capacitor C i1, Ci2 and switch S C2 among the integrating capacitor Ci, switch S C2 makes the capacitance of integrating capacitor Ci be substantially equal to capacitor C i1 and Ci2 sum in response to the control signal CS5 conducting of activation.The two ends of the two ends of switch S c1 and integrating capacitor Ci are cross-over connection negative input end and output terminal ndo in operational amplifier OP1, the control signal CS1 conducting that switch S c1 is enabled.The positive input terminal of operational amplifier OP1 is to receive reference voltage VR.Wherein, reference voltage VR is the ceiling voltage VDD of capacitance measurement circuit 10 of present embodiment and any specific reference voltage between ground voltage, and for example, reference voltage VR is substantially equal to voltage VDD/2.

Control circuit 12 comprises output terminal OE1, on-off circuit SW1, SW2, testing capacitance Cx and capacitance adjustable variable road Cadj.On-off circuit SW1 comprises switch S a1 and Sa2, and the end of switch S a1 and Sa2 is the section of being coupled to nd1, and the other end receives voltage Vf1 respectively and is coupled to the negative input end of operational amplifier OP1.Frequency signal CK_a1 that switch S a1 and Sa2 are enabled respectively and CK_a2 conducting.The two ends of testing capacitance Cx are the section of being coupled to nd1 and reception voltage Vf1 respectively.Voltage Vf1 for example is a ground voltage.

On-off circuit SW2 comprises switch S a3 and Sa4, and the end of switch S a3 and Sa4 is the section of being coupled to nd2, and the other end receives voltage Vf2 respectively and is coupled to the negative input end of operational amplifier OP1.Voltage Vf2 for example is ceiling voltage VDD.Frequency signal CK_a1 that switch S a3 and Sa4 are enabled respectively and CK_a2 conducting.The two ends of capacitance adjustable variable road Cadj are the section of being coupled to nd2 and reception voltage Vf1 respectively.The signal numerical value of the setting signal Sadj that capacitance adjustable variable road Cadj provides in response to processor circuit 18, the decision equivalent capacitance value.In the present embodiment, processor circuit 18 provides corresponding setting signal Sadj, and the equivalent capacitance value of setting capacitance adjustable variable road Cadj is substantially equal to the capacitance of testing capacitance Cx.

Control circuit 14 comprises output terminal OE2, on-off circuit SW3 and known capacitance Cc, and it is the section of being coupled to nd3.On-off circuit SW3 comprises switch Sb 1 and Sb2, and the one end section of being coupled to nd3, the other end receive voltage Vf2 respectively and be coupled to the negative input end of operational amplifier OP1.Frequency signal CK_b1 that switch Sb 1 and Sb2 are enabled respectively and CK_b2 conducting.The two ends of known capacitance Cc are the section of being coupled to nd3 and reception voltage Vf1 respectively.

Please refer to Fig. 2, it illustrates the coherent signal sequential chart of the capacitance measurement circuit 10 of Fig. 1.The capacitance measurement circuit 10 of present embodiment for example comprise voltage set during TP_IT1 and TP_IT2 between TP_PS, integration period.In an example, control signal CS5 is activation among TP_IT1 and the TP_IT2 between TP_PS, integration period during setting, make the capacitance of integrating capacitor Ci be substantially equal to capacitor C i1 and Ci2 and.

Among the TP_PS, processor circuit 18 is activation control signal CS1, with actuating switch Sc1 during voltage is set.Like this, operational amplifier OP1 is biased basically to be a unity gain buffer (Unit Gain Buffer), and the positive and negative input end of operational amplifier OP1 and the voltage on the output terminal ndo (promptly being integral voltage Vx) are set to reference voltage VR.

Among the TP_IT1, processor circuit 18 provides frequency signal CK_a1 and CK_a2 between integration period, with actuating switch Sa1～Sa4 accordingly.Wherein, frequency signal CK_a1 and CK_a2 are high levels in for example respectively during first and second child-operation, and be low level in respectively during second and first child-operation, equal respectively during first and second child-operation between the positive half cycle and negative half-cycle of frequency signal CK_a1.In every cycle through a frequency signal CK_a1, integrator circuit 16 is finished once the integration operation to integral voltage Vx.

In more detail, during first child-operation among the TP1, switch S a1 and Sa3 are that conducting and switch S a2 and Sa4 are for closing, the cross-pressure at testing capacitance Cx and integrating circuit Ci two ends is 0 volt of (Volt, V), the cross-pressure at Cadj two ends, capacitance adjustable variable road is that (Volt V), for example is ceiling voltage VDD to the Vf2-Vf1 volt.During second child-operation among the TP2, switch S a1 and Sa3 are for closing and switch S a2 and Sa4 are conducting.Because the section ndi (being the negative input end of operational amplifier OP1) that testing capacitance Cx and capacitance adjustable variable road Cadj and integrating capacitor Ci couple mutually is suspension joint (Floating) among the TP2 during second child-operation, the total electrical charge that testing capacitance Cx, capacitance adjustable variable road Cadj and integrating capacitor Ci store among the TP1 during first child-operation is substantially equal to the total electrical charge that it stores among TP2 during second child-operation, promptly be to satisfy equation:

(1)Cx×(Vf1-Vf1)+Cadj×(Vf2-Vf1)+Ci×[VR-Vx(t0)]＝

Cx×(VR-Vf)+Cadj×(VR-Vf)+Ci×[VR-Vx(t1)]

Wherein the levoform of equation (1) is the total electrical charge that testing capacitance Cx, capacitance adjustable variable road Cadj and integrating capacitor Ci store among the TP1 during first child-operation, and right formula be the total electrical charge of testing capacitance Cx, capacitance adjustable variable road Cadj and integrating capacitor Ci storage among the TP2 during second child-operation.Voltage level Vx (t0) is the start bit standard of integral voltage Vx (being substantially equal to reference voltage VR).If reference voltage VR equals the average voltage of voltage Vf1 and voltage Vf2, then can push away according to aforesaid equation:

$\left(2\right)---\mathrm{Vx}\left(t1\right)=\frac{1}{\mathrm{Ci}}\&times;[\frac{(\mathrm{Vf}2-\mathrm{Vf}1)}{2}\&times;(\mathrm{Cx}-\mathrm{Cadj})+\frac{\mathrm{<figure-callout\; id="2"\; label="Vf"\; filenames="A2008102108570039H1.png,A2008102108570042H1.png"\; state="\{\{state\}\}">Vf</figure-callout>}2+\mathrm{<figure-callout\; id="1"\; label="Vf"\; filenames="A2008102108570037H1.png,A2008102108570038H1.png"\; state="\{\{state\}\}">Vf</figure-callout>}1}{2}\&times;\mathrm{Ci}]$

$\left(3\right)---\mathrm{\&Delta;<figure-callout\; id="1"\; label="V"\; filenames="A2008102108570037H1.png,A2008102108570038H1.png"\; state="\{\{state\}\}">V</figure-callout>}1=\mathrm{Vx}\left(t1\right)-\mathrm{Vx}\left(t0\right)=\frac{1}{\mathrm{Ci}}\&times;[\frac{(\mathrm{Vf}2-\mathrm{Vf}1)}{2}\&times;(\mathrm{Cx}-\mathrm{Cadj})+\frac{\mathrm{<figure-callout\; id="2"\; label="Vf"\; filenames="A2008102108570039H1.png,A2008102108570042H1.png"\; state="\{\{state\}\}">Vf</figure-callout>}2+\mathrm{<figure-callout\; id="1"\; label="Vf"\; filenames="A2008102108570037H1.png,A2008102108570038H1.png"\; state="\{\{state\}\}">Vf</figure-callout>}1}{2}\&times;\mathrm{Ci}]-\mathrm{VR}=$

$\frac{(\mathrm{Cx}-\mathrm{Cadj})\&times;(\mathrm{Vf}2-\mathrm{Vf}1)}{2\&times;\mathrm{Ci}}$

According to above-mentioned derivation as can be known, through after integration operation, integral voltage Vx promotes a difference voltage Δ V1 basically.The cycle that for example comprises N frequency signal CK_a1 between integration period among the TP_IT1, control circuit 12 and integrator circuit 16 repeat N time to above-mentioned similar integration operation, be the accurate Vx of stop bit (tN) so that integral voltage Vx is promoted from its start bit standard (=reference voltage VR).Wherein, N is a natural number, and the accurate Vx of stop bit (tN) satisfies:

$\left(4\right)---\mathrm{Vx}\left(\mathrm{tN}\right)=N\&times;\left[\frac{(\mathrm{Cx}-\mathrm{Cadj})\&times;(\mathrm{Vf}2-\mathrm{Vf}1)}{2\&times;\mathrm{Ci}}\right]+\mathrm{VR}$

Among the TP_IT2, processor circuit 18 provides frequency signal CK_b1 and CK_b2 between integration period, comes Drive and Control Circuit 14 to carry out the operation close with control circuit 12, so that integral voltage Vx is carried out integration.Wherein, difference voltage Δ V2 satisfies:

$\left(5\right)---\mathrm{\&Delta;<figure-callout\; id="2"\; label="V"\; filenames="A2008102108570039H1.png,A2008102108570042H1.png"\; state="\{\{state\}\}">V</figure-callout>}2=\frac{\mathrm{Cc}\&times;(\mathrm{Vf}1-\mathrm{Vf}2)}{2\&times;\mathrm{Ci}}$

According to above-mentioned derivation as can be known, in integration operation, the integral voltage Vx difference voltage Δ V2 that descends.TP_IT2 for example comprises the cycle of M frequency signal CK_b1 between the integration period of present embodiment, and in the cycle of each frequency signal CK_b1, control circuit 14 is to carry out similar integration operation to integrator circuit 16, and M is a natural number.Like this, by carrying out above-mentioned integration operation repeatedly M time, integral voltage Vx dragged down from the accurate Vx of its stop bit (tN) being the accurate VR of start bit, promptly is to satisfy equation:

$\left(6\right)---\mathrm{VR}=\mathrm{Vx}\left(\mathrm{tN}\right)+M\&times;\mathrm{\&Delta;<figure-callout\; id="2"\; label="V"\; filenames="A2008102108570039H1.png,A2008102108570042H1.png"\; state="\{\{state\}\}">V</figure-callout>}2=N\&times;\left[\frac{(\mathrm{Cx}-\mathrm{Cadj})\&times;(\mathrm{Vf}2-\mathrm{Vf}1)}{2\&times;\mathrm{Ci}}\right]+\mathrm{VR}+M\&times;\left[\frac{\mathrm{Cc}\&times;(\mathrm{Vf}1-\mathrm{Vf}2)}{2\&times;\mathrm{Ci}}\right]$

Can obtain the relational expression of equivalent capacity, numerical value M, N and the known capacitance Cc of testing capacitance Cx, capacitance measurement circuit Cadj after the arrangement:

$\left(7\right)---\mathrm{Cx}-\mathrm{Cadj}=\frac{M}{N}\&times;\mathrm{Cc}$

Like this, processor circuit 18 also tries to achieve according to the capacitance of numerical value M, N, known capacitance Cc and capacitance adjustable variable road Cadj the capacitance of testing capacitance Cx according to aforesaid equation.

Please refer to Fig. 3, it illustrates the more detailed block diagram of the processor circuit 18 of Fig. 1.In more detail, processor circuit 18 comprises logical circuit 18a, comparator circuit 18b, pierce circuit 18c, counter circuit 18d, latch unit circuit 18e and computing circuit 18f.Logical circuit 18a comprises logical block 18a1 and 18a2.Logical block 18a2 is used for producing frequency signal CK_a1 and CK_a2 in response to the control signal CS2 of activation, and is used for producing frequency signal CK_b1 and CK_b2 in response to the control signal CS3 of activation.

For instance, the more detailed block diagram of logical block 18a2 is shown as shown in Figure 4.Wherein, logic lock and_1 and and_3 produce frequency signal CK_a1 and CK_b1 respectively according to the frequency signal CK_1 that pierce circuit 18c produces, and logic lock and_2 and and_4 produce frequency signal CK_a2 and CK_b2 respectively according to the frequency signal CK_2 that pierce circuit 18c produces.

Logical block 18a1 is used for that TP_PS produces control signal CS1 during voltage is set, and controls integrator circuit 16 voltage of charging voltage Vx is set at reference voltage VR.Logical block 18a1 is used among the TP_IT1 and TP_IT2, producing the control signal CS2 and the CS3 of activation respectively between integration period, comes steering logic unit 18a2 to produce frequency signal CK_a1 and CK_a2, CK_b1 and CK_b2.Logical block 18a1 also is used for writing down the cycle length what frequency signal CK_1 TP_IT2 between integration period corresponds to.

In the present embodiment, logical block 18a1 with decide and between integration period the initial time point Tx1 of TP_IT2 produce the control signal CS3 of activation.Whether logical block 18a1 also is used for detecting control event and triggers, and decides the termination time point Tx2 of TP_IT2 between integration period in response to this control event.

For instance, this control event is the incident of activation for the control signal CS4 that comparator circuit 18b produces.Comparator circuit 18b is used for receiving and comparing the position standard of integral voltage Vx and reference voltage VR, and produces control signal CS4 accordingly.As integral voltage Vx during greater than reference voltage VR, control signal CS4 is disabled.When the position of integral voltage Vx standard during basically less than reference voltage VR, comparator circuit 18b activation control signal CS4.Like this, by the control event that response comparator circuit 18b triggers, logical block 18a1 can determine the termination time point Tx2 of TP_IT2 between integration period effectively.

Logical block 18a1 for example is used for activation drive signal En between time point Tx1 and Tx2, and increase progressively 1 counting operation the cycle length (equaling the cycle of frequency signal CK_b1) of coming actuation counter circuit 18d to carry out every a frequency signal CK_1.Like this, the processor circuit 18 of present embodiment can obtain numerical value M by the counting operation of counter circuit 18d.

Counter circuit 18d for example is an i digit counter circuit, and its counting produces and export i bit data Bit_1～Bit_i of numerical value M to latch unit circuit 18e.Latch unit circuit 18e is used for receiving and the record latch data, and latch data comprises bit data Bit_1～Bit_i.Arithmetic element 18f obtains numerical value M according to bit data Bit_1～Biti that latch unit circuit 18e stores, and obtains the capacitance of testing capacitance Cx according to the relational expression of aforementioned testing capacitance Cx and numerical value M, N and known capacitance Cc.

Logical block 18a1 also is used for after the TP_IT2, in turn producing latch-up signal Srdy and reset signal Srst between integration period.Like this, latch unit circuit 18e lives the output valve of counter circuit 18d in response to latch-up signal Srdy breech lock.After latch unit circuit 18e finished breech lock and lives the operation of this output valve, counter circuit 18d was in response to reset signal Srst its count value of resetting.Latch unit circuit 18e and counter circuit 18d finish latch operations and the operation of resetting after, processor circuit 18 can carry out the measuring operation of testing capacitance next time.

The logical block 18a1 of present embodiment also is used for writing down numerical value of N, and decides TP_IT1 between integration period to comprise the cycle of what frequency signal CK_1 according to numerical value of N.In the present embodiment, numerical value of N (being the number in the cycle of the frequency signal CK_a1 that comprises among the TP_IT1 between integration period) is for adjustable, by adjusting numerical value of N, the user can make the capacitance measurement circuit 10 of present embodiment be applicable to the testing capacitance Cx that measures different capacitance scopes.

Please refer to Fig. 5, it illustrates the process flow diagram according to the measured capacitance value method of first embodiment of the invention.At first as step (a), control circuit 12 switches the voltage of at least one end of testing capacitance Cx and capacitance adjustable variable road Cadj in response to frequency signal CK_a1 and CK_a2, with integral voltage Vx be adjusted into the present position of integral voltage Vx accurate with difference voltage Δ V1's and.Then as step (b), control circuit 12 repeats N step (a) in response to frequency signal CK_a1 and CK_a2, and integral voltage Vx is adjusted into the accurate Vx of stop bit (tN) from the accurate VR of start bit.

As step (c), control circuit 14 is adjusted integral voltage Vx the accurate and difference voltage Δ V2 sum in present position of this integral voltage Vx in response to the voltage of at least one end of frequency signal CK_b1 and CK_b2 switching known capacitance Cc then.Then as step (d), the logical block 18a1 in the processor circuit 18 judges whether to receive control event, if not, and repeated execution of steps (c); If, execution in step (e).For instance, control event is the incident of activation for control signal CS4.

As step (e), processor circuit 18 determines TP_IT2 between integration period then, and the frequency period of the frequency signal CK_b1 that comprises among the TP_IT2 during the calculated product branch is counted M.Processor circuit 18 also calculates the capacitance variation amount of testing capacitance Cx according to the capacitance of numerical value M, N and known capacitance Cc.

In an example, also comprise step (f) before in step (a), processor circuit 18 produces control signal CS1 actuating switch Sc1, and the position standard of integral voltage Vx is set at start bit standard (promptly being the position standard of reference voltage VR).

In the present embodiment, though only the example that has a circuit structure as shown in Figure 1 with capacitance measurement circuit 10 explains, still, the capacitance measurement circuit 10 of present embodiment is not limited to have circuit structure as shown in Figure 1.In another example, the capacitance measurement circuit of present embodiment also can be as shown in Figure 6.

Capacitance measurement circuit 20 and 10 difference are that the on-off circuit SW2 ' in the control circuit 22 comprises switch S a31, Sa32, Sa41 and Sa42, and the on-off circuit SW3 ' in the control circuit 24 comprises switch Sb 11, Sb12, Sb21 and Sb22.The narration relevant according to aforementioned and capacitance measurement circuit 10, if reference voltage VR ' equals voltage Vf2 ', can put in order and obtain similar equation:

(8)Cx×(Vf1-Vf1)+Cadj×(Vf2′-Vf1)+Ci×(Vf2′-Vf2′)＝

Cx×(Vf2′-Vf1)+Cadj×(Vf2′-Vf2′)+Ci×(Vf2′-Vx(t1))

$\left(9\right)---\mathrm{\&Delta;<figure-callout\; id="1"\; label="V"\; filenames="A2008102108570037H1.png,A2008102108570038H1.png"\; state="\{\{state\}\}">V</figure-callout>}1=\mathrm{Vx}\left(t1\right)-\mathrm{<figure-callout\; id="2"\; label="Vf"\; filenames="A2008102108570039H1.png,A2008102108570042H1.png"\; state="\{\{state\}\}">Vf</figure-callout>}{2}^{\&prime;}=\frac{1}{\mathrm{Ci}}\&times;[\mathrm{Cx}\&times;({\mathrm{<figure-callout\; id="2"\; label="Vf"\; filenames="A2008102108570039H1.png,A2008102108570042H1.png"\; state="\{\{state\}\}">Vf</figure-callout>}2}^{\&prime;}-\mathrm{Vf}1)+\mathrm{Cadj}\&times;(\mathrm{Vf}1-{\mathrm{<figure-callout\; id="2"\; label="Vf"\; filenames="A2008102108570039H1.png,A2008102108570042H1.png"\; state="\{\{state\}\}">Vf</figure-callout>}2}^{\&prime;})]=\frac{(\mathrm{Cx}-\mathrm{Cadj})\&times;({\mathrm{<figure-callout\; id="2"\; label="Vf"\; filenames="A2008102108570039H1.png,A2008102108570042H1.png"\; state="\{\{state\}\}">Vf</figure-callout>}2}^{\&prime;}-\mathrm{Vf}1)}{\mathrm{Ci}}$

$\left(10\right)---\mathrm{\&Delta;<figure-callout\; id="2"\; label="V"\; filenames="A2008102108570039H1.png,A2008102108570042H1.png"\; state="\{\{state\}\}">V</figure-callout>}2=\frac{\mathrm{Cc}\&times;(\mathrm{Vf}1-{\mathrm{<figure-callout\; id="2"\; label="Vf"\; filenames="A2008102108570039H1.png,A2008102108570042H1.png"\; state="\{\{state\}\}">Vf</figure-callout>}2}^{\&prime;})}{\mathrm{Ci}}$

$\left(11\right)---{\mathrm{<figure-callout\; id="2"\; label="Vf"\; filenames="A2008102108570039H1.png,A2008102108570042H1.png"\; state="\{\{state\}\}">Vf</figure-callout>}2}^{\&prime;}={\mathrm{<figure-callout\; id="2"\; label="Vf"\; filenames="A2008102108570039H1.png,A2008102108570042H1.png"\; state="\{\{state\}\}">Vf</figure-callout>}2}^{\&prime;}+N\&times;\mathrm{\&Delta;<figure-callout\; id="1"\; label="V"\; filenames="A2008102108570037H1.png,A2008102108570038H1.png"\; state="\{\{state\}\}">V</figure-callout>}1+M\&times;\mathrm{\&Delta;<figure-callout\; id="2"\; label="V"\; filenames="A2008102108570039H1.png,A2008102108570042H1.png"\; state="\{\{state\}\}">V</figure-callout>}2\&DoubleRightArrow;\mathrm{Cx}-\mathrm{Cadj}=\frac{M}{N}\&times;\mathrm{Cc}$

Like this, with capacitance measurement circuit 10 similarly, capacitance measurement circuit 20 also can be by similar integration operation, reach the capacitance of measuring testing capacitance Cx.Wherein, voltage Vf2 ' satisfies condition:

(12) Vf2′+N×ΔV1≤VDD

Avoiding before integral voltage Vx being finished N integration operation, with integral voltage Vx integration to ceiling voltage VDD.

Though the example of only receiving voltage Vf1 with the termination of testing capacitance Cx in Fig. 6 explains, still, the end of testing capacitance Cx is not limited to receive voltage Vf1, but also can receive other any voltage between ceiling voltage VDD and ground voltage.

In the present embodiment, though only the example that is higher than the accurate Vx of start bit (t0) with the position standard of the accurate Vx of stop bit (tN) explains, still, it is accurate that the accurate Vx of stop bit (tN) is not limited to the position that is higher than the accurate Vx of start bit (t0).In another example, the stop bit standard is lower than the start bit standard.Like this, between integration period among the TP_IT1, capacitance measurement circuit 10 is less than 0 difference voltage Δ V1 integral voltage Vx to be reduced to the stop bit standard from its start bit standard basically by accumulation.Between integration period among the TP_IT2, capacitance measurement circuit 10 is greater than 0 difference voltage Δ V2 integral voltage Vx to be its start bit standard from accurate lifting of its stop bit basically by accumulation.

In the present embodiment, though be that example explains only in turn to control the situation that integrator circuit 16 carries out integration operation after the TP_PS during voltage is set by control circuit 12 and 14, but the capacitance measurement circuit 10 of present embodiment is not limited in turn to control integrator circuit 16 by control circuit 12 and 14 and operates.In another example, the capacitance measurement circuit 10 of present embodiment also can carry out integration operation by control circuit 14 control integrator circuits 16 earlier, carries out integration operation by control circuit 12 control integrator circuits 16 more afterwards.In other words, promptly be during voltage is set, in turn to enter TP_IT2 and TP_IT1 between integration period after the TP_PS.For instance, the coherent signal sequential chart of the capacitance measurement circuit 10 of Ci Shi Fig. 1 is as shown in Figure 7.

The capacitance measurement circuit of present embodiment comes integral voltage is carried out integration operation with the capacitance difference on testing capacitance and capacitance adjustable variable road.Compare with the technology of directly carrying out integration operation with testing capacitance traditionally, the capacitance of the equivalent point electric capacity of the capacitance measurement circuit of present embodiment is less.Like this, according to equation (3) as can be known, under integrating capacitor, testing capacitance and ceiling voltage were identical condition, the capacitance measurement circuit of present embodiment had the less and integral voltage of difference voltage Δ V1 and is integrated in being not easy during first integral and measures wrong advantage to ceiling voltage.

In addition, traditionally, be the size that reduces difference voltage Δ V1 by the bigger integrating capacitor of use capacitance, generally speaking, the integrating capacitor of traditional capacitance value metering circuit is can't be incorporated in the integrated circuit (IC).Because the capacitance of the equivalent point electric capacity of the capacitance measurement circuit of present embodiment is less, under difference voltage Δ V1 and ceiling voltage voltage were identical condition, the capacitance measurement circuit of present embodiment can use the lower integrating capacitor of capacitance.So, make the capacitance measurement circuit of present embodiment also have and integrating capacitor can be integrated in the integrated circuit and the advantage that can save circuit cost.

In addition, because the equivalent capacity on capacitance adjustable variable road is substantially equal to the capacitance of testing capacitance, when the capacitance of testing capacitance did not change, the difference on testing capacitance and capacitance adjustable variable road was near 0.Like this, according to equation (3) as can be known, under the condition that the capacitance of testing capacitance does not change, even if ceiling voltage changes to some extent because of circuit noise, difference voltage Δ V1 still remains 0.Like this, the capacitance measurement circuit of present embodiment also has the advantage that noise limit (Noise Margin) is higher and can measure changes in capacitance amount to be measured exactly.

Then, because the capacitance measurement circuit of present embodiment has less difference voltage Δ V1, under integrating capacitor and ceiling voltage are identical condition, the numerical value of N of the capacitance measurement circuit of present embodiment can be designed to higher numerical value, and still can guarantee to be integrated to ceiling voltage during integral voltage is not during first integral.According to equation (7) as can be known, the measured capacitance value resolution of capacitance measurement circuit is to promote accordingly along with the lifting of numerical value of N.Like this, the capacitance measurement circuit of present embodiment also has measured capacitance value resolution advantage of higher.

Second embodiment

The capacitance measurement circuit of present embodiment is to carry out the capacitance variation amount that trigonometric integral (Sigma-delta) algorithm computation obtains testing capacitance.Please refer to Fig. 8 A, 8B and Fig. 9, Fig. 8 A and 8B illustrate the part more detailed block diagram according to the capacitance measurement circuit of second embodiment of the invention, and Fig. 9 illustrates the more detailed block diagram of logical block 38a2 among Fig. 8 B.The capacitance measurement circuit 30 of present embodiment and the capacitance measurement circuit 10 of first embodiment have close structure, its difference be logic lock and 3 ' according to drive signal En, frequency signal CK_1 and control signal CS5 carry out logic and and (And) computing produce frequency signal CK_b1 ', logic lock and 4 ' carries out disjunction operation according to drive signal En, frequency signal CK_2 and control signal CS5 and produces frequency signal CK_b2 '.In addition, logical block 38a1 provides control signal CS1 reset signal as counter circuit 38d.

Please refer to Figure 10, it illustrates the coherent signal sequential chart of the capacitance measurement circuit 30 of Fig. 8 A and 8B.The capacitance measurement circuit 30 of present embodiment for example comprise voltage set during TP_IT3 between TP_PS ' and integration period, during wherein voltage is set between TP_PS ' and integration period the time span of TP_IT3 determined by processor circuit 38.For instance, comprise the cycle of X frequency signal CK_a1 ' between integration period among the TP_IT3, X is the natural number greater than 1.In an example, control signal CS5 TP_PS ' during voltage is set reaches between integration period and is activation among the TP_IT3, makes the capacitance of integrating capacitor Ci be substantially equal to capacitor C i1 and Ci2 sum.

During voltage is set among the TP_PS ', the operation that capacitance measurement circuit 30 is carried out is capacitance measurement circuit 10 operation among the TP_PS during voltage is set similar in appearance to first embodiment, and the control signal CS1 that processor circuit 38 provides activation is set to reference voltage VR with positive and negative input end and the integral voltage Vx of operational amplifier OP3.Wherein, different with the capacitance measurement circuit 10 of first embodiment, counter circuit 38d is a numerical value 0 in response to the control signal CS1 replacement enumeration data D_cnt of activation.In addition, as integral voltage Vx during more than or equal to reference voltage VR, the comparator circuit 38b of present embodiment produces the control signal CS4 of activation; As integral voltage Vx during less than reference voltage VR, comparator circuit 38b produces the control signal CS4 of disabled.

Among the TP_IT3, logical block 38a1 is the control signal CS2 ' that activation is provided constantly between integration period, drives logical block 38a2 and produces frequency signal CK_a1 ' and CK_a2 ' constantly.In addition, logical block 38a1 also is used for providing in response to the control signal CS4 of activation the drive signal En of activation.For instance, drive signal En is activation among the TP1 ' during operation, like this, logical block 38a2 produces frequency signal CK_b1 ' and CK_b2 ' in response to the drive signal of activation, control circuit 32 and 34 is simultaneously integral voltage Vx to be carried out integration operation, if reference voltage VR equals the average voltage of voltage Vf1 and voltage Vf2, equation is satisfied in the operation of this moment:

(13)Cx×(Vf1-Vf1)+Cadj×(Vf2-Vf1)+Cc×(Vf2-Vf1)+Ci×(VR-VR)＝

Cx×(VR-Vf1)+Cadj×(VR-Vf1)+Cc×(VR-Vf1)+Ci×(VR-Vx(t1))

$\left(14\right)---\mathrm{Vx}\left(t1\right)=\mathrm{Vx}\left(t0\right)+\mathrm{\&Delta;V}(-)=\mathrm{VR}+\frac{(\mathrm{Vf}2-\mathrm{Vf}1)\&times;(\mathrm{Cx}-\mathrm{Cadj}-\mathrm{Cc})}{2\mathrm{Ci}}$

In addition, counter circuit 38d makes enumeration data D_cnt increase progressively 1 (increased progressively by numerical value 0 and be numerical value 1) in response to the drive signal En of activation.

During operation TP1 ' afterwards, integral voltage Vx is pulled low to a position accurate Vx (t1), and is lower than reference voltage VR basically.Like this, control signal CS4 and drive signal En are disabled, and frequency signal CK_b1 ' and CK_b2 ' are by disabled.Like this, among the TP2 ', 32 couples of integral voltage Vx carry out integration operation by control circuit during operation during operation behind the TP1 ', and equation is satisfied in the operation of this moment:

(15)Cx×(Vf1-Vf1)+Cadj×(Vf2-Vf1)+Ci×(VR-Vx(t1))＝

Cx×(VR-Vf1)+Cadj×(VR-Vf1)+Ci×(VR-Vx(t2))

$\left(16\right)---\mathrm{Vx}\left(t2\right)=\mathrm{Vx}\left(t1\right)+\mathrm{\&Delta;V}(+)=[\mathrm{VR}+\mathrm{\&Delta;V}(-)]+\frac{(\mathrm{Vf}2-\mathrm{Vf}1)\&times;(\mathrm{Cx}-\mathrm{Cadj})}{2\mathrm{Ci}}$

Because the accurate Vx in position (t2) of integral voltage Vx still is lower than reference voltage VR, during operation, during TP2 ' operation afterwards among the TP3 ', carry out integration operation by 32 couples of integral voltage Vx of control circuit constantly.The operation narration of this moment can push away according to equation (15) and (16).

In sum, whether the activation of logical block 38a1 by judging drive signal En, drives capacitance measurement circuit 30 accordingly integral voltage Vx is dragged down a negative voltage difference DELTA V (-), or promote a forward voltage difference DELTA V (+).The numerical example of enumeration data D_cnt is as equaling the number of operations that 30 couples of integral voltage Vx of capacitance measurement circuit carry out the operation that drags down a negative voltage difference DELTA V (-).

When TP_IT3 finished between integration period, enumeration data D_cnt for example equaled numerical value Y, and Y is a natural number.In other words, between integration period among the TP_IT3, capacitance measurement circuit 30 is carried out Y time integral voltage Vx is dragged down the operation of a negative voltage difference DELTA V (-), and carries out X-Y the operation with an integral voltage Vx forward voltage difference DELTA V of lifting (+).The accurate Vx in position (tX) when like this, integral voltage Vx TP_IT3 between integration period finishes satisfies equation:

(17) Vx(tX)＝Vx(t0)+Y×ΔV(-)+(X-Y)×ΔV(+)

Assumed conditions:

(18) Vx(tX)＝Vx(t0)+ΔV _ERR

Equation (17) can be rewritten as:

$\left(19\right)---\mathrm{Vx}\left(t0\right)+{\mathrm{\&Delta;V}}_{\mathrm{ERR}}=\mathrm{Vx}\left(t0\right)+Y\&times;\frac{(\mathrm{Vf}2-\mathrm{Vf}1)\&times;(-\mathrm{Cc})}{\mathrm{Ci}}+X\&times;\frac{(\mathrm{Vf}2-\mathrm{Vf}1)\&times;(\mathrm{Cx}-\mathrm{Cadj})}{\mathrm{Ci}}$

$\&DoubleRightArrow;\mathrm{Cx}-\mathrm{Cadj}=\mathrm{Cc}\&times;\frac{Y}{X}+\frac{\mathrm{Ci}\&times;\mathrm{\&Delta;}{V}_{\mathrm{ERR}}}{X\&times;(\mathrm{Vf}2-\mathrm{Vf}1)}$

If satisfy condition:

(20) X×(Vf2-Vf1)＞＞Ci×ΔV _ERR

Equation (19) can be rewritten as:

$\left(21\right)---\mathrm{Cx}-\mathrm{Cadj}=\mathrm{Cc}\&times;\frac{Y}{X}$

Like this, the processor circuit 38 of present embodiment can obtain the variable quantity of testing capacitance Cx according to numerical value Y, X and known capacitance Cc computing.In the present embodiment, numerical value Y for example equals 8.

Please refer to Figure 11 A, it shows the process flow diagram according to the measured capacitance value method of second embodiment of the invention.At first as step (a '), control circuit 32 switches the voltage of at least one end of testing capacitance Cx and capacitance adjustable variable road Cadj in response to frequency signal CK_a1 ' and CK_a2 ', with integral voltage Vx be adjusted into the present position of integral voltage Vx accurate with difference voltage Δ V (+) sum, difference voltage Δ V (+) is relevant with the difference of the equivalent capacitance value of testing capacitance Cx and capacitance adjustable variable appearance Cadj.

Then as step (b '), processor circuit 38 judges whether to receive the control event of control signal CS4 activation, if not, repeated execution of steps (a '), if, execution in step (c ').Execution in step when receiving the incident of control signal CS4 activation (c '), counter circuit 38d increases progressively 1 with the numerical value of enumeration data D_cnt.Then as step (d '), the voltage that processor circuit 38 provides frequency signal to switch at least one end of known capacitance Cc, testing capacitance Cx and capacitance adjustable variable road Cadj in during operation is adjusted into integral voltage Vx accurate and difference voltage Δ V (-) sum in present position of integral voltage Vx.Difference voltage Δ V (-) is relevant with the capacitance of known capacitance Cc, testing capacitance Cx and capacitance adjustable variable road Cadj.

Then as step (e '), processor circuit 38 judges whether TP_IT3 stops between integration period, if not, repeated execution of steps (a '), if, execution in step (f ').Execution in step when TP_IT3 between integration period stops (f '), processor circuit 38 is according to the number of operations of the controlled circuit 34 of the numerical value Y of enumeration data D_cnt execution in step among the TP_IT3 (c ') between integration period, and obtains the capacitance variation amount of testing capacitance Cx according to the capacitance computing of number of operations Y, numerical value X and known capacitance Cc.

In an example, shown in Figure 11 B, execution in step (e1 ') when processor circuit in step (b ') 38 is judged the control event that receives control signal Cs4 activation, processor circuit 38 judges whether TP_IT3 stops between integration period, if not, execution in step (c '), if, execution in step (f ').Execution in step when processor circuit in step (b ') 38 is judged the control event that does not receive control signal CS4 activation (e2 '), processor circuit 38 judges whether TP_IT3 stops between integration period, if not, execution in step (a '), if, execution in step (f ').

In an example, shown in Figure 11 C, between step (c ') and (d '), also comprise step (e3 '), processor circuit 38 judges whether TP_IT3 stops between integration period, if not, execution in step (d '), if, execution in step (f ').

Similar to first embodiment, the measured capacitance value method of present embodiment also comprises step (g ') before in step (a '), and the position standard of integral voltage Vx is set at starting potential VR.

In the present embodiment, though only the example that has a circuit structure shown in Fig. 8 A and 8B with capacitance measurement circuit 30 explains, still, the capacitance measurement circuit 30 of present embodiment is not limited to have the circuit structure shown in Fig. 8 A and 8B.In another example, the capacitance measurement circuit 30 of present embodiment can be as shown in figure 12.Though the example of only receiving voltage Vf1 with the termination of testing capacitance Cx in Figure 12 explains, still, the end of testing capacitance Cx is not limited to receive voltage Vf1, and also can receive other any voltage between ceiling voltage VDD and ground voltage.

Similar to first embodiment, the capacitance measurement circuit of present embodiment also comes integral voltage is carried out integration operation with the difference on testing capacitance and capacitance adjustable variable road.Like this, the capacitance measurement circuit of present embodiment also have difference voltage Δ V (+) less, can be integrated in integrating capacitor in the integrated circuit, circuit cost is lower, the marginal higher and advantage that can measure changes in capacitance amount to be measured exactly of noise.

In addition, the capacitance measurement circuit of present embodiment is to come integral voltage is carried out integration by the trigonometric integral algorithm.Like this, compare with the capacitance measurement circuit of first embodiment, the capacitance measurement circuit of present embodiment also has the programmable numerical range of numerical value of N and reaches measured capacitance value resolution advantage of higher more greatly.

In above-mentioned first and second embodiment of the present invention, capacitance measurement circuit 10～40 also for example makes the capacitance of the capacitance of capacitance adjustable variable road Cadj near testing capacitance Cx by carrying out the capacitance setting operation.For instance, please refer to Figure 13, the coherent signal sequential chart when it illustrates capacitance measurement circuit according to the embodiment of the invention and carries out the capacitance setting operation.

Processor circuit is that the capacitance with capacitance adjustable variable road Cadj is set at minimum value, then according to testing capacitance Cx and capacitance adjustable variable road Cadj integral voltage Vx is carried out integration among the TP_ADJ (j) during capacitance is set, and j is a natural number.Processor circuit is the size of TP_ADJ (j) end back judgement integral voltage Vx and starting potential Vi during capacitance is set also.

For instance, when TP_ADJ (Z) finished during capacitance is set, processor circuit was judged integral voltage Vx greater than starting potential Vi, and z is a natural number.At this moment, the capacitance of expression capacitance adjustable variable road Cadj is less than the capacitance of testing capacitance Cx.Like this, processor circuit is adjusted the capacitance that setting signal Sadj promotes capacitance adjustable variable road Cadj.Repeat aforesaid operations, when processor detects integral voltage Vx less than the critical condition of starting potential Vi (when for example TP_ADJ (Z+1) finishes during magnitude of voltage is set), stop aforesaid operations.At this moment, the capacitance of capacitance adjustable variable road Cadj is near the capacitance of testing capacitance Cx.

During TP_ADJ (j) and voltage are set during capacitance is set among the TP_PS ', processor circuit also in order to the control signal CS5 of output disabled with the switch S c2 among the disabled integrating capacitor Ci, make the capacitance of integrating capacitor Ci equal capacitor C i1 but not equal capacitor C i1 and the Ci2 sum.Reach (5) as can be known according to equation (3), integrating capacitor Ci negative is about the size of difference voltage Δ V1 and Δ V2.Like this, the equivalent capacitance value that reduces integrating capacitor Ci by disabled switch S c2 can improve the difference voltage of execution integration operation among the TP_ADJ (j) during capacitance is set, and makes magnitude relationship between capacitance measurement circuit easier resolution integral voltage Vx and starting potential Vi.

Please refer to Figure 14, it shows the dependence diagram according to the capacitance establishing method of the embodiment of the invention.The capacitance establishing method for example be executed in above-mentioned first and second embodiment the measured capacitance value method step (a) and (a ') before, the capacitance establishing method of present embodiment for example comprises the following steps.At first as step (h), the equivalent capacitance value that processor circuit provides setting signal Sadj to set capacitance adjustable variable road Cadj, in an example, this equivalence capacitance for example is the position of minimum capacitance of capacitance adjustable variable road Cadj.Then as step (i), control circuit is in response to frequency signal CK_a1 " and CK_a2 " switch the voltage of at least one end of testing capacitance Cx and capacitance adjustable variable road Cadj, integral voltage Cx is adjusted into present integral voltage Vx and difference voltage Δ V (+) sum.

As step (j), during voltage is set, repeat L step (i) among the TP_ADJ (j) then, integral voltage Vx is adjusted into final voltage Vf (j).Then as step (k), processor circuit judges whether final voltage Vf (j) satisfies the critical condition less than starting potential Vi, if not, and execution in step (m), if, execution in step (l).

As step (m), processor circuit is adjusted the numerical value of setting signal Sadj, makes the capacitance of adjustable variable road Cadj increase minimum adjustable capacitance, and repeated execution of steps (i).As step (l), processor circuit is with the equivalent capacitance value of the numerical value decision capacitance adjustable variable road Cadj of present setting signal Sadj.In step (l) afterwards, the step (f) among the step among the execution graph 11A (g ') or Fig. 5.

Wherein also comprise step (n) in step (h) and (i), provide the control signal CS5 of disabled to close switch S c2 among the integrating capacitor Ci during processor circuit TP_ADJ (j) and voltage during capacitance is set are set among the TP_PS ', reduce the equivalent capacitance value of integrating capacitor Ci.

In sum, though the present invention discloses as above with preferred embodiment, it is not in order to limit the present invention.The ordinary technical staff in the technical field of the invention without departing from the spirit and scope of the present invention, should do various changes and modification.Therefore, protection scope of the present invention is as the criterion according to the content that claims limited.

The primary clustering symbol description

10,20,30,40: capacitance measurement circuit

12,14,22,24,32,34,42,44: control circuit

SW1, SW2, SW3, SW1 ', SW2 ', SW3 ', SW1 ", SW2 ", SW3 ": on-off circuit

Sa1～Sa4, Sb1, Sb2, Sc1, Sc2, Sa31, Sa32, Sa41, Sa42, Sb11, Sb12, Sb21, Sb22: switch

Cx: testing capacitance Cadj: capacitance adjustable variable road

Cc: known capacitance 16,26,36,46: integrator circuit

Ci: integrating capacitor Ci1, Ci2: electric capacity

OP1, OP2, OP3, OP4: operational amplifier

18,28,38,48: processor circuit

18a, 38a: logic circuit

18a1,18a2,38a1,38a2: logical block

And_1～and_4, and_1 '～and_4 ': logic lock

18b, 38b: comparator circuit

18c, 38c: pierce circuit

18d, 38d: counter circuit

18e, 38e: latch unit circuit

18f, 38f: computing circuit

(a)～(f), (a ')～(f '), (g)～(l): operation steps.

Claims (10)

1. capacitance measurement circuit comprises:

Integrator circuit has the first input end and first output terminal, has integral voltage on described first output terminal, and described integrator circuit is set at the start bit standard in order to the activation position standard in response to first control signal with described integral voltage;

First control circuit, comprise second output terminal, testing capacitance and capacitance adjustable variable road, described second output terminal is electrically connected to described first input end, equivalent capacitance value is decided in response to the signal numerical value of setting signal in described capacitance adjustable variable road, described equivalent capacitance value is near the capacitance of described testing capacitance, described first control circuit is in order to the voltage level at least one end at least one end that switches described testing capacitance in response to the first class frequency signal and described capacitance adjustable variable road, adjust operation to carry out first, with described integral voltage be adjusted into the present position of described integral voltage accurate with the first difference voltage sum, the capacitance of described first difference voltage and described testing capacitance is relevant with the difference of described equivalent capacitance value;

Second control circuit, comprise the 3rd output terminal and known capacitance, described the 3rd output terminal is electrically connected to described first input end, described second control circuit is in order to the voltage level at least one end that switches described known capacitance in response to the second class frequency signal, adjust operation to carry out second, described integrator voltage is adjusted into the accurate and second difference voltage sum in present position of described integral voltage; And

Processor circuit, in order to provide described first group and the described second class frequency signal drive respectively described first and described second control circuit carry out respectively and described first and described second adjust operation, calculate during first integral, described second control circuit is carried out described second and is adjusted the number of operations of operation, and obtains the capacitance of described testing capacitance according to the capacitance computing of described number of operations and described known capacitance.

2. capacitance measurement circuit according to claim 1, wherein, described first control circuit also comprises:

First on-off circuit, in order to activation position standard in response to the first positive frequencies signal in the described first class frequency signal, first end of first voltage to described testing capacitance is provided, and, make first end of described testing capacitance be coupled to described integrator circuit in response to the activation position standard of the first anti-phase frequency signal in the described first class frequency signal;

Wherein, described first forward and described first anti-phase frequency signal inversion signal each other.

3. capacitance measurement circuit according to claim 2, wherein, described first control circuit also comprises:

The second switch circuit, in order to activation position standard in response to the described first positive frequencies signal, first end of second voltage to described capacitance adjustable variable road is provided, and, make first end on described capacitance adjustable variable road be coupled to described integrator circuit in response to the activation position standard of the described first anti-phase frequency signal;

Wherein, second termination on second end of described testing capacitance and described capacitance adjustable variable road is received tertiary voltage.

4. capacitance measurement circuit according to claim 2, wherein, described first control circuit also comprises:

The second switch circuit, in order to activation position standard in response to the described first positive frequencies signal, make first end and second end on described capacitance adjustable variable road receive second voltage and described first voltage respectively, and, make first end on described capacitance adjustable variable road and second end be coupled to described integrator circuit respectively and receive described second voltage in response to the activation position standard of the described first anti-phase frequency signal.

5. capacitance measurement circuit according to claim 1, wherein, described integrator circuit comprises:

Operational amplifier, positive input terminal and negative input end receive the 4th voltage respectively and are coupled to described first and described second control circuit, and described output terminal is coupled to described processor circuit;

First integral electric capacity, the two ends of described integrating capacitor are coupled to the negative input end and the described output terminal of described operational amplifier respectively; And

The 4th on-off circuit, first end and second end are coupled to the negative input end and the described output terminal of described operational amplifier respectively, described the 4th on-off circuit is in order to the accurate conducting in activation position in response to first control signal, connect the negative input end and the described output terminal of described operational amplifier with short circuit, and set the negative input end of described operational amplifier and the voltage of described output terminal is described the 4th voltage.

6. capacitance measurement circuit according to claim 5, wherein, described integrator circuit also comprises second integral electric capacity and the 5th on-off circuit, described second integral electric capacity and described the 5th on-off circuit are connected in series negative input end and the described output terminal in described operational amplifier, described the 5th on-off circuit is in order to the conducting in response to the activation position standard of second control signal, make described first and described second integral electric capacity for being connected in parallel.

7. capacitance measurement circuit according to claim 1, described processor circuit comprises:

Comparator circuit is in order to the accurate height in the position of more described integral voltage and the 4th voltage, to export the 3rd control signal;

First logical circuit judges whether described the 3rd control signal satisfies trigger condition in during described first integral, and when described the 3rd control signal satisfies trigger condition, triggers control event;

Second logical circuit drives described first control circuit in order to produce the described first class frequency signal in during described first integral, and in order to produce the described second class frequency signal in response to described control event, to drive described second control circuit;

Counter circuit in during described first integral, increases progressively 1 in response to described control event with count value, during described first integral after, described counter circuit is exported as described number of operations with described count value; And

Latch circuit, the activation position standard in order in response to the breech lock control signal writes down described number of operations.

8. measured capacitance value method comprises:

(a) in response to the first class frequency signal, the voltage of at least one end of switching testing capacitance and at least one end on capacitance adjustable variable road, adjust operation to carry out first, with the integral voltage on the end of integrating capacitor be adjusted into the present position of described integral voltage accurate with the first difference voltage sum, the difference of the capacitance of described first difference voltage and described testing capacitance and the equivalent capacitance value of described capacitance adjustable variable appearance is relevant;

(b) repeat N step (a), so that described integral voltage is adjusted into second standard from first standard, N is a natural number;

(c) in response to the second class frequency signal, switch the voltage of at least one end of known capacitance, adjust operation to carry out second, described integral voltage is adjusted into the present position standard and the second difference voltage sum of described integral voltage;

(d) judge whether to receive first control event, if not, repeated execution of steps (c), if, execution in step (e);

(e) between the decision integration period, and the frequency period that calculates the described second class frequency signal that comprises between described integration period counts M, and calculates the capacitance of described testing capacitance according to the capacitance of numerical value M, N and described known capacitance.

9. measured capacitance value method comprises:

(a) in response to the first class frequency signal, switch the voltage of at least one end of known capacitance, adjust operation to carry out first, with the integral voltage on the end of integrating capacitor be adjusted into the present position of described integral voltage accurate with first difference voltage and;

(b) repeat N step (a), so that described integral voltage is adjusted into second standard from first standard, N is a natural number;

(c) in response to the second class frequency signal, the voltage of at least one end of switching testing capacitance and at least one end on capacitance adjustable variable road, adjust operation to carry out second, with described integral voltage be adjusted into the present position of described integral voltage accurate with the second difference voltage sum, the difference of the capacitance of described second difference voltage and described testing capacitance and the equivalent capacitance value of described capacitance adjustable variable appearance is relevant;

(d) judge whether to receive first control event, if not, repeated execution of steps

(c), if, execution in step (e);

(e) between the decision integration period, and the frequency period of the described second class frequency signal that comprises in calculating between described integration period counts M, and calculates the capacitance of described testing capacitance according to the capacitance of numerical value M, N and described known capacitance.

10. a measured capacitance value method is measured in order to the capacitance to testing capacitance between integration period, and described measured capacitance value method comprises:

(a) in response to the first class frequency signal, the voltage of at least one end of switching testing capacitance and at least one end on capacitance adjustable variable road, adjust operation to carry out first, with be stored in integral voltage on the end of integrating capacitor be adjusted into the present position of described integral voltage accurate with the first difference voltage sum, the difference of the capacitance of described first difference voltage and described testing capacitance and the equivalent capacitance value of described capacitance adjustable variable appearance is relevant;

(b) judge whether to receive first control event;

(c) when receiving described first control event, count value is increased progressively 1;

(d) switch the voltage of at least one end of known capacitance and in an operating period, adjust operation to carry out second, with described integral voltage be adjusted into the present position of described integral voltage accurate with the second difference voltage sum, described second difference voltage is relevant with the capacitance of described known capacitance;

(e) judge between described integration period whether stop; And

(f) when stopping between described integration period, in obtaining between described integration period according to described count value, described second control circuit is carried out described second and is adjusted the number of operations of operation, and obtains the capacitance of described testing capacitance according to the capacitance computing of described number of operations and described known capacitance.

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