CN101666830B - Capacitance value measuring circuit and electronic device using it - Google Patents

Abstract

The invention relates to a capacitance value measuring circuit, comprising: the device comprises a capacitive voltage division circuit, an analog-to-digital converter (ADC) and a processing module. The capacitive voltage-dividing circuit includes: a switch circuit, a known capacitor and a capacitor to be measured. The switch circuit is controlled by the first and second clock signals. The conducting state of the switch circuit enables the voltage variation of the first end of the known capacitor to be coupled to the first end of the capacitor to be measured. The analog-digital converter converts the voltage of the first end of the capacitor to be measured into a digital signal. The processing module detects the capacitance value and the variable quantity of the capacitor to be detected according to the digital signal of the analog-digital converter and the parameters of the analog-digital converter. The invention also relates to an electronic device applying the capacitance value measuring circuit, which is used for measuring the capacitance value of the capacitor to be measured.

Description

Capacitance measurement circuit and use its electronic installation

Technical field

The present invention relates to a kind of capacitance measurement circuit and the electronic installation of using it, it is used for measuring the capacitance of testing capacitance.

Background technology

Traditionally, realize that mainly with mechanical switch the user controls the interface greatly.Because the user need directly touch conventional mechanical switch, conventional mechanical switch just can respond user's steering order and operate, and traditional mechanical device easily is damaged in user's operating process.At present, developed touch control type switch.Touch control type switch is such as being capacitance-type switch etc.

In order to promote the convenience in the use, developed contact panel (touch panel) or shown contact panel (having simultaneously the function that shows with touch-control).Contact panel or show that contact panel can accept user's input, the operation such as click.Contact panel or demonstration contact panel can be applicable in the various electronic installations, for example in the mobile phone.Like this, can make the user directly at contact panel or show that contact panel clicks picture and operates, the operator scheme of more convenient and hommization is provided thus.Contact panel or to show that contact panel has multiple, capacitance type touch-control panel or show that contact panel is wherein a kind of.

When user's operating capacitance touch panel, when condenser type shows contact panel or capacitance-type switch, the capacitance of the testing capacitance that it is inner can change with user's operation.Thus, can detect user's operation.Yet, how to design the capacitance measurement circuit that can effectively detect the capacitance variation of testing capacitance, show that to promote capacitance type touch-control panel, condenser type the performance of contact panel or capacitance-type switch is one of direction of constantly endeavouring of this area.

Summary of the invention

The present invention relates to a kind of capacitance measurement circuit, compare with traditional capacitance value metering circuit, this capacitance measurement circuit can be measured capacitance and its capacitance variation amount of testing capacitance more accurately.

The present invention relates to a kind of electronic installation, the Touch Screen that it is inner and sensor can be shared same analog-digital converter (ADC), with circuit area and the cost that reduces this electronic installation.

The invention provides a kind of capacitance measurement circuit, comprise: the capacitive partial pressure circuit, it comprises: on-off circuit, the first electric capacity and the second electric capacity, on-off circuit is coupled to first and second electric capacity, on-off circuit is controlled by the first clock signal and second clock signal, the second clock signal is the inversion signal of the first clock signal, and the conducting state of on-off circuit is so that the voltage variety of the first end of the first electric capacity is coupled to the first end of the second electric capacity; Analog-digital converter is coupled to the capacitive partial pressure circuit, and analog-digital converter becomes the first digital signal with the voltage transitions of the first end of the second electric capacity; And processing module, being coupled to analog-digital converter, processing module is according to the first digital signal of analog-digital converter and the parameter of analog-digital converter, with capacitance and the variable quantity thereof that detects the second electric capacity.

In capacitance measurement circuit of the present invention, in one embodiment, the on-off circuit of this capacitive partial pressure circuit comprises: the first switch, and its first end is coupled to the first voltage source, its the second end is coupled to the first end of this second electric capacity, and the conducting of this first switch is controlled by the first clock signal; Second switch, its first end is coupled to the first voltage source, and its second end is coupled to the first end of this first electric capacity, and the conducting of this second switch is controlled by the first clock signal; And the 3rd switch, its first end is coupled to the second voltage source, and its second end is coupled to the first end of this first electric capacity, and the conducting of the 3rd switch is controlled by this second clock signal; Wherein, the second end of this first electric capacity is coupled to this first end of the second electric capacity, and the second end of this second electric capacity is coupled to the tertiary voltage source.

Capacitance measurement circuit of the present invention, in one embodiment, the parameter of this analog-digital converter comprises resolution and the changing voltage interval of this analog-digital converter; And this processing module is further according to the magnitude of voltage of this first voltage source, magnitude of voltage and the capacitance of this first electric capacity, the resolution of this analog-digital converter, this changing voltage interval of this analog-digital converter and first digital signal of this analog-digital converter in this second voltage source, with capacitance and the variable quantity thereof that detects this second electric capacity.

Capacitance measurement circuit of the present invention, in one embodiment, further comprise bias circuit, be coupled to this capacitive partial pressure circuit and this analog-digital converter, this bias circuit is used for applying being biased into first node, so that the voltage of this first node is relevant with the voltage of the first end of this bias voltage and this second electric capacity.

Capacitance measurement circuit of the present invention, in one embodiment, this analog-digital converter comprises: switch-sampling-condenser network, operational amplifier, comparer, latch (bolt lock device, latch), phase inverter, counter and switched-capacitor circuit, wherein, switch-sampling-condenser network has first input end and the output terminal of the first end of this second electric capacity that is coupled to this capacitive partial pressure circuit, this switch-sampling-condenser network is controlled by this first clock signal and this second clock signal, with the voltage of this first end of this second electric capacity of this capacitive partial pressure circuit of taking a sample; Operational amplifier has first input end, the second input end, the first output terminal and second output terminal of the output terminal that is coupled to this switch-sampling capacitor circuit; Comparer have the first output terminal that is coupled to this operational amplifier first input end, be coupled to the second input end of the second output terminal of this operational amplifier and the output terminal of exporting the second digital signal; Latch receives the second digital signal that comparer is exported, and under the triggering of this first clock signal, this latch is output into three digital signal with the second digital signal; The phase inverter that three digital signal is anti-phase; Counter is counted this three digital signal, to produce the first digital signal; And the switched-capacitor circuit, the second input end that it is coupled to this operational amplifier is controlled by the inversion signal of the first clock signal, second clock signal, three digital signal and three digital signal.

The present invention also provides a kind of electronic installation, comprising: testing capacitance is used for exporting voltage to be measured; Sensor is used for the output sensing signal; Multiplexer is coupled to testing capacitance and sensor, to export one of voltage to be measured and sensing signal; And analog-digital converter, be coupled to multiplexer, be used for converting voltage to be measured or sensing signal to digital output signal, digital output signal represents capacitance and the variable quantity thereof of testing capacitance, perhaps represents the sensing result of this sensor.

Electronic installation of the present invention further comprises Touch Screen in one embodiment, and wherein, this testing capacitance is positioned at Touch Screen.

For foregoing of the present invention can be become apparent more, hereinafter enumerate especially embodiment, and by reference to the accompanying drawings, be described in detail below:

Description of drawings

Fig. 1 shows the circuit diagram according to the capacitance measurement circuit of first embodiment of the invention.

Fig. 2 shows the waveform correlation figure of Fig. 1.

Fig. 3 shows the circuit diagram according to the capacitance measurement circuit of second embodiment of the invention.

Fig. 4 shows the waveform correlation figure of Fig. 3.

Fig. 5 shows the high-level schematic functional block diagram according to the electronic installation of third embodiment of the invention.

Embodiment

The capacitance that can be used for measuring testing capacitance according to the capacitance measurement circuit of the embodiment of the invention, and convert capacitance to digital output signal.Whether the capacitance that like this, can detect testing capacitance changes.In addition, according to the electronic installation of the embodiment of the invention, the Touch Screen that it is inner and sensor can be shared same ADC, with circuit area and the cost that reduces this electronic installation.

[the first embodiment]

Fig. 1 shows the circuit diagram according to the capacitance measurement circuit of first embodiment of the invention.Fig. 2 shows the waveform correlation figure of Fig. 1.

As shown in Figure 1, this capacitance measurement circuit comprises: analog-digital converter 110, capacitive partial pressure circuit 120 and processing module 130.This analog-digital converter 110 for example is the trigonometric integral analog-digital converter (sigma-deltaADC) with sampling-maintenance (S/H) function.Capacitive partial pressure circuit 120 comprises: switch 121～123, capacitor C s and Cx.In the present embodiment, V1, V2 and Vc are voltage source, and hypothesis V1＜V2, and clock signal ph1 and ph2 are anti-phase each other.

One end of switch 121 is coupled to voltage source V 2, and its other end is coupled to node nx.The voltage of node nx is Vx.The conducting state of switch 121 is controlled by clock signal ph1.Such as, when clock signal ph1 was noble potential, switch 121 was conducting; Vice versa.When switch 121 conducting, node voltage Vx equals V2.

One end of switch 122 is coupled to voltage source V 2, and its other end is coupled to node ns.The voltage of node ns is Vs.The conducting state of switch 122 is controlled by clock signal ph1.Such as, when clock signal ph1 was noble potential, switch 122 was conducting; Vice versa.When switch 122 conducting, node voltage Vs equals V2.

One end of switch 123 is coupled to voltage source V 1, and its other end is coupled to node ns.The conducting state of switch 123 is controlled by clock signal ph2.Such as, when clock signal ph2 was noble potential, switch 123 was conducting; Vice versa.When switch 123 conducting, node voltage Vs equals V1.

Capacitor C s is coupled between node ns and the nx.The capacitance of capacitor C s then is known.Capacitor C x is coupled between node nx and the voltage source V c.The capacitance of capacitor C x is unknown, and this capacitance measurement circuit can be used for measuring the capacitance of capacitor C x.

Now please be simultaneously with reference to Fig. 1 and Fig. 2, with the operation of the capacitance measurement circuit of understanding the first embodiment.

When clock signal ph1 is noble potential (namely clock signal ph2 is electronegative potential), switch 121 and 122 is conducting, so that node voltage Vx and Vs are equal to V2.

When clock signal ph1 is electronegative potential by the noble potential transition (namely clock signal ph2 is noble potential by the electronegative potential transition), switch 123 meeting conductings are so that node voltage Vs equals V1.Like this, with so that the change in voltage of the end of capacitor C s (also being node voltage Vs) is (V1-V2).This voltage variety (V1-V2) will be coupled to contact nx by capacitor C s, so that node voltage Vx changes.The voltage variety of node voltage Vx is shown in following formula (1):

$(V1-V2)\·\frac{\mathrm{Cs}}{(\mathrm{Cs}+\mathrm{Cx})}---\left(1\right)$

In a flash, node voltage Vx is V2 before transition occurs clock signal ph1.In a flash, node voltage Vx is shown in following formula (2) after transition occurs clock signal ph1:

$\mathrm{Vx}=V2+(V1-V2)\·\frac{\mathrm{Cs}}{(\mathrm{Cs}+\mathrm{Cx})}---\left(2\right)$

After the sampling and maintenance of node voltage Vx through ADC120, convert again digital output value BOUT[N:1 to].Digital output value BOUT[N:1] decimal value be expressed as DOUT.

According to the changing voltage of the capacitance of DOUT, capacitor C s, V1, V2, ADC120 interval (Full Scale) and resolution, processing module 130 can calculate capacitance and the variable quantity thereof of capacitor C x.

For example, if the changing voltage of ADC120 interval is V2 to V1, its resolution (resolution) is n position (n is positive integer), and then the relation between Cx, V1, V2, Cs, DOUT and n is shown in formula (3):

To can get Cx shown in formula (4) after formula (3) simplification:

Like this, can try to achieve the capacitance of capacitor C x.

The capacitance measurement circuit of the first embodiment can be applicable to capacitance-type switch, capacitance type touch-control panel, condenser type demonstration contact panel etc.When user's operating capacitance switch, the capacitance of the testing capacitance Cx that it is inner can change along with user's operation; Measure capacitance and its variable quantity of capacitor C x by capacitance measurement circuit, can learn whether the user presses capacitance-type switch.In addition, when user's operating capacitance touch panel or condenser type demonstration contact panel, the capacitance of the testing capacitance Cx that it is inner can change along with pressing of user; Measure capacitance and its variable quantity of capacitor C x by capacitance measurement circuit, can learn user's pressing position.

[the second embodiment]

Fig. 3 shows the circuit diagram according to the capacitance measurement circuit of second embodiment of the invention.Fig. 4 shows the waveform correlation figure of Fig. 3.

As shown in Figure 1, this capacitance measurement circuit comprises: analog-digital converter (ADC) 305, capacitive partial pressure circuit 380 and bias circuit 390.This analog-digital converter (ADC) 305 for example is the trigonometric integral analog-digital converter (sigma-delta ADC) with sampling-maintenance (S/H) function.

ADC305 comprises: operational amplifier (OP) 310, comparer (CMP) 320, latch 330, phase inverter 340, counter 350, switch 361～370, electric capacity 371～375.

Operational amplifier 310 has: positive input terminal inp is coupled to switch 368 and electric capacity 374; Negative input end inn is coupled to switch 370 and electric capacity 373; Positive output end outp is coupled to positive input terminal and the electric capacity 373 of comparer 320; And negative output terminal outn, be coupled to negative input end and the electric capacity 374 of comparer 320.

Comparer 320 has: positive input terminal is coupled to the positive output end outp of operational amplifier 310; Negative input end is coupled to the negative output terminal outn of operational amplifier 310; And output terminal, be coupled to latch 330.The output signal C_OUT of comparer 320 inputs to latch 330.

Latch 330 receives the output signal C_OUT of comparer 320, with output digit signals D1.Latch 330 is controlled by clock signal ph1.

Phase inverter 340 is inverted into another digital signal D1B with digital signal D1.Namely, digital signal D1 and D1B are anti-phase each other.

350 pairs of digital signal D1 countings of counter are to produce count results BOUT[N:1].

One end of switch 361 is coupled to voltage source (V1+V2)/2, and its other end is coupled to electric capacity 371 and switch 362.The conducting state of switch 361 is controlled by clock signal ph1.

One end of switch 362 is coupled to voltage source V 2, and its other end is coupled to electric capacity 371 and switch 361.The conducting state of switch 362 is controlled by clock signal ph2.

One end of switch 363 is coupled to voltage source (V1+V2)/2, and its other end is coupled to electric capacity 372 and switch 366.The conducting state of switch 363 is controlled by clock signal ph1.

One end of switch 364 is coupled to voltage source V 1, and its other end is coupled to switch 365 and 366.The conducting state of switch 364 is controlled by digital signal D1B.

One end of switch 365 is coupled to voltage source V 2, and its other end is coupled to switch 364 and 366.The conducting state of switch 365 is controlled by digital signal D1.

One end of switch 366 is coupled to electric capacity 372 and switch 363, and its other end is coupled to switch 364 and 365.The conducting state of switch 366 is controlled by clock signal ph2.Switch 364～366 is used for voltage source V 1 is sent to electric capacity 372 with one of V2.

One end of switch 367 is coupled to voltage source V 3, and its other end is coupled to switch 368, electric capacity 371 and 372.The conducting state of switch 367 is controlled by clock signal ph1.

One end of switch 368 is coupled to switch 367, electric capacity 371 and 372, and its other end is coupled to positive input terminal inp and the electric capacity 374 of operational amplifier 310.The conducting state of switch 368 is controlled by clock signal ph2.In addition, switch 361～368 and electric capacity 371～372 also can be described as the switched-capacitor circuit, and it is coupled to the input end inp of operational amplifier 310.This switched-capacitor circuit is controlled by clock signal ph1, clock signal ph2, digital signal D1 and D1B.

One end of switch 369 is coupled to voltage source V 3, and its other end is coupled to node nr.The conducting state of switch 369 is controlled by clock signal ph1.

One end of switch 370 is coupled to node nr, and its other end is coupled to negative input end inn and the electric capacity 373 of operational amplifier 310.The conducting state of switch 370 is controlled by clock signal ph2.

One end of electric capacity 371 is coupled to switch 361 and 362, and its other end is coupled to switch 367,368 and electric capacity 372.

One end of electric capacity 372 is coupled to switch 363 and 366, and its other end is coupled to switch 367,368 and electric capacity 371.

Electric capacity 373 is coupled between the negative input end inn and positive output end outp of operational amplifier 310, with as feedback loop.

Electric capacity 374 is coupled between the positive input terminal inp and negative output terminal outn of operational amplifier 310, with as feedback loop.

One end of electric capacity 375 is coupled to node nx, and its other end is coupled to switch 369,370.

Electric capacity 371,372 and 375 capacitance are C1; And the capacitance of electric capacity 373 and 374 is C2.

In addition, electric capacity 375 also can be described as switch-sampling-condenser network with switch 369～370, and it has: input end is coupled to an end nx of the Cs electric capacity of capacitive partial pressure circuit 380; And output terminal, be coupled to the input end inn of operational amplifier.This switch-sampling-condenser network is controlled by clock signal ph1 and ph2, with the end-point voltage Vx of sampling capacitor Cx.

Capacitive partial pressure circuit 380 comprises: switch 381～383 and capacitor C s and Cx.Capacitive partial pressure circuit 380 is same or similar in the capacitive partial pressure circuit 120 of the first embodiment, thereby omits in this article its details.

Bias circuit 390 is for generation of charge variation amount (V2-V1) C1, so that this charge variation amount is coupled on the node nr.Namely, after complete time clock period, capacitive partial pressure circuit 380 and bias circuit 390 can be coupled to node nr with the charge variation amount of (Vx-V1) C1.Bias circuit 390 comprises: switch 391～392, and electric capacity 393.The capacitance of electric capacity 393 is C1.

One end of switch 391 is coupled to voltage source V 1, and its other end is coupled to electric capacity 393.The conducting state of switch 391 is controlled by clock signal ph1.

One end of switch 392 is coupled to voltage source V 2, and its other end is coupled to electric capacity 393.The conducting state of switch 392 is controlled by clock signal ph2.

One end of electric capacity 393 is coupled to switch 391 and 392, and its other end is coupled to node voltage Vr.

Now please be simultaneously with reference to Fig. 3 and Fig. 4, with the operation of the capacitance measurement circuit of understanding the present embodiment.

In the present embodiment, the switching of switch can cause voltage Vx to change.Voltage Vx inputs to ADC305 to obtain digital value BOUT[N:1].Learn thus the capacitance of testing capacitance Cx.

To illustrate now and how learn the magnitude of voltage Vx that inputs to ADC305.

Before and after clock signal ph1 transition (before and after the namely clock signal ph2 transition), the electric charge of node nx should equate.Therefore, the electric charge of node nx satisfies formula (5):

(V2-V3)C1+(V2-V2)Cs+(V2-Vc)Cx＝(Vx(s)-V3)C1+(Vx(s)-V1)Cs+(Vx(s)-Vc)Cx (5)

In formula (5), equation left side representative be before the clock signal ph1 transition at the electric charge of node nx, and the representative of equation the right is at the electric charge of node nx after the clock signal ph1 transition.Wherein, the voltage Vx of Vx (s) representative when clock signal ph2 is activation.Also namely, when clock signal ph2 was activation, in the present embodiment, ADC305 can take a sample to voltage Vx-keep, to obtain voltage Vx (s).Vx (s) is represented such as formula (6):

$\mathrm{Vx}\left(s\right)=\frac{V2(\mathrm{Cx}+C1)+\mathrm{<figure-callout\; id="1"\; label="V"\; filenames="H2008102139738E00011.png,H2008102139738E00021.png"\; state="\{\{state\}\}">V</figure-callout>}1\mathrm{Cs}}{\mathrm{Cx}+\mathrm{Cs}+C1}---\left(6\right)$

When the output signal C_OUT of comparer 320 was 0, digital signal D1 was disabled (electronegative potential), and digital signal D1B is activation (noble potential).When the output signal C_OUT of comparer 320 was 0, before and after clock signal ph1 transition (also being before and after the clock signal ph2 transition), the electric charge of the input end inn of operational amplifier 310 should equate.Thereby the electric charge of input end inn can be expressed as formula (7):

[V3-voutp((i-0.5))]C2+(V3-V1)C1+(V3-V2)C1

＝[V3-voutp(i)]C2+(V3-V2)C1+[V3-Vx(s)]C1 (7)

Wherein, voutp (i-0.5) and voutp (i) represent respectively the node voltage voutp at (i-0.5) individual clock and i clock.

Similarly, when the output signal C_OUT of comparer 320 was 0, before and after clock signal ph1 transition (also being before and after the clock signal ph2 transition), the electric charge of the input end inp of operational amplifier 310 should equate.Therefore the electric charge of input end inp can be expressed as formula (8):

$[V3-\mathrm{voutn}\left((i-0.5)\right)]\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="H2008102139738E00021.png"\; state="\{\{state\}\}">C</figure-callout>}2+[V3-\frac{(\mathrm{<figure-callout\; id="1"\; label="V"\; filenames="H2008102139738E00011.png,H2008102139738E00021.png"\; state="\{\{state\}\}">V</figure-callout>}1+V2)}{2}]\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="H2008102139738E00011.png,H2008102139738E00021.png"\; state="\{\{state\}\}">C</figure-callout>}1+[V3-\frac{(\mathrm{<figure-callout\; id="1"\; label="V"\; filenames="H2008102139738E00011.png,H2008102139738E00021.png"\; state="\{\{state\}\}">V</figure-callout>}1+V2)}{2}]\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="H2008102139738E00011.png,H2008102139738E00021.png"\; state="\{\{state\}\}">C</figure-callout>}1$

$\text{=}[V3-\mathrm{voutn}\left(i\right)]\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="H2008102139738E00021.png"\; state="\{\{state\}\}">C</figure-callout>}2+(V3-V2)\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="H2008102139738E00011.png,H2008102139738E00021.png"\; state="\{\{state\}\}">C</figure-callout>}1+(V3-V1)C1---\left(8\right)$

Wherein, voutn (i-0.5) and voutn (i) represent respectively the node voltage voutn at (i-0.5) individual clock and i clock.

Obtain formula (9) after (7) and (8) two formulas are subtracted each other:

$\{[\mathrm{voutp}\left(i\right)-\mathrm{voutn}\left(i\right)]-[\mathrm{voutp}\left((i-0.5)\right)-\mathrm{voutn}\left((i-0.5)\right)]\}=\frac{(V1-\mathrm{Vx}\left(s\right))C1}{C2}---\left(9\right)$

Because the differential output voltage vout of operational amplifier 310 is the difference of positive output voltage voutp and negative output voltage voutn, formula (9) can be rewritten into formula (10):

$\mathrm{\&Delta;vout}(+)=[\mathrm{vout}\left(i\right)-\mathrm{vout}\left((i-0.5)\right)]=\frac{(V1-\mathrm{Vx}\left(s\right))C1}{C2}---\left(10\right)$

Wherein, the voltage variety of the output voltage vout of the operational amplifier 310 of Δ vout (+) representative when D1=0.By formula (10) as can be known, Δ vout (+) is on the occasion of (because V1〉Vx (s)).Also namely, when D1=0, output voltage vout can uprise.

The voltage variety Δ vout (-) of the output voltage vout of the operational amplifier 310 in the time of in like manner, can pushing away proper D1=1 is shown in formula (11):

$\mathrm{\&Delta;vout}(-)=\frac{(V2-\mathrm{Vx}\left(s\right))C1}{C2}---\left(11\right)$

By formula (11) as can be known, Δ vout (-) is negative value (because V2＜Vx (s)).Also namely, when D1=1, output voltage vout can step-down.

Within k the clock period (k is positive integer), be that m and D1 are that 0 clock periodicity is n (m+n=k if digital signal D1 is 1 clock periodicity, m and n are positive integer), then the differential output voltage vout of operational amplifier 310 can be expressed as formula (12):

vout(k)＝n·Δvout(+)+mΔvout(-)+vout(0) (12)

The differential output voltage vout (k) of operational amplifier 310 also can be expressed as primary voltage vout (0) and add difference voltage verr at this moment, shown in formula (13):

vout(k)＝vout(0)+verr (13)

With formula (10) and (11) substitution formula (12), solution formula (12) and (13) can get:

$\mathrm{Vx}\left(s\right)=\frac{\mathrm{<figure-callout\; id="1"\; label="nV"\; filenames="H2008102139738E00011.png,H2008102139738E00021.png"\; state="\{\{state\}\}">nV</figure-callout>}1+\mathrm{mV}2}{n+m}+\frac{\mathrm{verrC}2}{(m+n)C1}---\left(14\right)$

If $\frac{(m+n)C1}{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="H2008102139738E00021.png"\; state="\{\{state\}\}">C</figure-callout>}2}>>\mathrm{verr},$ Then Vx (s) can be similar to

With formula (6) substitution formula (15), the relational expression that can get testing capacitance Cx, known capacitance Cs, n, m and C1 is as follows:

$\mathrm{Cx}=\frac{m}{n}\mathrm{Cs}-C1---\left(16\right)$

Like this, the capacitance measurement circuit of the present embodiment can be according to numerical value m, n and known capacitance Cs, C1, and measures testing capacitance Cx and variable quantity thereof.

In Fig. 4, Tclk represents clock signal period, and (i-0.5) Tclk represents respectively (i-0.5) individual clock period and (i) individual clock period with (i) Tclk.When clock signal ph2 is activation, can take a sample to voltage Vx.This sampling result can exert an influence to the output voltage vout of operational amplifier 310.When clock signal ph2 was activation, voltage Vx can become greatly, and charge variation amount (Vx-V2) C1 is coupled to node nr, and bias circuit 390 also is coupled to charge variation amount (V2-V1) C1 on the node nr simultaneously.Namely, the charge variation amount that is coupled after complete time clock period of node nr is (Vx-V1) C1.Because V1〉Vx, so the nod charge variable quantity of node nr is negative value, voltage Vr can diminish.Thereby when clock signal ph2 was activation, output voltage vout had positive integrating effect (also namely raising) to keep the charge conservation of node nr, shown in the sequential point 410 and 420 of Fig. 4.410 representatives of sequential point are taken a sample to voltage Vx, and sequential point 420 then represents output voltage vout and is raised (its voltage variety is Δ vout (+)).

When the output voltage vout of operational amplifier 310 is higher than critical value (0V), with so that the output signal C_OUT of comparer 320 becomes 1, shown in sequential point 430.Because the output signal C_OUT of comparer 320 becomes 1, so the output signal D1 of latch also can become 1, shown in sequential point 440.Because output signal D1 is 1 (output signal D1B is 0), as described above, output voltage vout can reduce (its voltage variety is Δ vout (-)), and can be less than 0, shown in sequential point 450.

Owing to putting 450 o'clock in sequential, output voltage vout can be less than 0, so, subsequently, the output signal C_OUT of comparer 320 can transition be 0 and digital signal D1 also transition be 0 so that output voltage vout is again by positive integration.Mode according to this can learn that digital signal D1 is that 1 clock periodicity and digital signal D1 are 0 clock periodicity, thereby and releases the capacitance of capacitor C x.

The capacitance measurement circuit of the second embodiment can be applicable to capacitance-type switch, capacitance type touch-control panel, condenser type demonstration contact panel etc.When user's operating capacitance switch, the capacitance of the testing capacitance Cx that it is inner can change along with user's operation; Measure the capacitance variation of capacitor C x by capacitance measurement circuit, can learn whether the user presses capacitance-type switch.In addition, when user's operating capacitance touch panel or condenser type demonstration contact panel, the capacitance of the testing capacitance Cx that it is inner can change along with pressing of user; Measure the capacitance variation of capacitor C x by capacitance measurement circuit, can learn user's pressing position.

In addition, in first and second embodiment of the present invention, because trigonometric integral ADC has the function of sampling-maintenance, thereby, in the capacitance measurement circuit of first and second embodiment of the present invention, do not need sample and hold circuit.Yet the present invention is not limited thereto.If the used ADC of capacitance measurement circuit does not have the function of sampling-maintenance, then in capacitance measurement circuit, need sample and hold circuit.This sample and hold circuit is to voltage Vx (or voltage V1-Vx) sampling-after keeping, the result that will take a sample-keep delivers to ADC.

In addition, in first and second embodiment of the present invention, because operational amplifier is differential amplifier, therefore can suppress common-mode noise (common noise).

[the 3rd embodiment]

Fig. 5 shows the high-level schematic functional block diagram according to the electronic installation of third embodiment of the invention.This electronic installation such as, but be not limited to, have the digital camera of Touch Screen.This electronic installation comprises: sensor 510, multiplexer 520 and ADC530.

Sensor 510 such as but not limited to, optical sensor, inclination sensor (tilt sensor), temperature sensor and humidity sensor.But sensor 510 sensing external environments, and be converted into aanalogvoltage.This aanalogvoltage converts digital signal to by ADC530, judges by the processing module of rear end how this controls electronic installation according to the output signal of ADC again.

For example, sensor 510 comprises optical sensor.If photosensor senses is dark to external light source, then back end processing module can make electronic installation enter low consumption pattern.But when photosensor senses to external light source when bright, the output voltage of optical sensor changes, therefore, back end processing module can make electronic installation enter normal manipulation mode.

Again for example, sensor 510 comprises inclination sensor.If inclination sensor to electronic installation be tilted/rotate certain angle (such as, the user is with electronic installation inclination/90-degree rotation), then its voltage of exporting can change to some extent, then back end processing module can make the on-screen displays of electronic installation cooperate this inclination/anglec of rotation, watches on-screen displays to make things convenient for the user.

Again for example, sensor 510 comprises temperature sensor or humidity sensor.According to temperature sensor or the humidity sensor sensing result of environment to external world, back end processing module can make electronic installation carry out the optimization adjustment.

Can as required, required sensor be joined in the electronic installation.Like this, electronic installation has advantages of intelligence (smart) operation.

Multiplexer 520 is used for selecting a ground from the output signal of voltage Vx or sensor and exports to ADC530.

ADC530 can be same or similar in the ADC of the first embodiment or the second embodiment, thereby do not repeat its details at this.In the 3rd embodiment, Vx is the voltage of the testing capacitance Cx of the first or second embodiment, and it can be used for detecting user's touch point position.In third embodiment of the invention, because Touch Screen and sensor sharing A DC, thereby electronic installation has advantages of that circuit area dwindles.

In addition, the inner member of the capacitance measurement circuit of the first embodiment or the second embodiment can according to circumstances need and be added in the electronic installation of the 3rd embodiment, and these all within the scope of the present invention.

In sum, although the present invention with the embodiment disclosure as above, yet it is not for limiting the present invention.The persons of ordinary skill in the technical field of the present invention without departing from the spirit and scope of the present invention, should make various changes and revise.Therefore, protection scope of the present invention should be as the criterion with the claims restricted portion.

The primary clustering symbol description

110: analog-digital converter 120: the capacitive partial pressure circuit

121～123: switch 130: processing module

Cs, Cx: electric capacity 305: analog-digital converter

310: operational amplifier 320: comparer

330: latch 340: phase inverter

350: counter 361～370: switch

371～375: electric capacity 380: the capacitive partial pressure circuit

381～383: switch 390: bias circuit

391～392: switch 393: electric capacity

410～450: sequential point 510: sensor

520: multiplexer 530:ADC.

Claims (4)

1. A capacitance measurement circuit, comprising: A capacitive voltage divider circuit, comprising: a switch circuit, a first capacitor and a second capacitor, the switch circuit is coupled to the first capacitor and the second capacitor, the switch circuit is controlled by the first clock signal and the second capacitor A second clock signal, the second clock signal is an inversion signal of the first clock signal, and the conduction state of the switch circuit makes the voltage variation of the first terminal of the first capacitor coupled to the first the first terminal of the second capacitor; an analog-to-digital converter coupled to the capacitive voltage divider circuit, the analog-to-digital converter converts the voltage at the first terminal of the second capacitor into a first digital signal; and a processing module, coupled to the analog-to-digital converter, the processing module detects the capacitance value of the second capacitor according to the first digital signal of the analog-to-digital converter and the parameters of the analog-to-digital converter and its variation, wherein the parameters of the analog-to-digital converter include: the resolution of the analog-to-digital converter and the conversion voltage interval, and the processing module is further based on the voltage value of the first voltage source and the voltage of the second voltage source value and the capacitance value of the first capacitor, the resolution of the analog-to-digital converter, the conversion voltage range of the analog-to-digital converter and the first digital signal of the analog-to-digital converter, so as to detect the first The capacitance value of the second capacitor and its variation. 2. The capacitance measuring circuit according to claim 1, wherein the switch circuit of the capacitive voltage divider circuit comprises: A first switch, the first end of which is coupled to the first voltage source, and the second end of which is coupled to the first end of the second capacitor, the conduction of the first switch is controlled by the first clock signal ; The first end of the second switch is coupled to the first voltage source, the second end is coupled to the first end of the first capacitor, and the conduction of the second switch is controlled by the first clock signal; and A third switch, the first end of which is coupled to the second voltage source, the second end of which is coupled to the first end of the first capacitor, and the conduction of the third switch is controlled by the second clock signal ; Wherein, the second end of the first capacitor is coupled to the first end of the second capacitor, and the second end of the second capacitor is coupled to a third voltage source. 3. The capacitance measuring circuit according to claim 1, further comprising: a bias voltage circuit, coupled to the capacitive voltage divider circuit and the analog-to-digital converter, the bias voltage circuit is used to apply a bias voltage to the first node, so that the voltage of the first node is the same as the bias voltage The voltage is related to the voltage of the first terminal of the second capacitor. 4. The capacitance measuring circuit according to claim 1, wherein the analog-to-digital converter comprises: A switch-sampling-capacitor circuit has: a first input end coupled to the first end of the second capacitor of the capacitive voltage divider circuit; and an output end; the switch-sampling-capacitance circuit is controlled by The first clock signal and the second clock signal are used to sample the voltage at the first end of the second capacitor of the capacitive voltage divider circuit; The operational amplifier has: a first input terminal coupled to the output terminal of the switch-sampling-capacitor circuit; a second input terminal; a first output terminal and a second output terminal; The comparator has: a first input terminal coupled to the first output terminal of the operational amplifier; a second input terminal coupled to the second output terminal of the operational amplifier; and an output terminal outputting a second digital signal ; a latch, configured to receive the second digital signal output by the comparator, and under the trigger of the first clock signal, the latch outputs the second digital signal into a third digital signal; an inverter, inverting the third digital signal; a counter counting the third digital signal to generate the first digital signal; and A switch-capacitor circuit, coupled to the second input terminal of the operational amplifier, controlled by the first clock signal, the second clock signal, the third digital signal and the inverse of the third digital signal phase signal.

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