CN108780372B - Capacitance sensing circuit and touch terminal - Google Patents
Capacitance sensing circuit and touch terminal Download PDFInfo
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- CN108780372B CN108780372B CN201780000065.8A CN201780000065A CN108780372B CN 108780372 B CN108780372 B CN 108780372B CN 201780000065 A CN201780000065 A CN 201780000065A CN 108780372 B CN108780372 B CN 108780372B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
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Abstract
A capacitance sensing circuit (10) for sensing a capacitance to be measured of a circuit (12) to be measured, said circuit (12) to be measured receiving an analog transmit signal (TX) and outputting an analog receive signal (RX), said capacitance sensing circuit (10) comprising an analog down-conversion circuit (14) for receiving an analog high frequency signal (AHF) and generating an analog intermediate frequency signal (AIF), wherein said analog high frequency signal (AHF) is related to said analog receive signal; -an analog-to-digital converter (16) for converting said analog intermediate frequency signal (AIF) into a first digital signal (D); and a capacitance judging circuit (18) for judging the capacitance of the capacitor to be measured according to the first digital signal (D); wherein the analog high-frequency signal (AHF) has a first frequency (fX), the analog intermediate-frequency signal (AIF) has a second frequency (fI), and the first frequency (fX) is greater than the second frequency (fI).
Description
Technical Field
The present disclosure relates to a capacitance sensing circuit, and more particularly, to a capacitance sensing circuit for reducing an operating frequency of an analog-to-digital converter and a touch terminal using the same.
Background
With the increasing progress of science and technology, in recent years, the operation interfaces of various electronic products are gradually humanized. For example, through the touch panel, a user can directly use a finger or a Stylus (Stylus) to operate and input information/text/patterns on the screen, thereby eliminating the trouble of using an input device such as a keyboard or a key. In practice, the touch screen generally comprises a sensing panel and a display disposed behind the sensing panel. The electronic device judges the intention of the touch according to the position touched by the user on the sensing panel and the picture presented by the display at that time, and executes the corresponding operation result.
The capacitive touch technology is used for judging a touch event by sensing the Capacitance variation of a capacitor to be detected in a circuit to be detected, the existing capacitive touch technology can be divided into a Self-Capacitance type (Self-Capacitance) and a Mutual-Capacitance type (Mutual-Capacitance), the Capacitance sensing circuit in a Self-Capacitance type touch panel or a Mutual-Capacitance type touch panel can convert the capacitor of the capacitor to be detected into an analog output signal, and the analog output signal is converted into a digital signal by using an analog-digital converter so as to be judged by a rear-end Capacitance judging circuit. When a user operates on the touch screen with a Stylus (Stylus), the Stylus transmits an analog transmission signal to the touch screen, and the transmission signal transmitted by the Stylus is usually a high frequency signal, so that the analog output signal is also a high frequency signal. In order to accurately interpret the capacitance of the capacitor to be measured, an Analog-to-Digital converter (ADC) needs a higher sampling frequency, i.e., the ADC needs to be implemented by a more complex circuit, which increases the production cost. On the other hand, when the operating frequency of the adc is high, the operation amount of the back-end capacitance determination circuit is large, which increases power consumption.
Therefore, there is a need for improvement in the prior art.
Disclosure of Invention
It is therefore a primary objective of some embodiments of the present invention to provide a capacitance sensing circuit that can reduce the operating frequency of an analog-to-digital converter, so as to overcome the disadvantages of the prior art.
In order to solve the above technical problem, the present application provides a capacitance sensing circuit for sensing a to-be-measured capacitance of a to-be-measured circuit, wherein the to-be-measured circuit receives an analog transmission signal and outputs an analog reception signal, and the capacitance sensing circuit includes an analog down-conversion circuit, coupled to the to-be-measured circuit, for receiving an analog high-frequency signal and generating an analog intermediate-frequency signal, wherein the analog high-frequency signal is related to the analog reception signal; an analog-to-digital converter for converting the analog intermediate frequency signal into a first digital signal; the capacitance judging circuit is coupled to the analog signal converter and used for judging the capacitance of the capacitor to be detected according to the first digital signal; the analog high-frequency signal has a first frequency, the analog intermediate-frequency signal has a second frequency, and the first frequency is greater than the second frequency.
For example, the analog down-conversion circuit includes a switching mixer for receiving the analog high-frequency signal; and an integrating circuit for outputting the analog intermediate frequency signal.
For example, the switching mixer includes a forward buffer having a forward input end for receiving the analog high frequency signal; and a forward output end; a negative buffer having a negative input for receiving the analog high frequency signal; and a negative output terminal; and the switch unit is coupled with the positive output end and the negative output end and is controlled by a switch signal, and the switch unit outputs a mixing signal.
For example, the integration circuit includes an amplifier; and a first integrating capacitor coupled between a first input terminal and an output terminal of the amplifier.
For example, the analog down converter circuit further includes an impedance unit coupled between the switching mixer and the integrator circuit.
For example, the impedance unit includes a resistor.
For example, the impedance unit includes a capacitor having a first end and a second end; a first switch coupled between the first end of the capacitor and the switching mixer; a second switch coupled between the first end of the capacitor and a ground terminal; a third switch coupled between the second end of the capacitor and the integration circuit; and a fourth switch coupled between the second end of the capacitor and the ground terminal.
For example, the switching mixer has a first mixing input terminal, a second mixing input terminal, a first mixing output terminal and a second mixing output terminal, and the integrating circuit has a first integrating input terminal, a second integrating input terminal, a first integrating output terminal and a second integrating output terminal.
For example, the switching mixer includes a first mixing switch coupled between the first mixing input terminal and the first mixing output terminal; a second mixing switch coupled between the second mixing input terminal and the second mixing output terminal; a third mixing switch coupled between the first mixing input terminal and the second mixing output terminal; and a fourth mixing switch coupled between the second mixing input terminal and the first mixing output terminal.
For example, the integration circuit includes a fully differential amplifier coupled to the first integration input terminal, the second integration input terminal, the first integration output terminal, and the second integration output terminal; a first integration capacitor coupled between the first integration input terminal and the first integration output terminal; and a second integration capacitor coupled between the second integration input terminal and the second integration output terminal.
For example, the analog down-conversion circuit further includes a first impedance unit coupled between the first mixing output terminal and the first integrating input terminal; and a second impedance unit coupled between the second mixing output terminal and the second integration input terminal.
For example, the first impedance unit and the second impedance unit each include a resistor.
For example, each of the first impedance unit and the second impedance unit includes a capacitor having a first end and a second end; a first switch coupled to the first end of the capacitor; a second switch coupled between the first end of the capacitor and a ground terminal; a third switch coupled to the second end of the capacitor; and a fourth switch coupled between the second end of the capacitor and the ground terminal.
For example, the capacitance sensing circuit further includes an analog front-end circuit coupled between the circuit under test and the analog down-conversion circuit for receiving the analog receiving signal and generating the analog high-frequency signal.
For example, the analog transmit signal is generated by an active capacitive stylus.
For example, a sampling frequency of the analog-to-digital converter is greater than 2 times the second frequency-.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
Fig. 1 is a schematic diagram of a capacitance sensing circuit according to an embodiment of the present disclosure.
Fig. 2 is a schematic diagram of an analog down converter circuit according to an embodiment of the present disclosure.
Fig. 3 is a schematic diagram of an analog down converter circuit according to an embodiment of the present application.
Fig. 4 is a schematic diagram of an analog down converter circuit according to an embodiment of the present application.
Fig. 5 is a schematic diagram of an analog down converter circuit according to an embodiment of the present application.
Fig. 6 is a schematic diagram of a capacitance determining circuit according to an embodiment of the present disclosure.
FIG. 7 is a schematic diagram of an analog down converter circuit according to an embodiment of the present application.
Fig. 8 is a schematic diagram of an analog down converter circuit according to an embodiment of the present application.
Fig. 9 is a schematic diagram of an analog down converter circuit according to an embodiment of the present application.
Fig. 10 is a schematic diagram of an analog down converter circuit according to an embodiment of the present application.
Fig. 11 is a schematic diagram of an analog down converter circuit according to an embodiment of the present application.
Fig. 12 is a schematic diagram of an analog down converter circuit according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
Fig. 1 is a schematic diagram of a capacitance sensing circuit 10 according to an embodiment of the present disclosure. The capacitance sensing circuit 10 is coupled to a circuit to be tested 12, the circuit to be tested 12 receives an analog transmission signal TX and outputs an analog reception signal RX, and the capacitance sensing circuit 10 senses a capacitance of a capacitor to be tested CUT of the circuit to be tested 12 according to the analog reception signal RX. The capacitive sensing circuit 10 can be applied to a touch screen, and the analog transmission signal TX can be generated by an active capacitive Stylus (Stylus). The capacitance sensing circuit 10 includes an Analog front end circuit 13, an Analog down converter 14, an Analog-to-Digital converter (ADC) 16, and a capacitance determination circuit 18. The analog front-end circuit 13 is coupled to the circuit under test 12, and may include a buffer, a filter or an amplifier for performing analog front-end signal processing on the analog received signal RX, and the analog front-end circuit 13 generates an analog high-frequency signal AHF. The analog down converter circuit 14 is coupled to the analog front-end circuit 13, and is configured to receive the analog high-frequency signal AHF and generate an analog intermediate-frequency signal AIF. The adc 16 is coupled to the analog down-conversion circuit 14 for converting the analog if signal AIF into a digital signal D. The capacitance determining circuit 18 is coupled to the adc 16 for determining the capacitance of the capacitor CUT according to the digital signal D.
It should be noted that the analog high frequency signal AHF has a frequency fX, the analog intermediate frequency signal AIF has a frequency fI, and the frequency fX is greater than the frequency fI. In one embodiment, the frequency fX of the analog high-frequency signal AHF may be 200KHz, and the analog down-conversion circuit 14 may down-convert the analog high-frequency signal AHF to the analog intermediate-frequency signal AIF having 20KHz (i.e., the frequency fI is 20 KHz). In this way, the operating frequency of the adc 16 can be reduced, and when the operating frequency of the adc 16 is lower (compared to the frequency fX), the sampling data of the adc 16 per unit time is less (compared to the input signal of the adc is the analog high frequency signal AHF), so that the computation amount of the capacitance determining circuit 18 (which is a digital circuit) can be reduced. Furthermore, since the analog-to-digital converter 16 has a lower operating frequency, the analog-to-digital converter 16 can use a simpler circuit to achieve Oversampling (e.g., using a Delta-sigma analog-to-digital converter (Delta-sigma ADC)), so as to increase an Oversampling rate (OSR) of the analog-to-digital converter 16, and further reduce Quantization Noise (Quantization Noise) of the analog-to-digital converter 16 to obtain a better resolution. The oversampling of the analog-to-digital converter 16 (the analog intermediate Frequency Signal AIF) means that the analog-to-digital converter 16 samples the analog intermediate Frequency Signal AIF at a Sampling Frequency (Sampling Frequency) greater than N times the Frequency fI-, for example, when N is greater than 10, the quantization Noise can be effectively reduced, and the Signal-to-Noise Ratio (SNR) can be improved.
For the specific circuit of the analog down-conversion circuit 14, please refer to fig. 2 to 5. Fig. 2 to 5 are schematic diagrams of an analog down-conversion circuit 24, an analog down-conversion circuit 34, an analog down-conversion circuit 44, and an analog down-conversion circuit 54 according to different embodiments of the present invention, where the analog down- conversion circuits 24, 34, 44, and 54 can be used to implement the analog down-conversion circuit 14, where the analog down- conversion circuits 24 and 34 are Single-Ended Output (Single-Ended Input Single-Ended Output) circuits, and the analog down-conversion circuits 44 and 54 are Differential Input Differential Output (Differential Input Differential Output) circuits.
As shown in fig. 2, the analog down-conversion circuit 24 includes an impedance unit 244, a Switching Mixer 240(Switching Mixer), and an integrating circuit 242, the impedance unit 244 is coupled between the Switching Mixer 240 and the integrating circuit 242, the Switching Mixer 240 is used for receiving the analog high-frequency signal AHF, and the integrating circuit 242 is used for outputting the analog intermediate-frequency signal AIF. In detail, the switching mixer 240 includes a positive buffer (labeled as "1"), a negative buffer (labeled as "1"), and a switching unit SWM, wherein a positive input terminal of the positive buffer and a negative input terminal of the negative buffer are used for receiving the analog high-frequency signal AHF, the switching unit SWM is coupled to a positive output terminal of the positive buffer and a negative output terminal of the negative buffer, the switching unit SWM is controlled by a switching signal SC to switch between the positive output terminal and the negative output terminal, and the switching unit SWM is used for switching the integration direction of the integrating circuit 242. The switching signal SC may have two different signal values, which may be a logic 1 or a logic 0, or a signal having a signal value of a or-a. In addition, the switching signal SC may have a frequency fX + fI or a frequency fX-fI. The impedance unit 244 includes a resistor R, the integrating circuit 242 includes an amplifier Amp and an integrating capacitor CI coupled between a negative input terminal (labeled with the "sign") and an output terminal of the amplifier Amp, and a positive input terminal (labeled with the "plus" sign) of the amplifier Amp receives a reference voltage VREF.
As shown in FIG. 3, analog down converter circuit 34 is similar to analog down converter circuit 24, and like components are labeled similarly. Unlike the analog down converter 24, the analog down converter 34 includes an impedance unit 344, and the impedance unit 344 is a Switched Capacitor (Switched Capacitor) module including a Capacitor CS and switches SW 1-SW 4. The switch SW1 is coupled between a first end of the capacitor CS and the switching mixer 240; the switch SW2 is coupled between the first terminal of the capacitor CS and a ground terminal; the switch SW3 is coupled between a second terminal of the capacitor CS and the integrating circuit 242; the switch SW4 is coupled between the second terminal of the capacitor CS and the ground terminal. The switches SW 1-SW 4 can be controlled by the frequency control signals ph1 and ph2, wherein the frequency control signals ph1 and ph2 are orthogonal frequency control signals (i.e. the time when the frequency control signals ph1 and ph2 are at high potential do not overlap each other). Specifically, in one embodiment, the clock control signal ph1 is used to control the on states of the switches SW1 and SW3, and the clock control signal ph2 is used to control the on states of the switches SW2 and SW 4; in another embodiment, the clock control signal ph1 can be used to control the on states of the switches SW1 and SW4, and the clock control signal ph2 can be used to control the on states of the switches SW2 and SW 3. The frequency of the frequency control signals ph1 and ph2 is equal to or higher than the frequency fI —, that is, the frequency of the frequency control signals ph1 and ph2 is equal to or higher than the frequency fI —.
As shown in fig. 4, the analog down-conversion circuit 44 includes an impedance unit 444A, an impedance unit 444B, a switching mixer 440 and an integrator 442, wherein the switching mixer 440 has a first mixing input terminal, a second mixing input terminal, a first mixing output terminal and a second mixing output terminal; the integrating circuit 442 has a first integrating input terminal, a second integrating input terminal, a first integrating output terminal, and a second integrating output terminal, wherein the first mixing input terminal and the second mixing input terminal are used for receiving the analog high-frequency signal AHF, and the first integrating output terminal and the second integrating output terminal are used for outputting the analog intermediate-frequency signal AIF. In addition, the impedance unit 444A is coupled between the first mixing output terminal and the first integrating input terminal, and the impedance unit 444A includes a resistor RA; the impedance unit 444B is coupled between the second mixing output terminal and the second integrating input terminal, and the impedance unit 444B includes a resistor RB. Specifically, the switching mixer 440 includes mixing switches S1-S4, the mixing switch S1 is coupled between the first mixing input terminal and the first mixing output terminal; the mixing switch S2 is coupled between the second mixing input terminal and the second mixing output terminal; the mixing switch S3 is coupled between the first mixing input terminal and the second mixing output terminal; the mixing switch S4 is coupled between the second mixing input terminal and the first mixing output terminal. The mixing switches S1-S4 can be controlled by the frequency control signals ph1 'and ph 2', wherein the frequency control signals ph1 'and ph 2' are orthogonal frequency control signals (i.e. the time when the frequency control signals ph1 'and ph 2' are high-level signals do not overlap with each other), and the switch signals ph1 'and ph 2' can have a frequency fX + fI or a frequency fX-fI. Specifically, in one embodiment, the clock control signal ph1 'is used to control the on states of the switches S1 and S2, and the clock control signal ph 2' is used to control the on states of the switches S3 and S4.
In addition, the integrating circuit 442 includes a fully differential amplifier DAmp, and integrating capacitors CIA and CIB, wherein a negative input terminal (labeled with "sign") of the fully differential amplifier DAmp is coupled to the first integrating input terminal, a positive input terminal (labeled with "plus" sign) of the fully differential amplifier DAmp is coupled to the second integrating input terminal, a positive output terminal (labeled with "plus" sign) of the fully differential amplifier DAmp is coupled to the first integrating output terminal, and a negative output terminal (labeled with "sign") of the fully differential amplifier DAmp is coupled to the second integrating output terminal. The integrating capacitor CIA is coupled between the negative input terminal and the positive output terminal of the fully differential amplifier DAmp (i.e. the integrating capacitor CIA is coupled between the first integrating input terminal and the first integrating output terminal); the integrating capacitor CIB is coupled between the positive input terminal and the negative output terminal of the fully differential amplifier DAmp (i.e., the integrating capacitor CIA is coupled between the second integrating input terminal and the second integrating output terminal).
As shown in FIG. 5, analog down conversion circuit 54 is similar to analog down conversion circuit 44, and like components are labeled similarly. Unlike analog down-conversion circuit 44, analog down-conversion circuit 54 includes an impedance unit 544A and an impedance unit 544B. The circuit structures of the impedance units 544A and 544B are the same as the impedance unit 344, and are not described herein again.
In addition, the capacitance determination circuit 18 is not limited to being implemented with a specific circuit configuration. For example, referring to fig. 6, fig. 6 is a schematic diagram of a capacitance determination circuit 68 according to an embodiment of the present application, and the capacitance determination circuit 68 may be used to implement the capacitance determination circuit 18. The capacitance determination circuit 68 includes multipliers MP1, MP2, a waveform generator 680, a phase rotator 682, digital integrators 684, 686, and a capacitance measuring device (Capacitor measuring) 688. The capacitance determining circuit 68 may perform digital signal integration on an In-Phase Component (In Phase Component) and a Quadrature Component (Quadrature Component) of the digital signal D, respectively, to achieve more accurate interpretation of the capacitance CUT to be measured. The operation of the capacitance determination circuit 68 is well known to those skilled in the art and will not be described herein.
It should be noted that the foregoing embodiments are provided to illustrate the concepts of the present application and that various modifications can be made by those skilled in the art without limiting the scope of the invention. For example, the impedance unit coupled between the switching mixer and the integrating circuit may include both resistors and switching capacitor modules, and the connection manner between the resistors in the impedance unit and the switching capacitor modules may be adjusted according to the actual situation, for example, please refer to fig. 7 to 12, and fig. 7 to 12 are schematic diagrams of an analog down-conversion circuit 74, an analog down-conversion circuit 84, an analog down-conversion circuit 94, an analog down-conversion circuit a4, an analog down-conversion circuit B4, and an analog down-conversion circuit C4 in different embodiments of the present application, respectively. The analog down conversion circuits 74, 84, 94, A4, B4, and C4 can be used to implement the analog down conversion circuit 14. The analog down- conversion circuits 74, 84, and 94 are similar to the analog down- conversion circuits 24 and 34, so the same components are labeled with the same symbols, and different from the analog down- conversion circuits 24 and 34, the analog down- conversion circuits 74, 84, and 94 respectively include impedance units 744, 844, and 944, each of the impedance units 744, 844, and 944 includes a resistor R and a switched capacitor module, and the circuit structure of the switched capacitor module is the same as that of the impedance unit 344. The impedance units 744, 844, 944 are different from each other in the connection relationship between the resistor R and the switched capacitor module, for example, in the impedance unit 744, the resistor R is coupled between the switch SW3 of the switched capacitor module and the integrating circuit 242; in the impedance unit 844, the resistor R is coupled between the switching mixer 240 and the switch SW1 of the switched capacitor module; in the impedance unit 944, the resistor R is coupled between the switches SW1 and SW2 of the switched capacitor module and the capacitor CS.
Similarly, the analog down-conversion circuits A4, B4, and C4 are similar to the analog down-conversion circuits 44 and 54, and therefore the same reference numerals are used for the same components. Unlike the analog down-conversion circuits 44 and 54, the analog down-conversion circuits a4, B4, and C4 respectively include impedance units a44, B44, and C44, each of the impedance units a44, B44, and C44 includes a resistor R and a switched capacitor module, wherein the switched capacitor module has the same circuit structure as the impedance unit 544A (or the impedance unit 544B). The impedance units a44, B44, and C44 are different from each other in the connection relationship between the resistor R and the switched capacitor module, and the variation thereof is the same as the variation of the impedance units 744, 844, and 944 with respect to the impedance units 244 and 344, and therefore, the description thereof is omitted.
In summary, before entering the adc, the analog down-conversion circuit down-converts the high frequency analog high frequency signal into an intermediate frequency analog signal, so as to reduce the operating frequency of the dac and reduce the operation amount of the digital capacitance determination circuit.
The invention is not to be considered as limited to the particular embodiments shown and described, but is to be understood to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Claims (16)
1. A capacitance sensing circuit for sensing a to-be-tested capacitance of a to-be-tested circuit, the to-be-tested circuit receiving an analog transmission signal and outputting an analog reception signal, the capacitance sensing circuit comprising:
an analog down converter circuit, coupled to the circuit under test, for receiving an analog high frequency signal and generating an analog intermediate frequency signal, wherein the analog high frequency signal is related to the analog received signal; the analog frequency reducing circuit comprises: a switching mixer for receiving the analog high frequency signal; and an integrating circuit for outputting the analog intermediate frequency signal; the switching type mixer comprises a switch unit, the switch unit is controlled by a switch signal, and the switch unit outputs a mixed signal; the switching signal has a frequency fX + fI or a frequency fX-fI;
an analog-to-digital converter for converting the analog intermediate frequency signal into a first digital signal; and
a capacitance determining circuit, coupled to the adc, for determining a capacitance of the capacitor to be measured according to the first digital signal;
the analog high-frequency signal has a first frequency fX, the analog intermediate-frequency signal has a second frequency fI, and the first frequency fX is greater than the second frequency fI.
2. The capacitance sensing circuit of claim 1, wherein the switched mixer comprises:
a forward buffer comprising:
a positive input end for receiving the analog high-frequency signal; and
a forward output end;
a negative-going buffer, comprising:
a negative input terminal for receiving the analog high frequency signal; and
a negative output terminal; and
the switch unit is coupled to the positive output end and the negative output end.
3. The capacitive sensing circuit of claim 1, wherein the integration circuit comprises:
an amplifier; and
the first integrating capacitor is coupled between a first input end and an output end of the amplifier.
4. The capacitive sensing circuit of claim 1, wherein said analog down conversion circuit further comprises:
an impedance unit coupled between the switching mixer and the integrator circuit.
5. The capacitive sensing circuit of claim 4, wherein said impedance unit comprises a resistor.
6. The capacitive sensing circuit of claim 4, wherein the impedance unit comprises:
a capacitor including a first end and a second end;
a first switch coupled between the first end of the capacitor and the switching mixer;
a second switch coupled between the first end of the capacitor and a ground terminal;
a third switch coupled between the second end of the capacitor and the integration circuit; and
a fourth switch coupled between the second end of the capacitor and the ground terminal.
7. The capacitance sensing circuit of claim 1, wherein the switching mixer has a first mixing input, a second mixing input, a first mixing output, and a second mixing output, and the integrating circuit has a first integrating input, a second integrating input, a first integrating output, and a second integrating output.
8. The capacitive sensing circuit of claim 7, wherein the switching unit comprises:
a first mixing switch coupled between the first mixing input terminal and the first mixing output terminal;
a second mixing switch coupled between the second mixing input terminal and the second mixing output terminal;
a third mixing switch coupled between the first mixing input terminal and the second mixing output terminal; and
and the fourth mixing switch is coupled between the second mixing input end and the first mixing output end.
9. The capacitive sensing circuit of claim 7, wherein the integration circuit comprises:
a fully differential amplifier coupled to the first integration input, the second integration input, the first integration output, and the second integration output;
a first integration capacitor coupled between the first integration input terminal and the first integration output terminal; and
a second integration capacitor coupled between the second integration input terminal and the second integration output terminal.
10. The capacitive sensing circuit of claim 7, wherein said analog down conversion circuit further comprises:
a first impedance unit coupled between the first mixing output terminal and the first integration input terminal; and
and the second impedance unit is coupled between the second mixing output end and the second integral input end.
11. The capacitive sensing circuit of claim 10, wherein said first impedance unit and said second impedance unit each comprise a resistor.
12. The capacitive sensing circuit of claim 10, wherein the first impedance unit and the second impedance unit each comprise:
a capacitor including a first end and a second end;
a first switch coupled to the first end of the capacitor;
a second switch coupled between the first end of the capacitor and a ground terminal;
a third switch coupled to the second end of the capacitor; and
a fourth switch coupled between the second end of the capacitor and the ground terminal.
13. The capacitive sensing circuit of claim 7, further comprising:
and the analog front-end circuit is coupled between the circuit to be tested and the analog frequency reduction circuit and is used for receiving the analog receiving signal and generating the analog high-frequency signal.
14. The capacitive sensing circuit of claim 1, wherein the analog transmit signal is generated by an active capacitive stylus.
15. The capacitive sensing circuit of claim 1, wherein a sampling frequency of said analog-to-digital converter is greater than 2 times said second frequency fI.
16. A touch terminal, comprising a touch screen and a capacitance sensing circuit, wherein the capacitance sensing circuit is configured to detect a capacitance of at least one capacitor to be tested of the touch screen, and the capacitance sensing circuit employs the capacitance sensing circuit according to any one of claims 1 to 15.
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| PCT/CN2017/070993 WO2018129698A1 (en) | 2017-01-12 | 2017-01-12 | Capacitance sensing circuit and touch control terminal |
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| CN108780372B true CN108780372B (en) | 2021-08-10 |
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| CN102135828A (en) * | 2010-01-26 | 2011-07-27 | 禾瑞亚科技股份有限公司 | Method and device for signal detection |
| CN102721893A (en) * | 2011-02-25 | 2012-10-10 | 马克西姆综合产品公司 | Circuits, devices and methods having pipelined capacitance sensing |
| CN104679366A (en) * | 2013-12-03 | 2015-06-03 | 原相科技股份有限公司 | Capacitive touch sensing system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108780372A (en) | 2018-11-09 |
| WO2018129698A1 (en) | 2018-07-19 |
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