WO2018129698A1

WO2018129698A1 - Capacitance sensing circuit and touch control terminal

Info

Publication number: WO2018129698A1
Application number: PCT/CN2017/070993
Authority: WO
Inventors: 杨富强; 文亚南; 梁颖思
Original assignee: 深圳市汇顶科技股份有限公司
Priority date: 2017-01-12
Filing date: 2017-01-12
Publication date: 2018-07-19
Also published as: CN108780372A; CN108780372B

Abstract

A capacitance sensing circuit (10), for sensing a capacitance to be measured of a circuit to be measured (12), with the circuit to be measured (12) receiving an analogue transmission signal (TX) and outputting an analogue receiving signal (RX). The capacitance sensing circuit (10) comprises an analogue frequency reduction circuit (14), for receiving an analogue high frequency signal (AHF) and generating an analogue intermediate frequency signal (AIF), wherein the analogue high frequency signal (AHF) is related to the analogue receiving signal; an analogue-to-digital converter (16), for converting the analogue intermediate frequency signal (AIF) into a first digital signal (D); and a capacitance judgement circuit (18), for judging the capacitance of the capacitance to be measured according to the first digital signal (D), wherein the analogue high frequency signal (AHF) has a first frequency (fX), the analogue intermediate frequency signal (AIF) has a second frequency (fI), and the first frequency (fX) is greater than the second frequency (fI).

Description

Capacitance sensing circuit and touch terminal

Technical field

The present application relates to a capacitive sensing circuit, and more particularly to a capacitive sensing circuit for reducing the operating frequency of an analog to digital converter and a touch terminal using the same.

Background technique

With the advancement of technology, the operational interfaces of various electronic products have gradually become more humanized in recent years. For example, through the touch panel, the user can directly operate on the screen with a finger or a stylus (Stylus), input information/text/pattern, and save the trouble of using an input device such as a keyboard or a button. In fact, the touch screen usually consists of a sensing panel and a display disposed behind the sensing panel. The electronic device determines the intention of the touch according to the position touched by the user on the sensing panel and the picture presented by the display at that time, and executes the corresponding operation result.

Capacitive touch technology utilizes the amount of capacitance change of the capacitor to be tested in the circuit under test to interpret the touch event. The existing capacitive touch technology can be divided into self-capacitance and mutual capacitance (Mutual). -Capacitance), the capacitive sensing circuit in the self-capacitive touch panel or the mutual capacitive touch panel converts the capacitance of the capacitor to be tested into an analog output signal, and converts the analog output signal into an analog to digital converter. The digital signal is interpreted by the back end capacitance judging circuit. When the user uses the stylus (Stylus) to operate on the touch screen, the stylus transmits an analog transmission signal to the touch screen, and the transmission signal transmitted by the stylus is usually a high frequency signal, so that the simulation The output signal is also a high frequency signal. In order to accurately interpret the capacitance value of the capacitor to be tested, an analog-to-digital converter (Analog-to-Digital) Convertor, ADC) requires a higher sampling frequency, that is, the analog-to-digital converter needs to be implemented with more complicated circuits, which increases the production cost. On the other hand, when the operating frequency of the analog-to-digital converter is high, the amount of calculation of the back-end capacitance judging circuit is large, and power consumption is increased.

Therefore, the prior art is in need of improvement.

Summary of the invention

Accordingly, a primary object of some embodiments of the present invention is to provide a capacitive sensing circuit that reduces the operating frequency of an analog to digital converter to improve the shortcomings of the prior art.

In order to solve the above technical problem, the present application provides a capacitance sensing circuit for sensing a capacitance to be tested of a circuit to be tested, the circuit to be tested receiving an analog transmission signal and outputting an analog reception signal. The capacitive sensing circuit includes an analog down-converting circuit coupled to the circuit to be tested for receiving an analog high frequency signal and generating an analog intermediate frequency signal, wherein the analog high frequency signal is related to the analog received signal An analog-to-digital converter for converting the analog intermediate frequency signal into a first digital signal; and a capacitance determining circuit coupled to the analog signal converter for determining the first digital signal The capacitance of the capacitor to be tested; wherein the analog high frequency signal has a first frequency, the analog intermediate frequency signal has a second frequency, and the first frequency is greater than the second frequency.

For example, the analog down-converting circuit includes a switching mixer for receiving the analog high frequency signal; and an integrating circuit for outputting the analog intermediate frequency signal.

For example, the switched mixer includes a forward buffer including a forward input for receiving the analog high frequency signal; and a forward output; a negative buffer including a negative input a terminal for receiving the analog high frequency signal; and a negative output terminal; and a switching unit coupled Connected to the forward output terminal and the negative output terminal, the switch unit is controlled by a switch signal, and the switch unit outputs a mixed wave signal.

For example, the integrating circuit includes an amplifier; and a first integrating capacitor coupled between a first input end and an output end of the amplifier.

For example, the analog down-conversion circuit further includes an impedance unit coupled between the switching mixer and the integrating circuit.

For example, the impedance unit includes a resistor.

For example, the impedance unit includes a capacitor including a first end and a second end; a first switch is coupled between the first end of the capacitor and the switching mixer; a second switch is coupled between the first end of the capacitor and a ground; a third switch is coupled between the second end of the capacitor and the integrating circuit And a fourth switch coupled between the second end of the capacitor and the ground.

For example, the switching mixer has a first mixed wave input terminal, a second mixed wave input terminal, a first mixed wave output terminal and a second mixed wave output terminal, and the integrating circuit has a first integral. The input end, a second integral input end, a first integral output end, and a second integral output end.

For example, the switching mixer includes a first mixing switch coupled between the first mixing input terminal and the first mixed wave output terminal; and a second mixing switch coupled to the second mixing switch Between the second mixed wave input end and the second mixed wave output end; a third mixed wave switch coupled between the first mixed wave input end and the second mixed wave output end; And a fourth mixing switch coupled between the second mixed wave input end and the first mixed wave output end.

For example, the integrating circuit includes a fully differential amplifier coupled to the first integrating input terminal, the second integrating input terminal, the first integrating output terminal, and the second integrating output terminal; a first integrating capacitor coupled between the first integrating input and the first integrating output; and a second integrating capacitor coupled to the second integrating input and the second integrated output Between the ends.

For example, the analog down-conversion circuit further includes a first impedance unit coupled between the first mixed wave output end and the first integral input end, and a second impedance unit coupled to the Between the second mixed wave output and the second integral input.

For example, the first impedance unit and the second impedance unit each include a resistor.

For example, the first impedance unit and the second impedance unit each include a capacitor including a first end and a second end; a first switch is coupled to the first end of the capacitor; a second switch is coupled between the first end of the capacitor and a ground; a third switch coupled to the second end of the capacitor; and a fourth switch And coupled between the second end of the capacitor and the ground.

For example, the capacitive sensing circuit further includes an analog front end circuit coupled between the circuit to be tested and the analog down-converting circuit for receiving the analog received signal and generating the analog high frequency signal. .

For example, the analog transmission signal is generated by an active capacitive stylus.

For example, a sampling frequency of the analog to digital converter is greater than twice the second frequency.

DRAWINGS

The one or more embodiments are exemplified by the accompanying drawings in the accompanying drawings, and FIG. The figures in the drawings do not constitute a scale limitation unless otherwise stated.

FIG. 1 is a schematic diagram of a capacitance sensing circuit according to an embodiment of the present application.

2 is a schematic diagram of an analog down frequency circuit according to an embodiment of the present application.

FIG. 3 is a schematic diagram of an analog down frequency circuit according to an embodiment of the present application.

4 is a schematic diagram of an analog down-conversion circuit according to an embodiment of the present application.

FIG. 5 is a schematic diagram of an analog down frequency circuit according to an embodiment of the present application.

FIG. 6 is a schematic diagram of a capacitance determining circuit according to an embodiment of the present application.

FIG. 7 is a schematic diagram of an analog down frequency circuit according to an embodiment of the present application.

FIG. 8 is a schematic diagram of an analog down frequency circuit according to an embodiment of the present application.

FIG. 9 is a schematic diagram of an analog down frequency circuit according to an embodiment of the present application.

FIG. 10 is a schematic diagram of an analog down frequency circuit according to an embodiment of the present application.

FIG. 11 is a schematic diagram of an analog down frequency circuit according to an embodiment of the present application.

FIG. 12 is a schematic diagram of an analog down frequency circuit according to an embodiment of the present application.

detailed description

In order to make the objects, technical solutions, and advantages of the present application more comprehensible, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the application and are not intended to be limiting.

FIG. 1 is a schematic diagram of a capacitive sensing circuit 10 according to an embodiment of the present application. The capacitance sensing circuit 10 is coupled to a circuit 12 to be tested. The circuit 12 to be tested receives an analog transmission signal TX and outputs an analog receiving signal RX. The capacitance sensing circuit 10 senses one of the circuits 12 to be tested according to the analog receiving signal RX. The capacitance of the capacitor CUT to be tested. The capacitive sensing circuit 10 can be applied to a touch screen, and the analog transmission signal TX can be generated by an active capacitive stylus (Stylus). The capacitance sensing circuit 10 includes an analog front end circuit 13, an analog down frequency circuit 14, and an analog to digital converter (Analog-to-Digital). Convertor, ADC) 16 and a capacitance judging circuit 18. The analog front end circuit 13 is coupled to the circuit 12 to be tested, and may include a buffer, a filter or an amplifier for performing analog front end signal processing on the analog received signal RX, and the analog front end circuit 13 generates an analog high frequency signal AHF. . The analog down-conversion circuit 14 is coupled to the analog front end circuit 13 for receiving the analog high frequency signal AHF and generating an analog intermediate frequency signal AIF. The analog-to-digital converter 16 is coupled to the analog down-conversion circuit 14 for converting the analog intermediate frequency signal AIF into a digital signal D. The capacitance determining circuit 18 is coupled to the analog-to-digital converter 16 for determining the capacitance of the capacitor CUT to be tested according to the digital signal D.

It should be noted that the analog high frequency signal AHF has a frequency fX, the analog intermediate frequency signal AIF has a frequency fI, and the frequency fX is greater than the frequency fI. In one embodiment, the frequency fX of the analog high frequency signal AHF may be 200 KHz, and the analog down frequency circuit 14 may down-convert the analog high frequency signal AHF to an analog intermediate frequency signal AIF having a 20 KHz (ie, the frequency fI is 20 KHz). In this way, the operating frequency of the analog-to-digital converter 16 can be lowered. When the analog-to-digital converter 16 operates at a lower frequency (compared to the frequency fX), the analog-to-digital converter 16 per unit time samples less data. The input signal to the analog-to-digital converter is the analog high-frequency signal AHF), which in turn reduces the amount of computation of the capacitance judging circuit 18 (which is a digital circuit). Further, since the operating frequency of the analog-to-digital converter 16 is low, the analog-to-digital converter 16 can implement oversampling (such as using a delta-sigma analog-to-digital converter (Delta-sigma ADC)) using a simpler circuit. An Oversample Ratio (OSR) of the analog-to-digital converter 16 is boosted, thereby reducing the quantization noise of the analog-to-digital converter 16 to obtain a better resolution. Wherein, the analog-to-digital converter 16 (oversampling the analog intermediate frequency signal AIF) means that the analog-to-digital converter 16 samples the analog intermediate frequency signal AIF at a sampling frequency greater than N times the frequency fI-, for example, when N When it is greater than 10, the quantization noise can be effectively reduced to improve the Signal-to-Noise Ratio (SNR).

Regarding the specific circuit of the analog down converter circuit 14, please refer to FIG. 2 to FIG. 2 to FIG. 5 are schematic diagrams showing an analog down-conversion circuit 24, an analog down-conversion circuit 34, an analog down-conversion circuit 44, and an analog down-conversion circuit 54 in various embodiments of the present application. The analog down-

conversion circuits

24, 34 are shown in FIG. 44, 54 can be used to implement the analog down-conversion circuit 14, wherein the analog down-

conversion circuits

24, 34 are single-ended input single-ended output (Single-Ended Input Single-Ended Output) circuit, and the analog down-conversion circuit 44, 54 is a circuit of Differential Input Differential Output.

As shown in FIG. 2 , the analog down converter circuit 24 includes an impedance unit 244 , a switching mixer 240 (Switching Mixer), and an integrating circuit 242 . The impedance unit 244 is coupled to the switching mixer 240 and the integrating circuit 242 . Between the switching mixer 240 is used to receive the analog high frequency signal AHF, and the integrating circuit 242 is used to output the analog intermediate frequency signal AIF. In detail, the switching mixer 240 includes a forward buffer (labeled "+1"), a negative buffer (labeled "-1"), and a switching unit SWM, one of the forward buffers. The negative input of one of the forward input terminal and the negative buffer is used to receive the analog high frequency signal AHF, and the switch unit SWM is coupled to one of the forward output of the forward buffer and one of the negative output of the negative buffer. The switching unit SWM is controlled between a forward output terminal and a negative output terminal by a switching signal SC, and the switching unit SWM is used to switch the integration direction of the integrating circuit 242. The switch signal SC can have two different signal values, which can be logic 1 or logic 0, or a signal whose signal value is A or -A. In addition, the switching signal SC may have a frequency fX+fI or a frequency fX-fI. The impedance unit 244 includes a resistor R. The integrating circuit 242 includes an amplifier Amp and an integrating capacitor CI. The integrating capacitor CI is coupled between a negative input terminal (labeled with a "-" sign) and an output terminal of the amplifier Amp. A positive input of the amplifier Amp (labeled with a "+" sign) receives a reference voltage VREF.

As shown in FIG. 3, analog down-convert circuit 34 is similar to analog down-convert circuit 24, so the same components follow the same symbols. Unlike the analog down converter circuit 24, the analog down frequency circuit 34 includes an impedance list. Element 344, the impedance unit 344 is a switched capacitor module, which includes a capacitor CS and switch switches SW1 SWSW4. The switch SW1 is coupled between a first end of the capacitor CS and the switching mixer 240; the switch SW2 is coupled between the first end of the capacitor CS and a ground; the switch SW3 is coupled to the capacitor CS The second end of the capacitor is coupled between the second end of the capacitor CS and the ground. The switches SW1 to SW4 can be controlled by the frequency control signals ph1, ph2, wherein the frequency control signals ph1, ph2 are mutually orthogonal frequency control signals (i.e., the times at which the frequency control signals ph1, ph2 are at a high potential do not overlap each other). Specifically, in an embodiment, the frequency control signal ph1 can be used to control the on state of the switches SW1, SW3, and the frequency control signal ph2 can be used to control the on state of the switches SW2, SW4; in another embodiment, The frequency control signal ph1 can be used to control the on state of the switches SW1, SW4, and the frequency control signal ph2 can be used to control the conduction state of the switches SW2, SW3. In addition, the frequency of the frequency control signals ph1, ph2 is greater than or equal to the frequency fI-, that is, the frequency of the frequency control signals ph1, ph2 is greater than or equal to fI-.

As shown in FIG. 4, the analog down converter circuit 44 includes an impedance unit 444A, an impedance unit 444B, a switching mixer 440, and an integration circuit 442. The switching mixer 440 has a first mixer input. a second mixed wave input terminal, a first mixed wave output terminal and a second mixed wave output terminal; the integrating circuit 442 has a first integral input terminal, a second integral input terminal, a first integral output terminal, and a first The second integrated output terminal, wherein the first mixed wave input end and the second mixed wave input end are used for receiving the analog high frequency signal AHF, and the first integrated output end and the second integrated output end are used for outputting the analog intermediate frequency signal AIF. In addition, the impedance unit 444A is coupled between the first mixed wave output end and the first integral input end, the impedance unit 444A includes a resistor RA, and the impedance unit 444B is coupled to the second mixed wave output end and the second integral input end. The impedance unit 444B includes a resistor RB. In detail, the switching type mixer 440 includes a mixing switch S1 to S4, and the mixing switch S1 is coupled between the first mixed wave input end and the first mixed wave output end; The mixing switch S2 is coupled between the second mixed wave input end and the second mixed wave output end; the mixed wave switch S3 is coupled between the first mixed wave input end and the second mixed wave output end; the mixed wave switch S4 The second hybrid input is coupled between the second mixed input and the first mixed output. The mixing switches S1 S S4 can be controlled by the frequency control signals ph1 ′, ph 2 ′, wherein the frequency control signals ph1 ′, ph 2 ′ are mutually orthogonal frequency control signals (ie, the frequency control signals ph1 ′, ph 2 ′ are high potential The times do not overlap each other), and the switching signals ph1', ph2' may have a frequency fX+fI or a frequency fX-fI. Specifically, in one embodiment, the frequency control signal ph1' can be used to control the conduction state of the switches S1, S2, and the frequency control signal ph2' can be used to control the conduction state of the switches S3, S4.

In addition, the integration circuit 442 includes a fully differential amplifier DAmp and integral capacitors CIA, CIB. A negative input terminal (labeled with a "-" sign) of the fully differential amplifier DAmp is coupled to the first integral input terminal, and a fully differential amplifier DAmp The positive input terminal (labeled with a "+" sign) is coupled to the second integral input terminal. A positive output terminal of the fully differential amplifier DAmp (labeled with a "+" sign) is coupled to the first integral output terminal, and the fully differential amplifier DAmp A negative output terminal (labeled with a "-" sign) is coupled to the second integral output terminal. The integrating capacitor CIA is coupled between the negative input terminal and the positive output terminal of the fully differential amplifier DAmp (ie, the integrating capacitor CIA is coupled between the first integral input terminal and the first integral output terminal); the integrating capacitor CIB is coupled to the entire The positive input terminal and the negative output end of the differential amplifier DAmp (ie, the integrating capacitor CIA is coupled between the second integral input terminal and the second integral output terminal).

As shown in FIG. 5, the analog down-conversion circuit 54 is similar to the analog down-conversion circuit 44, so the same components follow the same symbols. Unlike the analog down converter circuit 44, the analog down converter circuit 54 includes an impedance unit 544A and an impedance unit 544B. The circuit structure of the impedance unit 544A and the impedance unit 544B is the same as that of the impedance unit 344, and details are not described herein again.

In addition, the capacitance judging circuit 18 is not limited to being implemented with a specific circuit configuration. For example, please Referring to FIG. 6, FIG. 6 is a schematic diagram of a capacitance determining circuit 68 according to an embodiment of the present application. The capacitance determining circuit 68 can be used to implement the capacitance determining circuit 18. The capacitance judging circuit 68 includes multipliers MP1, MP2, a mode generator 680, a phase rotator 682,

digital integrators

684, 686, and a capacitance calculator 688. The capacitance judging circuit 68 can respectively perform digital signal integration on an In Phase Component and a Quadrature Component of the digital signal D to achieve a more accurate interpretation of the capacitance CUT to be measured. The details of the operation of the capacitance judging circuit 68 are well known to those of ordinary skill in the art and will not be described again.

It should be noted that the foregoing embodiments are used to explain the concept of the present application, and those skilled in the art can make various modifications, and are not limited thereto. For example, the impedance unit coupled between the switching mixer and the integrating circuit can include both the resistor and the switched capacitor module, and the connection between the resistor and the switched capacitor module in the impedance unit can be determined according to actual conditions. For example, please refer to FIG. 7 to FIG. 12 . FIG. 7 to FIG. 12 are respectively an analog frequency reduction circuit 74 , an analog frequency reduction circuit 84 , an analog frequency reduction circuit 94 , and a different embodiment of the present application. A schematic diagram of an analog down-conversion circuit A4, an analog down-conversion circuit B4, and an analog down-conversion circuit C4. Analog down-

conversion circuits

74, 84, 94, A4, B4, C4 can all be used to implement analog down-conversion circuit 14. The analog down-converting

circuits

74, 84, 94 are similar to the analog down-converting

circuits

24, 34, so the same components follow the same symbols. Unlike the analog down-converting

circuits

24, 34, the analog down-converting

circuits

74, 84, 94 respectively Each of the

impedance units

744, 844, and 944 includes a resistor R and a switched capacitor module, and the circuit structure of the switched capacitor module is the same as that of the impedance unit 344. The

impedance unit

744, 844, and 944 are different from each other in the connection relationship between the resistor R and the switched capacitor module. For example, in the impedance unit 744, the resistor R is coupled to the switch of the switched capacitor module. Between the SW3 and the integrating circuit 242; in the impedance unit 844, the resistor R is coupled to the switching mixer 240 and the switched capacitor module In the impedance unit 944, the resistor R is coupled between the switch SW1 and SW2 of the switched capacitor module and the capacitor CS.

Similarly, analog down-converters A4, B4, C4 are similar to analog down-converters 44, 54 so that the same components follow the same symbols. Different from the analog down-conversion circuits 44 and 54, the analog down-conversion circuits A4, B4, and C4 respectively include impedance units A44, B44, and C44, and each of the impedance units A44, B44, and C44 includes a resistor R and a The capacitor module is switched, wherein the circuit structure of the switched capacitor module is the same as the impedance unit 544A (or the impedance unit 544B). The impedance units A44, B44, and C44 are different from each other in the connection relationship between the resistor R and the switched capacitor module, and the manner of change is the same as that of the

impedance units

744, 844, and 944 with respect to the

impedance units

244, 344. Therefore, it will not be repeated here.

In summary, before entering the analog-to-digital converter, the present application uses an analog down-conversion circuit to down-convert the high-frequency analog high-frequency signal into an analog intermediate frequency signal with an intermediate frequency, so that the ratio converter can be reduced. The operating frequency reduces the amount of computation of the digital capacitance judging circuit. In addition, when the analog-to-digital converter utilizes the oversampling technique, the quantization noise can be further reduced to obtain a better resolution.

The above description is only a part of the embodiments of the present application, and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention. within.

Claims

A capacitance sensing circuit for sensing a capacitance to be tested of a circuit to be tested, the circuit to be tested receiving an analog transmission signal and outputting an analog receiving signal, the capacitance sensing circuit comprising:

An analog down-converting circuit coupled to the circuit to be tested for receiving an analog high frequency signal and generating an analog intermediate frequency signal, wherein the analog high frequency signal is related to the analog received signal;

An analog to digital converter for converting the analog intermediate frequency signal into a first digital signal;

a capacitance determining circuit coupled to the analog signal converter for determining a capacitance of the capacitor to be tested according to the first digital signal;

The analog high frequency signal has a first frequency, the analog intermediate frequency signal has a second frequency, and the first frequency is greater than the second frequency.
The capacitance sensing circuit of claim 1 wherein said analog downconverting circuit comprises:

a switching mixer for receiving the analog high frequency signal;

An integrating circuit for outputting the analog intermediate frequency signal.
The capacitive sensing circuit of claim 2 wherein said switched mixer comprises:

A forward buffer, including:

a forward input terminal for receiving the analog high frequency signal;

a forward output;

A negative buffer, including:

a negative input for receiving the analog high frequency signal;

a negative output;

a switching unit coupled to the forward output terminal and the negative output terminal, the switch unit being controlled by a switching signal, the switching unit outputting a mixed wave signal.
The capacitance sensing circuit of claim 2 wherein said integrating circuit comprises:

An amplifier;

A first integrating capacitor is coupled between a first input end and an output end of the amplifier.
The capacitance sensing circuit of claim 2, wherein the analog down converter circuit further comprises:

An impedance unit coupled between the switching mixer and the integrating circuit.
The capacitance sensing circuit of claim 5 wherein said impedance unit comprises a resistor.
The capacitance sensing circuit of claim 5, wherein the impedance unit comprises:

a capacitor comprising a first end and a second end;

a first switch is coupled between the first end of the capacitor and the switching mixer;

a second switch is coupled between the first end of the capacitor and a ground end;

a third switch coupled between the second end of the capacitor and the integrating circuit;

A fourth switch is coupled between the second end of the capacitor and the ground.
The capacitance sensing circuit of claim 2, wherein the switching mixer has a first mixed wave input terminal, a second mixed wave input terminal, a first mixed wave output terminal, and a second mixed wave The output circuit has a first integral input terminal, a second integral input terminal, a first integrated output terminal and a second integrated output terminal.
The capacitance sensing circuit of claim 8 wherein said switching mixer comprises:

a first mixing switch coupled between the first mixed wave input end and the first mixed wave output end;

a second mixing switch coupled between the second mixed wave input end and the second mixed wave output end;

a third mixing switch coupled between the first mixed wave input end and the second mixed wave output end;

A fourth mixing switch is coupled between the second mixed wave input end and the first mixed wave output end.
The capacitance sensing circuit of claim 8 wherein said integrating circuit comprises:

a fully differential amplifier coupled to the first integrating input, the second integrating input, the first integrating output, and the second integrating output;

a first integrating capacitor coupled between the first integrating input and the first integrated output;

A second integrating capacitor is coupled between the second integrating input and the second integrated output.
The capacitance sensing circuit of claim 8 wherein said analog down converter circuit further comprises:

a first impedance unit coupled between the first mixed wave output end and the first integral input end;

A second impedance unit is coupled between the second mixed wave output end and the second integrated input end.
The capacitance sensing circuit of claim 8, wherein the first impedance unit and the second impedance unit each comprise a resistor.
The capacitance sensing circuit of claim 8, wherein the first impedance unit and the second impedance unit each comprise:

a capacitor comprising a first end and a second end;

a first switch is coupled to the first end of the capacitor;

a second switch is coupled between the first end of the capacitor and a ground end;

a third switch coupled to the second end of the capacitor;

A fourth switch is coupled between the second end of the capacitor and the ground.
The capacitance sensing circuit of claim 8 further comprising:

An analog front end circuit coupled between the circuit under test and the analog down-converting circuit for receiving the analog received signal and generating the analog high frequency signal.
The capacitive sensing circuit of claim 1 wherein said analog transmit signal is generated by an active capacitive stylus.
The capacitance sensing circuit of claim 1 wherein a sampling frequency of said analog to digital converter is greater than twice said second frequency.
A touch control terminal includes a touch screen and a capacitance sensing circuit, wherein the capacitance sensing circuit is configured to detect a capacitance of at least one capacitor to be tested of the touch screen, and the capacitance sensing circuit adopts a claim The capacitance sensing circuit of any of 1-16.