CN105807205A - PLL automatic test circuit and test method - Google Patents
PLL automatic test circuit and test method Download PDFInfo
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- CN105807205A CN105807205A CN201610137635.5A CN201610137635A CN105807205A CN 105807205 A CN105807205 A CN 105807205A CN 201610137635 A CN201610137635 A CN 201610137635A CN 105807205 A CN105807205 A CN 105807205A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2882—Testing timing characteristics
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- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
The invention provides a PLL automatic test circuit, and the circuit comprises a frequency allocation memory unit, a frequency allocation unit, a pathway selection unit, a lock detection unit, a counter unit, a comparison unit and a desired value memory unit; the frequency allocation memory unit, the frequency allocation unit and the pathway selection unit are connected with the PLL in sequence, and the frequency allocation unit and the pathway selection unit are connected with a test mode effective state bit signal; the pathway selection unit is connected with an allocation control signal under a function mode; the lock detection unit, the PLL, the counter unit, the comparison unit and the desired value memory unit are connected in sequence; the lock detection unit is also connected with the counter unit and the comparison unit; and the PLL and the counter unit are connected with a reference clock signal. According to the invention, the circuit and method can perform a full spectrum band covering test on the PLL in chip CP test phase, can judge if the function of the PLL is correct through automatic calculation and can directly get the result.
Description
Technical field
The present invention relates to a kind of PLL automatic testing circuit and method of testing.
Background technology
The progressively expansion of SOC scale, the clock demand of SOC is also more and more higher, and the source of generation of clock is PLL (phaselocked loop) circuit in chip, therefore the quality of PLL circuit directly influences the normal operation of soc chip, if PLL can not work, then whole SOC can only be scrapped, and then uses the whole hardware system of soc chip all can collapse.Simultaneously because high performance PLL circuit is usually analog circuit, current method of testing is all directly after chip package, chip is allowed to start working, then pass through chip PLL signal observation pin to be observed, see whether PLL frequency and concussion characteristic meet expection, thus judging that can the PLL of chip normal operation.And the shortcoming of this method is also apparent from, it has been found that the time of problem, now chip had been completed encapsulation too late, if it find that problem chip rejection just wastes encapsulation overhead；Allow the whole working range that cannot cover PLL during chip normal operation simultaneously, cannot guarantee that PLL can normal operation in all working scope；Test result needs artificial observation, cannot be automatically performed.
Summary of the invention
The technical problem to be solved in the present invention, it is in that to provide a kind of PLL automatic testing circuit and method of testing, just PLL can be carried out at chip CP test phase the test of Whole frequency band covering, then pass through automatic computing to judge whether that PLL function is correct and directly gives test result.
The PLL automatic testing circuit of the present invention is achieved in that a kind of PLL automatic testing circuit, including frequency configuration memory cell, frequency dispensing unit, path selection unit, lock detection unit, counter unit, comparing unit and expected value memory element；Described frequency configuration memory cell, frequency dispensing unit, path selection unit are sequentially connected to PLL；And described frequency dispensing unit and path selection unit are all connected with test pattern effective status position signal；Described path selection unit is also connected with the configuration control signal under functional mode；Described lock detection unit, PLL, counter unit, comparing unit and expected value memory element are sequentially connected with；Described lock detection unit is additionally coupled to counter unit, comparing unit；Described PLL, counter unit are also connected with reference clock signal.
Further, described comparing unit is also connected with frequency dispensing unit.
Further, described test pattern effective status position signal and reference clock signal provide by tester table.
The PLL automatic test approach of the present invention is achieved in that a kind of PLL automatic test approach, adopts PLL automatic testing circuit of the present invention to test, and its test process is as follows:
(1), chip is when starting to test, and test pattern effective status position signal is set to effectively, then starts to pour into reference clock signal to PLL sum counter unit；
(2), described frequency dispensing unit receive test pattern effective status position signal and become after effectively, start to read the configuration of minimum PLL frequency from frequency configuration memory cell, be sent to path selection unit；The PLL frequency configuration of wherein said frequency configuration memory cell storage prestores in chip production process；
(3), path selection unit carry out path handover operation according to test pattern effective status position signal, the test pattern frequency configuration information of frequency dispensing unit is communicated to PLL；
(4), after PLL receives the configuration of minimum PLL frequency, start vibration and produce clock locking, and frequency lock is completed signal be sent to lock detection unit；
(5), lock detection unit become after effectively in locking signal PLL being detected, control counter unit and comparing unit are started working；
(6), counter unit use PLL stabilizing clock count, then the pll clock count value in a number of reference clock cycle is sent to comparing unit；
(7), the pll clock count value that comparing unit is sent here according to counter unit, if count value corresponding to the pll clock of respective amount reference clock cycle under this frequency in expected value memory element contrasts. error is within ± 1, then it is judged as that PLL can normal operation and frequency meet the requirements under this frequency, otherwise it is judged to that PLL frequency is inaccurate, then pass through the test that test result is sent and stopped this chip by test result holding wire, and chip is classified as PLL defect class；Described comparing unit, after comparing end, can control frequency dispensing unit and start the configuration flow of next Frequency point；
(8), described frequency dispensing unit receive comparing unit next Frequency point configure control after, from frequency configuration memory cell read higher one grade PLL frequency configuration, be sent to path selection unit；So circulation, until all preset Frequency points are all completed, if the test result of all Frequency points all meets expection, then the PLL circuit of this chip can be determined that as function correct.
Further, the configuration under functional mode is communicated to PLL by described path selection unit in the functional mode.
Further, described a number of reference clock cycle is 10 reference clock cycles.
Present invention have the advantage that
1. just PLL can being tested at chip CP test phase, after chip dispatches from the factory, stage the earliest pinpoints the problems, and makes waste be preferably minimized；Wherein, CP (ChipProbe) test refers to before chip not yet encapsulates, and in the stage of wafer, is just pricked by probe card and chip carries out on chip pin performance and functional test, and sometimes this procedure is also referred to as WS (WaferSort)；
2. the test that Whole frequency band covers, avoids a test coverage that part of detecting frequency causes incomplete；.
3. automatically computing judge test result, saves risk and the workload of artificial judgment.
Accompanying drawing explanation
The present invention is further illustrated in conjunction with the embodiments with reference to the accompanying drawings.
Fig. 1 is the FB(flow block) of PLL automatic testing circuit of the present invention.
Detailed description of the invention
As it is shown in figure 1, the PLL automatic testing circuit of the present invention includes frequency configuration memory cell 101, frequency dispensing unit 102, path selection unit 103, lock detection unit 104, counter unit 105, comparing unit 106 and expected value memory element 107；Described frequency configuration memory cell 101, frequency dispensing unit 102, path selection unit 103 are sequentially connected to PLL；And described frequency dispensing unit 102 and path selection unit 103 are all connected with test pattern effective status position signal；Described path selection unit 103 is also connected with the configuration control signal under functional mode；Described lock detection unit 104, PLL, counter unit 105, comparing unit 106 and expected value memory element 107 are sequentially connected with；Described lock detection unit 104 is additionally coupled to counter unit 105, comparing unit 106；Described PLL, counter unit 105 are also connected with reference clock signal；Described comparing unit 106 is also connected with frequency dispensing unit 102.
Described test pattern effective status position signal and reference clock signal provide by tester table.
The PLL automatic test approach of the present invention adopts PLL automatic testing circuit of the present invention to test, and its test process is as follows:
(1), chip is when starting to test, and test pattern effective status position signal is set to effectively, then starts to pour into reference clock signal to PLL sum counter unit 105；
(2), described frequency dispensing unit 102 receive test pattern effective status position signal and become after effectively, start to read the configuration of minimum PLL frequency from frequency configuration memory cell 101, be sent to path selection unit 103；The PLL frequency configuration of wherein said frequency configuration memory cell 101 storage prestores in chip production process；
(3), path selection unit 103 carry out path handover operation according to test pattern effective status position signal, the test pattern frequency configuration information of frequency dispensing unit 102 is communicated to PLL；
(4), after PLL receives the configuration of minimum PLL frequency, start vibration and produce clock locking, and frequency lock is completed signal be sent to lock detection unit 104；
(5), lock detection unit 104 become after effectively in locking signal PLL being detected, control counter unit 105 and comparing unit 106 are started working；
(6), counter unit 105 use the stabilizing clock of PLL to count, then the pll clock count value in a number of reference clock cycle is sent to comparing unit 106.
(7), the pll clock count value that comparing unit 106 is sent here according to counter unit 105, if count value corresponding to the pll clock of respective amount reference clock cycle under this frequency in expected value memory element 107 contrasts. error is within ± 1, then it is judged as that PLL can normal operation and frequency meet the requirements under this frequency, otherwise it is judged to that PLL frequency is inaccurate, then pass through the test that test result is sent and stopped this chip by test result holding wire, and chip is classified as PLL defect class；Described comparing unit 106, after comparing end, can control frequency dispensing unit 102 and start the configuration flow of next Frequency point；
(8), described frequency dispensing unit 102 receive comparing unit 106 next Frequency point configure control after, from frequency configuration memory cell 101 read higher one grade PLL frequency configuration, be sent to path selection unit 103；So circulation, until all preset Frequency points are all completed, if the test result of all Frequency points all meets expection, then the PLL circuit of this chip can be determined that as function correct.
Configuration under functional mode is communicated to PLL by described path selection unit 103 in the functional mode.
Although the foregoing describing the specific embodiment of the present invention; but those familiar with the art is to be understood that; we are merely exemplary described specific embodiment; rather than for the restriction to the scope of the present invention; those of ordinary skill in the art, in the equivalent modification made according to the spirit of the present invention and change, should be encompassed in the scope of the claimed protection of the present invention.
Claims (6)
1. a PLL automatic testing circuit, it is characterised in that: include frequency configuration memory cell, frequency dispensing unit, path selection unit, lock detection unit, counter unit, comparing unit and expected value memory element；
Described frequency configuration memory cell, frequency dispensing unit, path selection unit are sequentially connected to PLL；And described frequency dispensing unit and path selection unit are all connected with test pattern effective status position signal；Described path selection unit is also connected with the configuration control signal under functional mode；
Described lock detection unit, PLL, counter unit, comparing unit and expected value memory element are sequentially connected with；Described lock detection unit is additionally coupled to counter unit, comparing unit；Described PLL, counter unit are also connected with reference clock signal.
2. PLL automatic testing circuit according to claim 1, it is characterised in that: described comparing unit is also connected with frequency dispensing unit.
3. PLL automatic testing circuit according to claim 1, it is characterised in that: described test pattern effective status position signal and reference clock signal provide by tester table.
4. a PLL automatic test approach, it is characterised in that: adopting the PLL automatic testing circuit described in claim 1 to test, its test process is as follows:
(1), chip is when starting to test, and test pattern effective status position signal is set to effectively, then starts to pour into reference clock signal to PLL sum counter unit；
(2), described frequency dispensing unit receive test pattern effective status position signal and become after effectively, start to read the configuration of minimum PLL frequency from frequency configuration memory cell, be sent to path selection unit；The PLL frequency configuration of wherein said frequency configuration memory cell storage prestores in chip production process；
(3), path selection unit carry out path handover operation according to test pattern effective status position signal, the test pattern frequency configuration information of frequency dispensing unit is communicated to PLL；
(4), after PLL receives the configuration of minimum PLL frequency, start vibration and produce clock locking, and frequency lock is completed signal be sent to lock detection unit；
(5), lock detection unit become after effectively in locking signal PLL being detected, control counter unit and comparing unit are started working；
(6), counter unit use PLL stabilizing clock count, then the pll clock count value in a number of reference clock cycle is sent to comparing unit；
(7), the pll clock count value that comparing unit is sent here according to counter unit, if count value corresponding to the pll clock of respective amount reference clock cycle under this frequency in expected value memory element contrasts. error is within ± 1, then it is judged as that PLL can normal operation and frequency meet the requirements under this frequency, otherwise it is judged to that PLL frequency is inaccurate, then pass through the test that test result is sent and stopped this chip by test result holding wire, and chip is classified as PLL defect class；Described comparing unit, after comparing end, can control frequency dispensing unit and start the configuration flow of next Frequency point；
(8), described frequency dispensing unit receive comparing unit next Frequency point configure control after, from frequency configuration memory cell read higher one grade PLL frequency configuration, be sent to path selection unit；So circulation, until all preset Frequency points are all completed, if the test result of all Frequency points all meets expection, then the PLL circuit of this chip can be determined that as function correct.
5. PLL automatic test approach according to claim 4, it is characterised in that: the configuration under functional mode is communicated to PLL by described path selection unit in the functional mode.
6. PLL automatic test approach according to claim 4, it is characterised in that: described a number of reference clock cycle is 10 reference clock cycles.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610137635.5A CN105807205B (en) | 2016-03-11 | 2016-03-11 | PLL automatic testing circuits and test method |
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| CN201610137635.5A CN105807205B (en) | 2016-03-11 | 2016-03-11 | PLL automatic testing circuits and test method |
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| CN105807205A true CN105807205A (en) | 2016-07-27 |
| CN105807205B CN105807205B (en) | 2018-07-03 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107991600A (en) * | 2017-11-29 | 2018-05-04 | 成都锐成芯微科技股份有限公司 | Automatic test approach and its test system |
| CN108693465A (en) * | 2018-03-30 | 2018-10-23 | 北京联想核芯科技有限公司 | A kind of test control method, circuit and system |
| CN109361378A (en) * | 2018-09-25 | 2019-02-19 | 福州瑞芯微电子股份有限公司 | The verification platform and verification method of SOC chip asynchronous clock |
| CN110855978A (en) * | 2019-10-30 | 2020-02-28 | 晶晨半导体（深圳）有限公司 | Method for testing PLL (phase locked loop) stability of HDMI (high-definition multimedia interface) through SOC (system on chip) |
| CN113129991A (en) * | 2021-04-01 | 2021-07-16 | 深圳市纽创信安科技开发有限公司 | Chip safety protection method and circuit for ROMBIST test |
| CN113190389A (en) * | 2021-04-14 | 2021-07-30 | 西安紫光国芯半导体有限公司 | Self-test method, test apparatus, and computer-readable storage medium |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107991600A (en) * | 2017-11-29 | 2018-05-04 | 成都锐成芯微科技股份有限公司 | Automatic test approach and its test system |
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| CN109361378B (en) * | 2018-09-25 | 2022-05-24 | 瑞芯微电子股份有限公司 | Verification platform and verification method for asynchronous clock of SOC (System on chip) |
| CN110855978A (en) * | 2019-10-30 | 2020-02-28 | 晶晨半导体（深圳）有限公司 | Method for testing PLL (phase locked loop) stability of HDMI (high-definition multimedia interface) through SOC (system on chip) |
| CN113129991A (en) * | 2021-04-01 | 2021-07-16 | 深圳市纽创信安科技开发有限公司 | Chip safety protection method and circuit for ROMBIST test |
| CN113190389A (en) * | 2021-04-14 | 2021-07-30 | 西安紫光国芯半导体有限公司 | Self-test method, test apparatus, and computer-readable storage medium |
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| CN105807205B (en) | 2018-07-03 |
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Address after: 350000 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee after: Ruixin Microelectronics Co., Ltd Address before: 350000 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee before: Fuzhou Rockchips Electronics Co.,Ltd. |