CN105807205B - PLL automatic testing circuits and test method - Google Patents
PLL automatic testing circuits and test method Download PDFInfo
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- CN105807205B CN105807205B CN201610137635.5A CN201610137635A CN105807205B CN 105807205 B CN105807205 B CN 105807205B CN 201610137635 A CN201610137635 A CN 201610137635A CN 105807205 B CN105807205 B CN 105807205B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2882—Testing timing characteristics
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- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The present invention provides a kind of PLL automatic testing circuits and includes frequency configuration storage unit, frequency configuration unit, path selection unit, lock detection unit, counter unit, comparing unit and desired value storage unit；The frequency configuration storage unit, frequency configuration unit, path selection unit are sequentially connected to PLL；And the frequency configuration unit and path selection unit are all connected with test pattern effective status position signal；The path selection unit is also connected with the configuration control signal under functional mode；The lock detection unit, PLL, counter unit, comparing unit and desired value storage unit are sequentially connected；The lock detection unit is additionally coupled to counter unit, comparing unit；The PLL, counter unit are also connected with reference clock signal.The present invention just can carry out PLL in chip CP test phases the test of Whole frequency band covering, then by automatic operation to determine whether PLL functions are correct and directly give test result.
Description
Technical field
The present invention relates to a kind of PLL automatic testing circuits and test methods.
Background technology
The gradually expansion of SOC chip scale, the clock demand of SOC chip is also higher and higher, and in chip clock generation
Source is PLL (phaselocked loop) circuit, therefore the quality of PLL circuit directly influences the normal work of soc chips, if PLL is not
It can work, then entire SOC chip can only scrap, and then can all be collapsed using the entire hardware system of soc chips.It is simultaneously because high
The PLL circuit of performance is typically analog circuit, and current test method is all directly after chip package, and chip is allowed to start
Then work is observed pin by chip PLL signals and is observed, see whether PLL frequencies and concussion characteristic meet expection, so as to
Can the PLL that judge chip work normally.And the shortcomings that this method, is also apparent from, the time pinpointed the problems too late, core at this time
Piece has been completed encapsulation, if it find that problem chip rejection just wastes encapsulation overhead；When allowing the chip to work normally simultaneously without
Method covers the entire working range of PLL, can not ensure that PLL can be worked normally in all working range；Test result needs people
Work is observed, and can not be automatically performed.
Invention content
The technical problem to be solved in the present invention is to provide a kind of PLL automatic test approach, can test rank in chip CP
Section just to PLL carry out Whole frequency band covering test, then by automatic operation to determine whether PLL functions correctly and directly give
Test result.
What the PLL automatic test approach of the present invention was realized in：A kind of PLL automatic test approach is surveyed automatically using PLL
Examination circuit is tested, which includes frequency configuration storage unit, frequency configuration unit, access selection list
Member, lock detection unit, counter unit, comparing unit and desired value storage unit；The frequency configuration storage unit, frequency
Rate dispensing unit, path selection unit are sequentially connected to PLL；And the frequency configuration unit and path selection unit are all connected with surveying
Die trial formula effective status position signal；The path selection unit is also connected with the configuration control signal under functional mode；The PLL,
Counter unit, comparing unit and desired value storage unit are sequentially connected, and the output of the PLL is connected to lock detection unit
Input, the output of the desired value storage unit is connected to the input of comparing unit；The lock detection unit is additionally coupled to
Counter unit, comparing unit；The PLL, counter unit are also connected with reference clock signal；
Its test process is as follows：
(1), when chip starts test, test pattern effective status position signal is set as effective, then starts to pour into reference
Clock signal is to PLL and counter unit；
(2), the frequency configuration unit receive test pattern effective status position signal become effectively after, start to match from frequency
It puts storage unit and reads minimum PLL frequency configurations, be sent to path selection unit；Wherein described frequency configuration storage unit is deposited
The PLL frequency configurations of storage are pre-stored during chip production；
(3), path selection unit carries out access handover operation according to test pattern effective status position signal, by frequency configuration
The test pattern frequency configuration information of unit is communicated to PLL；
(4), after PLL receives minimum PLL frequency configurations, start oscillation and generate clock and lock, and Frequency Locking is completed
Signal is sent to lock detection unit；
(5), lock detection unit control counter unit and compares after the locking signal for detecting PLL becomes effectively
Unit is started to work；
(6), counter unit is counted using the stabilizing clock of PLL, then will be in a certain number of reference clocks week
Pll clock count value in phase is sent to comparing unit；
(7), the pll clock count value that comparing unit is sent according to counter unit, with being somebody's turn to do in desired value storage unit
If it is within ± 1 that the pll clock of corresponding number reference clock cycle, which corresponds to count value and carries out comparison errors, under frequency, then sentence
Breaking can work normally and frequency meets the requirements for PLL under the frequency, be otherwise determined as PLL frequencies inaccuracy, then pass through
Test result is sent out and stops the test of the chip by test result signal wire, and chip is classified as PLL defect classes；The comparison
Unit can control frequency configuration unit to start the configuration flow of next Frequency point after comparison；
(8), the frequency configuration unit is deposited after the next Frequency point configuration control for receiving comparing unit from frequency configuration
Storage unit reads the PLL frequency configurations of one grade of higher, is sent to path selection unit；So cycle, until all preset
Frequency point is all completed, if the test result of all Frequency points all meets expection, the PLL circuit of the chip can be determined that
It is correct for function.
Further, the configuration under functional mode is communicated to PLL by the path selection unit in the functional mode.
Further, a certain number of reference clock cycles are 10 reference clock cycles.
The invention has the advantages that：
1. can just be tested in chip CP test phases PLL, after chip manufacture the earliest stage pinpoint the problems,
It is preferably minimized waste；Wherein, before CP (Chip Probe) tests refer to that chip not yet encapsulates, in the stage of wafer, just lead to
It crosses probe card and pricks and performance and functional test are carried out to chip on chip pin, sometimes this procedure is also referred to as WS (Wafer
Sort)；
2. the test of Whole frequency band covering, it is incomplete to avoid a test coverage caused by part of detecting frequency point；.
3. automatic operation simultaneously judges test result, the risk and workload of artificial judgment are saved.
Description of the drawings
The present invention is further illustrated in conjunction with the embodiments with reference to the accompanying drawings.
Fig. 1 is the flow diagram of PLL automatic testing circuits of the present invention.
Specific embodiment
As shown in Figure 1, the PLL automatic testing circuits of the present invention include frequency configuration storage unit 101, frequency configuration unit
102nd, path selection unit 103, lock detection unit 104, counter unit 105, comparing unit 106 and desired value storage are single
Member 107；The frequency configuration storage unit 101, frequency configuration unit 102, path selection unit 103 are sequentially connected to PLL；And
The frequency configuration unit 102 and path selection unit 103 are all connected with test pattern effective status position signal；The access selection
Unit 103 is also connected with the configuration control signal under functional mode；The PLL, counter unit 105, comparing unit 106 and phase
Prestige value storage unit 107 is sequentially connected；The output of the PLL is connected to the input of lock detection unit 104, and the desired value is deposited
The output of storage unit 107 is connected to the input of comparing unit 106；The lock detection unit 104 is additionally coupled to counter unit
105th, comparing unit 106；The PLL, counter unit 105 are also connected with reference clock signal；The comparing unit 106 also with frequency
Rate dispensing unit 102 connects.
The test pattern effective status position signal and reference clock signal are provided by tester table.
The PLL automatic test approach of the present invention is tested using PLL automatic testing circuits of the present invention, is tested
Process is as follows：
(1), when chip starts test, test pattern effective status position signal is set as effective, then starts to pour into reference
Clock signal is to PLL and counter unit 105；
(2), the frequency configuration unit 102 receive test pattern effective status position signal become effectively after, start from frequency
Rate configuration memory cell 101 reads minimum PLL frequency configurations, is sent to path selection unit 103；Wherein described frequency configuration
The PLL frequency configurations that storage unit 101 stores are pre-stored during chip production；
(3), path selection unit 103 carries out access handover operation according to test pattern effective status position signal, by frequency
The test pattern frequency configuration information of dispensing unit 102 is communicated to PLL；
(4), after PLL receives minimum PLL frequency configurations, start oscillation and generate clock and lock, and Frequency Locking is completed
Signal is sent to lock detection unit 104；
(5), lock detection unit 104 is after the locking signal for detecting PLL becomes effectively, control counter unit 105
It starts to work with comparing unit 106；
(6), counter unit 105 is counted using the stabilizing clock of PLL, then will be in a certain number of reference clocks
Pll clock count value in period is sent to comparing unit 106.
(7), the pll clock count value that comparing unit 106 is sent according to counter unit 105, with desired value storage unit
It is ± 1 that if the pll clock of corresponding number reference clock cycle, which corresponds to count value and carries out comparison errors, under the frequency in 107
Within, then it is judged as that PLL can be worked normally under the frequency and frequency meets the requirements, is otherwise determined as PLL frequencies inaccuracy,
Then test result by test result signal wire is sent out to and stopped the test of the chip, and chip is classified as PLL defect classes；
The comparing unit 106 can control frequency configuration unit 102 to start the configuration flow of next Frequency point after comparison；
(8), the frequency configuration unit 102 is after the next Frequency point configuration control for receiving comparing unit 106, from frequency
Configuration memory cell 101 reads the PLL frequency configurations of one grade of higher, is sent to path selection unit 103；So cycle, directly
It is all completed to all preset Frequency points, if the test result of all Frequency points all meets expection, the PLL of the chip
Circuit can be determined that correct for function.
Configuration under functional mode is communicated to PLL by the path selection unit 103 in the functional mode.
Although specific embodiments of the present invention have been described above, those familiar with the art should manage
Solution, our described specific embodiments are merely exemplary rather than for the restriction to the scope of the present invention, are familiar with this
The equivalent modification and variation that the technical staff in field is made in the spirit according to the present invention, should all cover the present invention's
In scope of the claimed protection.
Claims (3)
1. a kind of PLL automatic test approach, it is characterised in that：It is tested using PLL automatic testing circuits, which surveys automatically
Try circuit include frequency configuration storage unit, frequency configuration unit, path selection unit, lock detection unit, counter unit,
Comparing unit and desired value storage unit；
The frequency configuration storage unit, frequency configuration unit, path selection unit are sequentially connected to PLL；And the frequency is matched
It puts unit and path selection unit is all connected with test pattern effective status position signal；The path selection unit is also connected with function mould
Configuration control signal under formula；
The PLL, counter unit, comparing unit and desired value storage unit are sequentially connected, and the output of the PLL is connected to
The input of lock detection unit, the output of the desired value storage unit are connected to the input of comparing unit；The lock-in detection
Unit is additionally coupled to counter unit, comparing unit；The PLL, counter unit are also connected with reference clock signal；
Its test process is as follows：
(1), when chip starts test, test pattern effective status position signal is set as effective, then starts to pour into reference clock
Signal is to PLL and counter unit；
(2), the frequency configuration unit receive test pattern effective status position signal become effectively after, start to deposit from frequency configuration
Storage unit reads minimum PLL frequency configurations, is sent to path selection unit；Wherein described frequency configuration storage unit storage
PLL frequency configurations are pre-stored during chip production；
(3), path selection unit carries out access handover operation according to test pattern effective status position signal, by frequency configuration unit
Test pattern frequency configuration information be communicated to PLL；
(4), after PLL receives minimum PLL frequency configurations, start oscillation and generate clock and lock, and Frequency Locking is completed into signal
It is sent to lock detection unit；
(5), lock detection unit is after the locking signal for detecting PLL becomes effectively, control counter unit and comparing unit
It starts to work；
(6), counter unit is counted using the stabilizing clock of PLL, then will be in a certain number of reference clock cycles
Pll clock count value be sent to comparing unit；
(7), the pll clock count value that comparing unit is sent according to counter unit, with the frequency in desired value storage unit
The pll clock of lower corresponding number reference clock cycle corresponds to count value and is compared, if error is within ± 1, is judged as
PLL can be worked normally under the frequency and frequency meets the requirements, and is otherwise determined as PLL frequencies inaccuracy, then passes through test
Test result is sent out and stops the test of the chip by consequential signal line, and chip is classified as PLL defect classes；The comparing unit
After comparison, frequency configuration unit can be controlled to start the configuration flow of next Frequency point；
(8), the frequency configuration unit stores single after the next Frequency point configuration control for receiving comparing unit from frequency configuration
Member reads the PLL frequency configurations of one grade of higher, is sent to path selection unit；So cycle, until all preset frequencies
Point is all completed, if the test result of all Frequency points all meets expection, the PLL circuit of the chip can be determined that as work(
It can be correct.
2. PLL automatic test approach according to claim 1, it is characterised in that：The path selection unit is in function mould
The configuration under functional mode is communicated to PLL under formula.
3. PLL automatic test approach according to claim 1, it is characterised in that：A certain number of reference clock weeks
Phase is 10 reference clock cycles.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201610137635.5A CN105807205B (en) | 2016-03-11 | 2016-03-11 | PLL automatic testing circuits and test method |
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| CN201610137635.5A CN105807205B (en) | 2016-03-11 | 2016-03-11 | PLL automatic testing circuits and test method |
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| CN105807205A CN105807205A (en) | 2016-07-27 |
| CN105807205B true CN105807205B (en) | 2018-07-03 |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107991600A (en) * | 2017-11-29 | 2018-05-04 | 成都锐成芯微科技股份有限公司 | Automatic test approach and its test system |
| CN108693465A (en) * | 2018-03-30 | 2018-10-23 | 北京联想核芯科技有限公司 | A kind of test control method, circuit and system |
| CN109361378B (en) * | 2018-09-25 | 2022-05-24 | 瑞芯微电子股份有限公司 | Verification platform and verification method for asynchronous clock of SOC (System on chip) |
| CN110855978B (en) * | 2019-10-30 | 2021-12-21 | 晶晨半导体（深圳）有限公司 | Method for testing PLL (phase locked loop) stability of HDMI (high-definition multimedia interface) through SOC (system on chip) |
| CN113129991B (en) * | 2021-04-01 | 2023-04-07 | 深圳市纽创信安科技开发有限公司 | Chip safety protection method and circuit for ROMBIST test |
| CN113190389A (en) * | 2021-04-14 | 2021-07-30 | 西安紫光国芯半导体有限公司 | Self-test method, test apparatus, and computer-readable storage medium |
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| US5381085A (en) * | 1993-07-06 | 1995-01-10 | Motorola, Inc. | Phase lock loop with self test circuitry and method for using the same |
| CN102571079A (en) * | 2010-12-27 | 2012-07-11 | 北京国睿中数科技股份有限公司 | ATE (Automatic Test Equipment) test circuit for PLL (Phase Locked Loop) and test method thereof |
| CN102868399A (en) * | 2012-10-11 | 2013-01-09 | 广州润芯信息技术有限公司 | Phase-locked loop frequency synthesizer and phase-locked loop loss lock detecting and adjusting method |
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| JP4492907B2 (en) * | 2001-03-29 | 2010-06-30 | ルネサスエレクトロニクス株式会社 | PLL circuit, lock determination circuit thereof, and test method and apparatus |
| JP2007017158A (en) * | 2005-07-05 | 2007-01-25 | Sharp Corp | Test circuit, delay circuit, clock generating circuit, and image sensor |
| US20140225635A1 (en) * | 2013-02-11 | 2014-08-14 | Qualcomm Incorporated | All-digital phase locked loop self test system |
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| US5381085A (en) * | 1993-07-06 | 1995-01-10 | Motorola, Inc. | Phase lock loop with self test circuitry and method for using the same |
| CN102571079A (en) * | 2010-12-27 | 2012-07-11 | 北京国睿中数科技股份有限公司 | ATE (Automatic Test Equipment) test circuit for PLL (Phase Locked Loop) and test method thereof |
| CN102868399A (en) * | 2012-10-11 | 2013-01-09 | 广州润芯信息技术有限公司 | Phase-locked loop frequency synthesizer and phase-locked loop loss lock detecting and adjusting method |
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Address after: 350000 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee after: Ruixin Microelectronics Co., Ltd Address before: 350000 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee before: Fuzhou Rockchips Electronics Co.,Ltd. |
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