CN113190389A

CN113190389A - Self-test method, test apparatus, and computer-readable storage medium

Info

Publication number: CN113190389A
Application number: CN202110400249.1A
Authority: CN
Inventors: 邱锋波; 左丰国; 王玉冰
Original assignee: Xian Unilc Semiconductors Co Ltd
Current assignee: Xian Unilc Semiconductors Co Ltd
Priority date: 2021-04-14
Filing date: 2021-04-14
Publication date: 2021-07-30

Abstract

The application discloses a self-test method, a test device and a computer readable storage medium. The self-testing method comprises the following steps: controlling the special integrated chip to switch to a self-test mode through a first logic signal, and starting a clock phase-locked loop of the special integrated chip; controlling the clock phase-locked loop of the special integrated chip to operate through a reference clock signal, and acquiring the state of the clock phase-locked loop; and responding to the locked state of the clock phase-locked loop, and performing writing and reading operations on each storage unit to obtain a test result. By the method, a large amount of additional logic and wiring resources are not needed, and the test cost is reduced.

Description

Self-test method, test apparatus, and computer-readable storage medium

Technical Field

The present application relates to the field of electronic technologies, and in particular, to a self-test method, a test apparatus, and a computer-readable storage medium.

Background

An Application Specific Integrated Circuit (ASIC) is an Integrated Circuit designed for a Specific purpose, specifically designed and manufactured according to the requirements of a Specific user and the needs of a Specific electronic system. The special integrated chip is characterized by facing the requirements of specific users, and compared with a general integrated circuit, the special integrated chip has the advantages of smaller volume, lower power consumption, improved reliability, improved performance, enhanced confidentiality, reduced cost and the like during batch production.

Among them, the application of the large data multi-channel parallel processing asic based on the high bandwidth storage architecture is becoming more and more widespread, for example, the asic integrates a Processing Element (PE) of thousands of multi-channel processing units, and is applied to parallel mining.

Since the output of the asic is very large, the asic needs to be screened to improve the yield of the asic. Currently, an asic is tested by ATPG (Automatic Test Pattern Generation), but the ATPG Test requires a lot of additional logic and wiring resources, resulting in high Test cost.

Disclosure of Invention

The application provides a self-testing method, a testing device and a computer readable storage medium, which aim to solve the technical problem of high testing cost.

In order to solve the technical problem, the application adopts a technical scheme that: a self-test method is provided. The self-testing method is used for testing an application specific integrated chip, the application specific integrated chip is provided with a plurality of storage units, and the self-testing method comprises the following steps:

controlling the special integrated chip to switch to a self-test mode through a first logic signal, and starting a clock phase-locked loop of the special integrated chip;

controlling the clock phase-locked loop of the special integrated chip to operate through a reference clock signal, and acquiring the state of the clock phase-locked loop;

and responding to the locked state of the clock phase-locked loop, and performing writing and reading operations on each storage unit to obtain a test result.

Wherein the operations of writing and reading to and from each of the memory cells comprise:

writing preset data into each storage unit;

reading first data from each of the memory cells;

comparing the first data with the corresponding preset data to obtain a comparison result;

obtaining a first comparison result in response to the first data being the same as the corresponding preset data;

and obtaining a second comparison result in response to the first data being different from the corresponding preset data.

Wherein the obtaining of the test result comprises:

receiving a plurality of output signals obtained based on the comparison results of all the storage units, and judging whether the plurality of output signals are all 1;

responding to the plurality of output signals to be 1, and obtaining that the test of the special integrated chip is successful;

and responding to at least one output signal not being 1, and obtaining that the test of the application specific integrated chip fails.

Wherein the plurality of output signals obtained based on the comparison results of all of the memory cells includes:

in response to the comparison results of all the memory cells being the first comparison result, obtaining that the plurality of output signals are all 1;

and responding to the comparison result of at least one memory cell as the second comparison result, and obtaining that the corresponding output signal is not 1.

Wherein, the ASIC is provided with a plurality of first pins, and the ASIC is controlled to switch to a self-test mode by a first logic signal, including:

inputting the first logic signal to the plurality of first pins;

and responding to all the first logic signals to be at a first level, and controlling the application specific integrated chip to be switched to the self-test mode.

Wherein, the asic further includes a plurality of logic core units and a plurality of network-on-chip units, each of the memory units and each of the logic core units are respectively connected to the corresponding network-on-chip units, and after the step of starting the clock phase-locked loop of the asic, the self-test method further includes:

judging whether to test all the logic core units based on a second logic signal;

responding to the second logic signal as a first level, testing all the logic core units, and executing the step of controlling the clock phase-locked loop of the special integrated chip to operate through a reference clock signal;

and responding to the second logic signal as a second level, executing the step of controlling the operation of the clock phase-locked loop of the application-specific integrated chip through the reference clock signal.

Wherein, the asic is provided with a plurality of second pins, and the determining whether to test the logic core unit of the asic by a second logic signal includes:

waiting for a first preset time, and inputting the second logic signals to the plurality of second pins;

after the step of controlling the operation of the clock phase locked loop of the asic by the reference clock signal, the self-test method further includes:

counting the test time, and comparing the test time with preset time;

and responding to the test time which is more than or equal to the preset time, acquiring a plurality of output signals, resetting the test time, and executing the step of obtaining the test result.

In order to solve the above technical problem, another technical solution adopted by the present application is: a test apparatus is provided. The testing device is provided with an application specific integrated chip, the application specific integrated chip comprises a plurality of logic core units, a plurality of network-on-chip units, a plurality of storage units and a plurality of first pins, each logic core unit and each storage unit are respectively connected with the corresponding network-on-chip unit, the network-on-chip units in each row are correspondingly provided with two first pins, the testing device is used for testing the application specific integrated chip through the plurality of first pins, and the testing device comprises a processor and a memory; the memory stores a computer program, and the processor is used for executing the computer program to realize the self-test method.

In order to solve the above technical problem, another technical solution adopted by the present application is: a computer-readable storage medium is provided. The computer readable storage medium stores program instructions that can be executed to implement the self-test method described above.

The self-test method comprises the following steps: controlling the special integrated chip to switch to a self-test mode through a first logic signal, and starting a clock phase-locked loop of the special integrated chip; controlling the clock phase-locked loop of the special integrated chip to operate through a reference clock signal, and acquiring the state of the clock phase-locked loop; and responding to the locked state of the clock phase-locked loop, and performing writing and reading operations on each storage unit to obtain a test result. The method comprises the steps that a first logic signal is input into an application-specific integrated chip, a reference clock signal is input into the application-specific integrated chip, and in response to the fact that a clock phase-locked loop is in a locked state, writing and reading operations are conducted on each storage unit to obtain a test result; therefore, a large amount of additional logic and wiring resources are not needed, and the test cost is reduced; in addition, the pins of the special integrated chip are multiplexed, so that the pins of the special integrated chip are not required to be added, and the test cost is further reduced.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

FIG. 1 is a schematic flow chart diagram illustrating an embodiment of a self-test method of the present application;

FIG. 2 is a block diagram of an ASIC and a test apparatus according to the present application;

FIG. 3 is a schematic flow chart of one embodiment of step S103 in FIG. 1;

FIG. 4 is a flowchart illustrating an embodiment of step S304 in FIG. 3;

FIG. 5 is a schematic diagram of an embodiment of the application specific integrated chip of FIG. 2;

FIG. 6 is a schematic flow chart diagram illustrating another embodiment of a self-test method of the present application;

FIG. 7 is a flowchart illustrating an embodiment of step S503 in FIG. 6;

FIG. 8 is a block diagram of an embodiment of the test apparatus of the present application;

FIG. 9 is a schematic structural diagram of an embodiment of a computer-readable storage medium of the present application.

Detailed Description

The present application will be described in further detail with reference to the following drawings and examples. It is to be noted that the following examples are only illustrative of the present application, and do not limit the scope of the present application. Likewise, the following examples are only some examples and not all examples of the present application, and all other examples obtained by a person of ordinary skill in the art without any inventive step are within the scope of the present application.

Referring to fig. 1-2, fig. 1 is a schematic flow chart of an embodiment of a self-test method of the present application;

FIG. 2 is a block diagram of an ASIC and a test apparatus according to the present invention. The self-test method of the present application is used for testing the application specific integrated chip 20 (i.e. the application specific integrated chip 20 to be tested), i.e. the testing device 10 tests the application specific integrated chip 20 by the self-test method of the present application.

As shown in fig. 2, the test apparatus 10 is provided with an application specific integrated chip 20 for testing the application specific integrated chip 20. For example, the testing apparatus 10 is provided with a testing platform, and the application specific integrated chip 20 is provided on the testing platform.

The application specific integrated chip 20 is provided with a plurality of first pins 21, a plurality of second pins 22, a clock pin 23 and a plurality of output pins 24, wherein the application specific integrated chip 20 is connected with the testing device 10, for example, the plurality of first pins 21 and the clock pin 23 of the application specific integrated chip 20 are connected with the testing device 10. Optionally, the total number of the first pins 21 is equal to the total number of the second pins 22.

As shown in fig. 1, the self-test method of the present embodiment includes the following steps:

s101: the ASIC 20 is controlled by the first logic signal to switch to the self-test mode and the clock PLL of the ASIC 20 is enabled.

When the test apparatus 10 tests the application specific integrated chip 20, the test apparatus 10 is powered on to operate the test apparatus 10 normally. When the testing apparatus 10 works normally, the testing apparatus 10 generates a first logic signal, and controls the asic 20 to switch to the self-test mode through the first logic signal. For example, the testing apparatus 10 may input a first logic signal to the first pin 21 of the asic 20, and the asic 20 switches to a self-test mode (also referred to as a test mode or a detection mode) based on the first logic signal, so as to control the asic 20 to switch to the self-test mode through the first logic signal. In other embodiments, the test apparatus 10 may receive a test command and generate the first logic signal based on the test command.

The asic 20 is further provided with a clock Phase-Locked Loop (PLL), which may also be referred to as a Phase-Locked Loop, for integrating clock signals to enable the high-frequency device to work normally. For example, the clock phase-locked loop may continually adjust the clock phase of the local oscillator according to the phase of the external signal until the phases of the two signals are synchronized.

Alternatively, the test apparatus 10 may input a first logic signal to the plurality of first pins 21, wherein the first logic signal includes a first level (high level) and a second level (low level). The testing apparatus 10 controls the asic 20 to switch to the self-test mode in response to the first pins 21 receiving all the first logic signals at the first level.

Further, when the asic 20 switches to the self-test mode, the clock pll of the asic 20 is started, i.e. the asic 20 controls the clock pll to start based on the first logic signal.

S102: the clock phase-locked loop of the application specific integrated chip 20 is controlled to operate by the reference clock signal, and the state of the clock phase-locked loop is obtained.

The test device 10 controls the clock phase-locked loop of the asic 20 to operate by referring to the clock signal, and obtains the state of the clock phase-locked loop. For example, after the test apparatus 10 inputs the first logic signal to the first pin 21 of the asic 20, the test apparatus 10 waits for a third preset time, the test apparatus 10 inputs the reference clock signal to the clock pin 23 of the asic 20, and the clock pll operates based on the reference clock signal.

The test apparatus 10 obtains the state of the clock pll, i.e. the test apparatus 10 can query the state of the clock pll internally through the asic 20. The testing device 10 further determines whether the state of the clock phase-locked loop is locked; if the test apparatus 10 determines that the state of the clock pll is the locked state, step S103 is performed; if the test device 10 determines that the state of the clock pll is not locked, the method returns to the step of determining whether the state of the clock pll is locked by the test device 10.

For example, the test apparatus 10 acquires the state of the clock phase-locked loop, that is, the PLL lock (PLL lock signal), from the asic 20, and determines whether the PLL lock is 1; if yes, the clock phase-locked loop of the asic 20 locks and stably outputs, and the process goes to step S103; if not, returning to the step of judging whether the PLL lock is 1 or not.

S103: and responding to the locked state of the clock phase-locked loop, and performing writing and reading operations on each storage unit to obtain a test result.

In response to the clock phase locked loop being in a locked state, the test apparatus 10 performs writing and reading operations on each memory cell. The asic 20 is provided with a plurality of memory cells, and the test apparatus 10 performs writing and reading operations on each memory cell to implement that the test apparatus 10 performs writing and reading operations on all memory cells to implement that all memory cells are tested. The test apparatus 10 obtains test results including test success and test failure based on the operations of writing and reading to and from all the memory cells.

In the embodiment, the testing device 10 inputs the first logic signal to the asic 20, so that the asic 20 switches to the self-test mode; inputting a reference clock signal to the asic 20 through the testing apparatus 10 to control the clock pll of the asic 20 to operate; in response to the clock phase-locked loop being in a locked state, performing writing and reading operations on each storage unit to obtain a test result; therefore, the embodiment does not need a large amount of additional logic and wiring resources, and reduces the test cost; in addition, in the embodiment, the pins of the asic 20 are multiplexed, so that the pins of the asic 20 do not need to be added, thereby further reducing the test cost.

As shown in fig. 3, step S103 includes the steps of:

s301: preset data is written to each memory cell.

The test device 10 writes preset data into each memory cell in response to the clock phase-locked loop being in the locked state, so that the test device 10 writes the preset data into all the memory cells. For example, the test apparatus 10 is preset with preset data, and writes the preset data to each memory cell; alternatively, the application specific integrated chip 20 is preset with preset data, and the test apparatus 10 controls the application specific integrated chip 20 to write the preset data into each memory cell.

S302: first data is read from each memory cell.

After the testing device 10 writes the preset data to each memory cell, the testing device 10 reads the first data from each memory cell, where the data read by the testing device 10 from each memory cell may be referred to as the first data, and does not mean that the data read by the testing device 10 from each memory cell must be the same.

S303: and comparing the first data with corresponding preset data to obtain a comparison result.

The testing device 10 compares the first data with the corresponding preset data to obtain a comparison result, where the comparison result includes a first comparison result and a second comparison result, and thus the testing device 10 obtains a plurality of comparison results for the plurality of memory cells. In other embodiments, the asic 20 compares the first data with the corresponding preset data to obtain a comparison result.

In response to the first data being identical to the corresponding preset data, the asic 20 obtains a first comparison result. In response to the first data being different from the corresponding preset data, the asic 20 obtains a second comparison result. Alternatively, the first comparison result may be correct and the second comparison result may be error.

For example, the test apparatus 10 is preset with preset data a, which is written into the memory cell B1, the memory cell B2, and the memory cell B3, respectively. The test apparatus 10 reads the data C1, the data C2 and the data C3 from the memory cell B1, the memory cell B2 and the memory cell B3, respectively. Among them, the data C1, the data C2, and the data C3 may all be referred to as first data. The testing apparatus 10 compares the data C1, the data C2, and the data C3 with the preset data a, respectively, and if the data C1 and the data C2 are the same as the preset data a, the asic 20 obtains two first comparison results; if the data C3 is not the same as the preset data a, the asic 20 obtains a second comparison result; the asic 20 therefore obtains three comparison results.

Alternatively, the asic chip 20 is preset with preset data a1, preset data a2, and preset data A3, and writes the preset data a1, the preset data a2, and the preset data A3 in the memory cell B1, the memory cell B2, and the memory cell B3, respectively. The asic 20 reads data C1, data C2, and data C3 from the memory cell B1, the memory cell B2, and the memory cell B3, respectively. The asic chip 20 compares the data C1, the data C2, and the data C3 with the preset data a1, the preset data a2, and the preset data A3, respectively, and if the data C1 is the same as the preset data a1, the asic chip 20 obtains a first comparison result; if the data C2 is different from the predetermined data A2, the ASIC 20 obtains a second comparison result; if the data C3 is the same as the predetermined data A3, the ASIC 20 obtains a first comparison result; the asic 20 therefore obtains three comparison results.

In the present embodiment, the operations of writing and reading all the memory cells of the asic 20 are implemented by writing the preset data into each memory cell and reading the first data from each memory cell, so that the full coverage test can be implemented for all the memory cells.

S304: a plurality of output signals based on the comparison results of all the memory cells are received, and whether or not the plurality of output signals are all 1 is determined.

The test apparatus 10 receives a plurality of output signals based on the comparison results of all the memory cells, wherein the plurality of output pins 24 of the asic 20 are used for the plurality of output signals, and the test apparatus 10 receives the plurality of output signals through the plurality of output pins 24 of the asic 20.

S305: in response to all of the output signals being 1, the asic 20 is tested successfully.

S306: in response to at least one output signal not being 1, the asic 20 fails the test.

The test device 10 responds to the plurality of output signals all being 1, and then the test success of the special integrated chip 20 is obtained, namely the test result of the test device 10 on the special integrated chip 20 is the test success; and responding to that at least one output signal is not 1, and obtaining that the test of the application specific integrated chip 20 fails, namely that the test result of the test device 10 on the application specific integrated chip 20 is the test failure, so as to realize the test screening of the application specific integrated chip 20 and improve the yield of the application specific integrated chip 20. In addition, the test device 10 reads the states of the output pins 24 to determine the test result of the asic 20, thereby reducing the test time and improving the test efficiency.

As shown in fig. 4, step S304 includes the steps of:

s401: in response to the comparison results of all the memory cells being the first comparison result, a plurality of output signals all being 1 are obtained.

The application specific integrated chip 20 obtains the comparison results of all the memory cells and judges whether the comparison results of all the memory cells are the first comparison result; in response to the comparison results of all the memory cells being the first comparison result, the plurality of output signals output by the asic 20 are all 1, i.e., each output pin 24 of the asic 20 outputs 1. In response to the comparison result of the at least one memory cell being the second comparison result, the process proceeds to step S402.

S402: in response to the comparison result of the at least one memory cell being the second comparison result, the corresponding output signal is not 1.

In response to the comparison result of at least one memory cell being the second comparison result, the asic 20 obtains an output signal corresponding to the memory cell other than 1 (e.g., the output signal is at a low level of 0), and the plurality of output signals output by the asic 20 include an output signal other than 1.

In the present embodiment, the test apparatus 10 obtains the test result of the asic 20 based on the plurality of output signals obtained as a result of comparison of all the memory cells, and the test result can be improved.

In an embodiment, as shown in fig. 5, the asic 20 further includes a plurality of logic core units pe (process elements), a plurality of network on chip units noc (network on chip), and a plurality of memory units 25, wherein the memory units 25 are disclosed in the above embodiment. Wherein a plurality of network-on-chip units NOC may be distributed in a matrix, for example network-on-chip units NOC00-NOC03 are arranged along rows and network-on-chip units NOC00-NOC30 are arranged along columns. And a plurality of network on chips NOC arranged along the rows are connected in sequence, and a plurality of network on chips NOC arranged along the columns are connected in sequence, for example, network on chips NOC00-NOC03 are connected in sequence, and network on chips NOC00-NOC30 are connected in sequence. Each logical core unit PE and each storage unit 25 is connected to a corresponding network on chip unit NOC, for example, network on chip units NOC00-NOC02 are connected to one storage unit 25, network on chip unit NOC03 is connected to two storage units 25, and network on chip units NOC01-NOC31 are connected to one logical core unit PE.

Further, the asic 20 is provided with a plurality of first pins 21, a plurality of second pins 22, a clock pin 23, and a plurality of output pins 24, and the testing device 10 is connected to the plurality of first pins 21 and the plurality of second pins 22 to test the asic 20 through the plurality of first pins 21 and the plurality of second pins 22; the network-on-chip units NOC of each row are provided with two first pins 21 and two second pins 22, respectively, i.e. the application specific integrated chip 20 is provided with 8 first pins 21 and 8 second pins 22. For example, the network on chip unit NOC00-NOC03 is provided with two first pins 21 and two second pins 22, respectively, the first pin 21 being a pin ca0, the second pin 21 being a pin ca1, and the clock pin 23 being a pin ck _ t. In other embodiments, the test apparatus 10 may multiplex 8 first pins 21 to realize the function of 8 second pins 22, for example, the test apparatus 10 only has 8 first pins 21, and does not need to have the second pins 22; the plurality of output pins 24 may also multiplex the 8 first pins 21.

Alternatively, the test apparatus 10 is provided with a plurality of BIST logic units 11, which is a kind of circuit block for testing that is capable of directly generating test stimuli and detecting test responses. Wherein the plurality of BIST logic units 11 are configured to generate a first logic signal and a second logic signal, and receive a plurality of output signals of the application specific integrated chip 20, and generate a test result based on the plurality of output signals. The total number of BIST logic units 11 may be equal to the total number of first pins 21, for example, the testing apparatus 10 is provided with 8 BIST logic units 11, and two BIST logic units 11 are correspondingly provided for a plurality of network on chip units NOC arranged along a row. In other embodiments, the total number of BIST logic units 11 may be set to other values, such as 4, 6, 7.

Based on the self-test method of the above embodiment, the 8 BIST logic units 11 respectively input the first logic signals to the corresponding first pins 21, that is, pull the input of the first pins 21 high, so that the asic 20 switches to the self-test mode, and the clock pll of the asic 20 is started. The test apparatus 10 waits for a third preset time, and inputs a reference clock signal to the clock pin 23 of the asic 20, and the clock pll operates based on the reference clock signal. The test apparatus 10 responds to the clock-locked loop being in the locked state, and the test apparatus 10 performs writing and reading operations on each memory cell 25 through the 8 BIST logic units 11 to receive the plurality of output signals of the asic 20, and generates a test result based on the plurality of output signals, so as to realize that the test apparatus 10 tests the asic 20.

The present application provides a self-test method of another embodiment, as shown in fig. 6, the self-test method includes the following steps:

s501: the ASIC 20 is controlled by the first logic signal to switch to the self-test mode and the clock PLL of the ASIC 20 is enabled.

Step S501 is the same as step S101, and is not described herein again.

S502: and judging whether to test all the logic core units PE based on the second logic signal.

The 8 BIST logic units 11 of the test apparatus 10 input a second logic signal to each of the second pins 22. In response to the second logic signal being at the first level, that is, the second logic signal being at the high level, the testing apparatus 10 needs to test all the logic core units PE, and then step S503 is performed; in response to the second logic signal being at the second level, i.e. the second logic signal being at the low level, the testing apparatus 10 does not need to test all the logic core units PE, and directly proceeds to step S503.

Alternatively, after the test apparatus 10 inputs the first logic signal to each first pin 21, the test apparatus 10 waits for a first preset time, and inputs the second logic signal to each second pin 22, where the first preset time is 1 us. In other embodiments, the first predetermined time may be in the range of 1-5 us.

S503: the clock phase-locked loop of the application specific integrated chip 20 is controlled to operate by the reference clock signal, and the state of the clock phase-locked loop is obtained.

After the test apparatus 10 inputs the second logic signal to each second pin 22, the test apparatus 10 waits for a second preset time, and inputs the reference clock signal to the clock pin 23, where the second preset time is 1 us. In other embodiments, the second predetermined time may be in the range of 1-5 us.

Further, the third preset time of the above embodiment is equal to the sum of the first preset time and the second preset time.

Step S503 is further the same as step S102, and is not repeated herein.

S504: in response to the clock phase locked loop being in a locked state, the write and read operations are performed on each memory cell 25 to obtain the test result.

Step S504 differs from step S103 in that: in response to the second logic signal being at the first level, the test apparatus 10 needs to test all the logic core units PE. Therefore, before the test apparatus 10 performs the writing and reading operations on each memory cell 25, the test apparatus 10 further performs a test on all the logic core units PE, for example, the test apparatus 10 inputs second preset data to each logic core unit PE, each logic core unit PE outputs second data based on the second preset data, and the second data is compared with the corresponding second preset data to obtain a comparison result of all the logic core units PE. The test apparatus 10 obtains a test result based on the comparison results of all the logic core units PE and the comparison results of all the memory units 25.

In this embodiment, it is determined whether to test all the logic core units PE based on the second logic signal, that is, the self-test mode includes testing all the logic core units PE and all the memory units 25, or the self-test mode includes testing only all the memory units 25, so as to support multiple test modes, and the asic 20 having fault-tolerant capability of the logic core units PE can be tested, thereby improving the test range.

As shown in fig. 7, after the clock phase-locked loop of the asic 20 is controlled to operate by the reference clock signal in step S503, the self-test method further includes the steps of:

s601: and counting the test time, and comparing the test time with the preset time.

After the test apparatus 10 inputs the reference clock signal to the clock pin 23, the test apparatus 10 starts counting the test time and comparing the test time with a preset time. Before the testing device 10 obtains the testing result, the testing device 10 determines that the testing time is greater than or equal to the preset time, that is, in response to the testing time being greater than or equal to the preset time, then step S602 is performed; the testing device 10 determines that the testing time is less than the preset time, i.e. in response to the testing time being less than the preset time, returns to the step of comparing the testing time with the preset time.

S602: and acquiring a plurality of output signals in response to the test time being greater than or equal to the preset time, and resetting the test time.

In response to the test time being greater than or equal to the preset time, the test apparatus 10 obtains a plurality of output signals of the asic 20 and resets the test time, i.e., the test time is reset to zero. The testing apparatus 10 obtains the test result based on the plurality of output signals of the asic 20, i.e. performs the step of obtaining the test result in step S504.

In this embodiment, the test time is counted, and the test time is compared with the preset time, so that the test can be completed in time when an error occurs in the test apparatus 10 (for example, the test apparatus 10 goes down), and the accuracy and the test efficiency of the test apparatus 10 are improved.

If the test result obtained by the test apparatus 10 is a test failure, the self-test method further analyzes the asic 20 that has failed in the test, so as to perform scrap processing on the asic 20.

The application further performs simulation test on the application-specific integrated chip 20 based on the self-test method to obtain a simulation result: the testing device 10 tests the asic 20 by the self-testing method, and the test coverage can reach 99.8%, so that the self-testing method of the present application can complete the full-coverage test of the logic of the asic 20 without a large amount of extra logic and wiring resources. In addition, the testing device 10 can also test a plurality of application specific integrated chips 20 at the same time, thereby realizing parallel testing and improving the testing efficiency.

In summary, the self-test method of the present application does not need a large amount of additional logic and wiring resources, and can complete the full-coverage test of the logic of the asic 20, thereby reducing the test cost. In addition, the self-test method of the application can finish the test of the special integrated chip 20 by multiplexing the pins of the special integrated chip 20 without additionally increasing the pins and waiting for a fixed test time (millisecond level), so the test time is short, and the test cost is further reduced. In addition, the self-test method supports multiple test modes, and can test the application specific integrated chip 20 with the fault-tolerant capability of the logic core unit PE, thereby improving the test range.

The present application further proposes a testing device, as shown in fig. 8, the testing device 10 comprising a processor 71 and a memory 72; the memory 72 stores a computer program, and the processor 71 is used for executing the computer program to implement the self-test method disclosed in the above embodiments. The test apparatus 10 is provided with an application specific integrated chip 20 for testing the application specific integrated chip 20.

The present application further proposes a computer-readable storage medium, as shown in fig. 9, the computer-readable storage medium 80 of the present embodiment is used for storing the program instructions 810 of the above-mentioned embodiment, and the program instructions 810 can be executed to implement the control method of the above-mentioned embodiment. The program instructions 810 have been described in detail in the above method embodiments, and are not described in detail here.

The computer readable storage medium 80 of the embodiment may be, but is not limited to, a usb disk, an SD card, a PD optical drive, a removable hard disk, a high-capacity floppy drive, a flash memory, a multimedia memory card, a server, etc.

In addition, if the above functions are implemented in the form of software functions and sold or used as a standalone product, the functions may be stored in a storage medium readable by a mobile terminal, that is, the present application also provides a storage device storing program data, which can be executed to implement the method of the above embodiments, the storage device may be, for example, a usb disk, an optical disk, a server, etc. That is, the present application may be embodied as a software product, which includes several instructions for causing an intelligent terminal to perform all or part of the steps of the methods described in the embodiments.

In the description of the present application, reference to the description of the terms "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, mechanism, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, mechanisms, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and the scope of the preferred embodiments of the present application includes other implementations in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present application.

The logic and/or steps represented in the flowcharts or otherwise described herein, such as an ordered listing of executable instructions that can be viewed as implementing logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device (e.g., a personal computer, server, network device, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions). For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a random access memory unit (RAM), a read-only memory unit (ROM), an erasable programmable read-only memory unit (EPROM or flash memory unit), an optical fiber device, and a portable compact disc read-only memory unit (CDROM). Further, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory unit. The above description is only an embodiment of the present application, and not intended to limit the scope of the present application, and all equivalent mechanisms or equivalent processes performed by the present application and the contents of the appended drawings, or directly or indirectly applied to other related technical fields, are all included in the scope of the present application.

Claims

1. A self-test method for testing an asic chip, the asic chip having a plurality of memory cells, the self-test method comprising:

2. The self-test method according to claim 1, wherein the writing and reading operations for each of the memory cells comprise:

writing preset data into each storage unit;

reading first data from each of the memory cells;

3. The self-test method of claim 2, wherein the obtaining test results comprises:

4. The self-test method according to claim 3, wherein the plurality of output signals based on the comparison results of all of the memory cells comprises:

in response to the comparison results of all the memory cells being the first comparison result, obtaining that the plurality of output signals are all the 1 s;

5. The method of claim 1, wherein the asic has a plurality of first pins, and the controlling the asic to switch to the self-test mode by the first logic signal comprises:

inputting the first logic signal to the plurality of first pins;

6. The self-test method according to any one of claims 1 to 5, wherein the ASIC further comprises a plurality of logic core units and a plurality of network-on-chip units, each of the storage units and each of the logic core units being respectively connected to a corresponding network-on-chip unit, and after the step of activating a clock phase-locked loop of the ASIC, the self-test method further comprises:

7. The method of claim 6, wherein the asic has a plurality of second pins, and the determining whether to test the logic core unit of the asic according to the second logic signal comprises:

and waiting for a first preset time, and inputting the second logic signals to the plurality of second pins.

8. The self-test method of claim 6, wherein the asic is provided with a clock pin, and the controlling the operation of the clock pll of the asic by the reference clock signal comprises:

waiting for a second preset time, and inputting the reference clock signal to the clock pin;

counting the test time, and comparing the test time with preset time;

9. A testing device is characterized in that the testing device is provided with an application specific integrated chip, the application specific integrated chip comprises a plurality of logic core units, a plurality of network-on-chip units, a plurality of storage units and a plurality of first pins, each logic core unit and each storage unit are respectively connected with the corresponding network-on-chip unit, the network-on-chip units in each row are correspondingly provided with two first pins, the testing device is used for testing the application specific integrated chip through the plurality of first pins, and the testing device comprises a processor and a memory; the memory has stored therein a computer program for execution by the processor to carry out the steps of the self-test method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that the computer-readable storage medium stores program instructions that are executable to implement the steps of the self-test method according to any one of claims 1-8.