CN102571079A - ATE (Automatic Test Equipment) test circuit for PLL (Phase Locked Loop) and test method thereof - Google Patents
ATE (Automatic Test Equipment) test circuit for PLL (Phase Locked Loop) and test method thereof Download PDFInfo
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- CN102571079A CN102571079A CN201010607240XA CN201010607240A CN102571079A CN 102571079 A CN102571079 A CN 102571079A CN 201010607240X A CN201010607240X A CN 201010607240XA CN 201010607240 A CN201010607240 A CN 201010607240A CN 102571079 A CN102571079 A CN 102571079A
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Abstract
The invention discloses an ATE (Automatic Test Equipment) test circuit for PLL (Phase Locked Loop) and a test method thereof. The test circuit is arranged at the periphery of a tested PLL circuit, and comprises a test control circuit, a test switch, one or more counters, a comparator and a test result output circuit, wherein the comparator corresponds to each counter. The test method comprises the following steps of: (1) configuring PLL circuit parameters and the test control circuit; (2) starting the test switch; (3) counting by the counter; (4) closing the test switch; (5) comparing, by the comparator, an output value of the counter with a standard value; and (6) outputting the test result. The test circuit provided by the invention is organized in the form of module; the output of the test circuit can be effectively tested in a PLL operation process; the correctness of the PLL output can be judged; the test result is directly output at the end of test; the hardware expenditure is low; the control is simple; and the complexity and the operation difficulty of a test vector used by the ATE are greatly reduced.
Description
Technical field
The present invention relates to field of automatic testing; Especially relate to and be used for ATE (Automatic Test Equipment; Be automated test device) the test methodology field of tester table; Relate more specifically to test circuit and method of testing to PLL (Phase Locked Loop, i.e. phase-locked loop) circuit.
Background technology
Along with the develop rapidly of IC industry, the effect of integrated circuit testing in industrial chain is increasing, and specialized integrated circuit testing already is an important component part in the IC industry.In present IC industry; Because the problems such as excessive cycle of the limitation of dedicated tester, nonstandard parasexuality and dedicated tester exploitation; Make the use of dedicated tester receive bigger restriction, and universal tester ATE is with its versatility, standard, portability and the open main flow that becomes the integrated circuit testing industry rapidly.
As everyone knows; ATE is a kind of equipment that carries out tests such as device, circuit board and subsystem through computer program replacement hand labor; And in the test process of ATE tester table, all be a difficult point to the test of the clock generating circuit PLL of IC interior to integrated circuit all the time.Because the clock signal of PLL is real fast signal, it has represented frequency the fastest in the entire circuit, so its speed that can support output pin and ATE equipment all has higher requirement.In addition and since the PLL in some circuit can't guarantee volume production the time clock signal in every product all have unified phase relation, therefore cause finding unified ATE test vector to come real-time testing is carried out in the output of PLL circuit.
In order to adapt to PLL forms different in the various circuit design, and obtain stable output, need find a kind of effective method of testing to come the PLL circuit is tested specially so that test result is judged accurately.This method of testing should be accomplished: (1) can comprehensively be tested each road output of PLL; (2) can accomplish complete compatibility to the output clock phase difference of the PLL that causes by process variations, promptly can not cause different print selectivity compatibilities because of choosing of pull-in time point of test to circuit-under-test; (3) in circuit-under-test inside PLL output clock is compared and judge; Outside the direct output chip of judged result; Avoiding the lower and test limits that causes of interface pin or the parameter configuration of ATE tester table own, the control testing cost, and improve the stability of test result.
Summary of the invention
In order to overcome above-mentioned one or more deficiencies of existing PLL circuit testing method, the invention provides a kind of comprehensive, compatible all kinds PLL circuit, circuit output pin and ATE testing equipment are required low and/or be easy to the test circuit and the method for testing that realize and measure.
According to an aspect of the present invention, a kind of ATE test circuit to the PLL circuit is provided, this ATE test circuit comprises:
Test control circuit is used to dispose the preassigned value parameter of said ATE test circuit;
At least one counter wherein a road of the corresponding PLL circuit of each counter is exported signal, and each counter is used for the saltus step up and down of its pairing one tunnel output signal is counted;
At least one comparator wherein a road of the corresponding PLL circuit of each comparator export signal, and each comparator is used for the count results and the corresponding standard value parameter of its pairing counter are compared;
Test Switchboard is used to start and stop the work of above-mentioned counter; And
The test result output circuit is used to export the comparative result of above-mentioned comparator.
Preferably, directly control the configuration and the said Test Switchboard of said preassigned value parameter by ATE.
Preferably, when the mode of operation of tested PLL circuit and output branch road select to be configured finish and stable clock signal after, just start said Test Switchboard, to start the work of said counter.
Preferably, describe by test vector the start-up time of said Test Switchboard.
Preferably, calculate the termination time of said Test Switchboard according to the current output clock frequency of tested PLL circuit and the external clock frequency that is input to said PLL circuit.
Preferably, said calculating comprises: the inverse with the current output clock frequency of tested PLL circuit multiply by the respective standard value parameter that is input in the comparator, can obtain Test Switchboard from being opened to the total time of closing; With said total time divided by the inverse of said external clock frequency to obtain the termination time of Test Switchboard.
Preferably, the termination time of said Test Switchboard is described by test vector.
Preferably, through ATE Direct observation and the test result of measuring said ATE test circuit.
Preferably, said ATE test circuit can be tested the multichannel output of PLL circuit, and wherein said ATE test circuit all is provided with standard value parameter, a counter and the comparator through configuration to the every road output in the said multichannel output.
Preferably; The comparative result output signal of each comparator corresponding with the every road output in the output of said multichannel is used as the external pin that one group of test result directly outputs to the chip that said ATE test circuit and tested PLL circuit be positioned at jointly respectively, and confession ATE observes.
Preferably; The comparative result of all comparators that will be corresponding with said multichannel output is through carrying out " logical AND " computing with door; Obtain a final testing result; And only this final testing result is outputed to the external pin of the chip that said ATE test circuit and tested PLL circuit be positioned at jointly separately, supply ATE to observe.
Preferably, said ATE test circuit and said PLL circuit are in same chip.
According to a second aspect of the invention, a kind of ATE method of testing to PLL is provided, it is following to comprise step:
(1) parameter of the tested PLL circuit of configuration and the preassigned value parameter of test circuit;
(2) start Test Switchboard;
(3) after Test Switchboard starts, all counters begin counting to the saltus step up and down of each road output signal of tested PLL circuit respectively simultaneously;
(4) close Test Switchboard;
(5) output numerical value and the corresponding standard value parameter with each counter compares;
(6) output test result.
Preferably, the parameter that disposes said tested PLL circuit comprises that the mode of operation and the output branch road that dispose tested PLL circuit select.
Preferably, in said step (2), the startup of Test Switchboard is directly controlled by ATE, and described by test vector its start-up time.
Preferably, be positioned at the start-up time of Test Switchboard said tested PLL circuit be configured finish and stable clock signal after any time.
Preferably; Said tested PLL circuit is configured and finishes and time that stable clock signal is required; By the self structure feature constraint of tested PLL circuit, the technical staff can select proper time point according to the unique characteristics of tested PLL circuit; And be recorded in the test vector so that on ATE completing steps (2).
Preferably, in said step (4), closing by ATE of Test Switchboard directly controlled, and its shut-in time is described by test vector.
Preferably, calculate the shut-in time of Test Switchboard according to the current output clock frequency of tested PLL circuit and the external clock frequency that is input to said PLL circuit.
Preferably, said calculating comprises: the inverse with the current output clock frequency of tested PLL circuit multiply by the respective standard value parameter that is input in the comparator, can obtain Test Switchboard from being opened to the total time of closing; With said total time divided by the inverse of said external clock frequency to obtain the termination time of Test Switchboard.
Preferably, in said step (5), be stored in comparative result in the built-in memory relatively afterwards and/or directly output.
Preferably, in said step (6), directly measure test result by ATE, the moment of measurement is chosen in above-mentioned Test Switchboard and is closed, and the said comparator output numerical value of accomplishing comparison operation and this comparator is when reaching stable state.
Preferably, in above-mentioned steps (3), tested PLL circuit should be operated in normal mode or other can make under the pattern of PLL circuit normal operation.
Preferably, in counting process, it is stable that the relevant parameter of tested PLL circuit and input clock frequency thereof should keep, so as test result can truly reflect the design and running of tested PLL circuit the time the standard that should possess.
The present invention has following one or more advantage:
1. can comprehensively test each road output of PLL;
2. the phase place difference that the output clock of PLL is caused by process variations can be accomplished complete compatibility, promptly can not cause the different print selectivity compatibilities to circuit-under-test because of choosing of pull-in time point of test;
3. in circuit-under-test inside PLL output clock is compared and judge, outside the direct output chip of judged result, avoiding the lower and test limits that causes of interface pin or the parameter configuration of ATE tester table own, and improve the stability of test result;
4, test circuit of the present invention is organizational form with the module; Can in the PLL running, effectively test its output; And judge the correctness that PLL exports, and when EOT, directly outputing test result, hardware spending is little; Control is simple, greatly reduces the complexity and the operation easier of the employed test vector of ATE.
Description of drawings
In order to describe exemplary embodiment of the present invention in more detail, will carry out reference to accompanying drawing now, in the accompanying drawings:
Fig. 1 is the ATE test circuit structure figure to the PLL circuit according to first embodiment of the invention;
Fig. 2 is the ATE test circuit structure figure to the PLL circuit according to second embodiment of the invention.
Embodiment
Some term is used for indicating particular system component from start to finish in present specification.As person of skill in the art will appreciate that, can indicate identical parts with different titles usually, thereby present specification is unexpectedly schemed to distinguish, and those are just different rather than in the function aspects various parts nominally.In present specification, use a technical term " comprising ", " comprising " and " having " with open form, and so should it be interpreted as mean " including but not limited to ... "
Below in conjunction with accompanying drawing and embodiment the present invention is described in further detail.
Fig. 1 shows first preferred embodiment of the present invention.
As shown in Figure 1, PLL 10 is tested PLL circuit, the actual configuration parameter that is input as external clock and PLL circuit of this PLL circuit 10 (this parameter is predetermined each the relevant work parameter of the manufacturer of PLL circuit).The output of this PLL circuit 10 only has one road two divided-frequency signal (the output clock is 1/2 after the PLL frequency multiplication).When PLL circuit 10 is in normal mode of operation, this road two divided-frequency signal will be imported in the middle of the normal circuit 20 so that normal circuit 20 operates normally; When PLL circuit 10 was in the PLL test pattern, said two divided-frequency signal also will be input in the counter 11 shown in Fig. 1 when being imported into normal circuit 20.(promptly be used to calculate tested PLL circuit 10 and exported what clock pulse) counted in the saltus step up and down of the output signal of 11 pairs of tested PLL circuit 10 of said counter.
As shown in Figure 1, counter 11 links to each other with comparator 12 with Test Switchboard 13 respectively, and wherein, the output signal of said Test Switchboard 13 will be input in the counter 11, and the output signal of said counter 11 will be input in the comparator 12.
Particularly; After 10 configurations of PLL circuit are finished according to said configuration parameter (for example selecting configuration to finish the mode of operation and the output branch road of tested PLL circuit) and PLL circuit 10 are exported the stable clock signals; Open Test Switchboard 13 by ATE control and count, till ATE control Test Switchboard is closed with the saltus step up and down of the output signal of 11 pairs of PLL circuit 10 of enabling counting device.Wherein, calculate the termination time of said Test Switchboard 13 according to the current output clock frequency of tested PLL circuit 10 and the external clock frequency of being imported.
Preferably; ATE tester table of the present invention (abbreviating ATE in this article as) calculates said Test Switchboard 13 through following manner termination time; That is: the inverse (promptly exporting the cycle of clock) with the current output clock frequency of tested PLL circuit multiply by the expectation count value (being standard value parameter 14) that is input in the comparator, can obtain Test Switchboard from being opened to the total time of closing; Afterwards can be obtained the termination time of Test Switchboard 13 said total time divided by said external clock cycle (being the inverse of external clock frequency); This termination time is used for indication when what cycles external clock arrives, and ATE closes said Test Switchboard 13.
Wherein, the start-up time of said Test Switchboard and termination time preferably adopt test vector to describe.
In addition; The ATE test circuit to the PLL circuit according to first embodiment of the invention also comprises the test control circuit (not shown in figure 1); It is used to dispose the preassigned value parameter (being foregoing preset expected count value) of said ATE test circuit, and said preassigned value parameter 14 is input in the said comparator 12.
As previously mentioned, the actual count result of counter 11 is outputed in the comparator shown in Figure 1 12, in this comparator 12, compares to said actual count result with from the preassigned value parameter of said test control circuit.If comparative result is identical, then export high level; If comparative result is different, then output low level.This comparative result directly exports the output pin of the chip that said ATE test circuit and tested PLL circuit be positioned at jointly to by test result output circuit (not shown in figure 1), carries out Direct observation and measurement by ATE.
To describe the second embodiment of the present invention in detail below.
As shown in Figure 2, the configuration parameter that is input as external clock and PLL of tested PLL circuit 100 (with embodiment 1).This tested PLL circuit is output as one road two divided-frequency signal, one road three frequency division signal and one tunnel four fractional frequency signal (the output clock is respectively 1/2,1/3 and 1/4 after the PLL frequency multiplication).When tested PLL circuit 100 was in normal mode of operation, this three-way output signal used for normal circuit in the middle of being imported into normal circuit; When tested PLL circuit is in test mode following time, this three road signal also is imported in three different counter 111,112,113 shown in Fig. 2 when being outputed to normal circuit.Said three counters 111,112,113 are counted (what clock pulse each road that promptly is used to calculate tested PLL circuit 100 has exported) to the saltus step up and down of each road output signal of tested PLL circuit 100 respectively.
As shown in Figure 2; In the counter 111,112,113 each all links to each other with a comparator with Test Switchboard 130; Wherein, the output signal of said Test Switchboard 130 will be input in each counter, and the output signal of said each counter will be input in the comparator corresponding with it.
After finishing when PLL circuit 100 is configured (for example selecting configuration to finish the mode of operation of tested PLL circuit and output branch road) and exporting stable clock signal; Test Switchboard 130 each counter 111,112,113 of startup by ATE control are counted; That is: this Test Switchboard 130 is controlled three counters simultaneously and is counted simultaneously, till ATE control Test Switchboard 130 is closed.
Wherein, calculate the termination time (account form is with the corresponding account form among first embodiment) of said Test Switchboard 130 according to the current output clock frequency of tested PLL circuit 100 and the external clock frequency of being imported.
Wherein, the start-up time of said Test Switchboard 130 and termination time are preferably described by test vector.
In addition; The ATE test circuit to the PLL circuit according to second embodiment of the invention also comprises test control circuit (not shown among Fig. 2); It is used for disposing according to each road output frequency of PLL circuit each preassigned value parameter (each promptly corresponding respectively with each road output of tested PLL circuit preset expected count value) of said ATE test circuit, and said each preassigned value parameter is input to respectively in the corresponding comparator; For example; The first preassigned value parameter is input in the comparator 121; The second preassigned value parameter is input in the comparator 122; The 3rd preassigned value parameter is input in the comparator 123, and wherein the first via of this first preassigned value parameter and PLL circuit is exported the frequency dependence of signal (two divided-frequency signal as shown in Figure 2), the frequency dependence of the second tunnel output signal (three frequency division signal as shown in Figure 2) of the second preassigned value parameter and PLL circuit; The rest may be inferred, the frequency dependence of the Third Road output signal (four fractional frequency signals as shown in Figure 2) of the 3rd preassigned value parameter and PLL circuit.
As previously mentioned; The count results of each road counter is exported to respectively in the comparator of the correspondence shown in Fig. 2; That is: the actual count result of counter 111 is imported in the comparator 121; The actual count result of counter 112 is imported in the comparator 122, and the actual count result of counter 113 is imported in the comparator 123.In each comparator, the actual count result who is imported is compared with the corresponding preassigned value parameter of being imported by test control circuit (each road all has one group of independent predetermined standard value to compare).If comparative result is identical, then export high level; If comparative result is different, then output low level.
Preferably; Three road comparative results are delivered to one three input and door 150; To carry out " logical AND " computing; Thereby obtain a final result, export final result the outside output pin of the chip that said ATE test circuit and tested PLL circuit be positioned at jointly to through test result output circuit (not shown among Fig. 2) then, measure by ATE.
Replacedly; Also can make with said three tunnel outputs in the comparative result of corresponding each comparator of every road output directly output to the outside output pin of the chip that said ATE test circuit and tested PLL circuit be positioned at jointly as one group of test result via the test result output circuit respectively, confession ATE measures.
Whether replacedly, the comparative result among above-mentioned first embodiment and second embodiment also can be stored in earlier in the built-in memory, according to circumstances select then to export.
Preferably, in first embodiment and second embodiment, the measurement of directly measuring test result by ATE is chosen in above-mentioned Test Switchboard constantly and is closed, and the said comparator output numerical value of accomplishing comparison operation and this comparator is when reaching stable state.
Preferably, in the process that counter is counted, tested PLL circuit should be operated in normal mode or other can make under the pattern of PLL circuit normal operation.
Preferably, in counting process, it is stable that the relevant parameter of tested PLL circuit and input clock frequency thereof should keep, so as test result can truly reflect the design and running of tested PLL circuit the time the standard that should possess.
Preferably, in the aforementioned embodiment, said ATE test circuit and said PLL circuit are in same chip.
Through the description of above-mentioned two embodiment, advantage of the present invention is tangible.The present invention has overcome the aforementioned deficiency of conventional P LL circuit testing method, and feasibility is good, the test result true and accurate.
What should explain at last is: above embodiment is the unrestricted technical scheme of the present invention in order to explanation only; Although the present invention is specified with reference to the foregoing description; Those of ordinary skill in the art is to be understood that: still can make amendment or be equal to replacement the present invention; And replace any modification or the part that do not break away from the spirit and scope of the present invention, and it all should be encompassed in the middle of the claim scope of the present invention.
Claims (10)
1. ATE test circuit to the PLL circuit is characterized in that this ATE test circuit comprises:
Test control circuit is used to dispose the preassigned value parameter of said ATE test circuit;
At least one counter wherein a road of the corresponding PLL circuit of each counter is exported signal, and each counter is used for the saltus step up and down of its pairing one tunnel output signal is counted;
At least one comparator wherein a road of the corresponding PLL circuit of each comparator export signal, and each comparator is used for the count results and the corresponding standard value parameter of its pairing counter are compared;
Test Switchboard is used to start and stop the work of above-mentioned counter; And
The test result output circuit is used to export the comparative result of above-mentioned comparator.
2. ATE test circuit according to claim 1 is characterized in that, when the mode of operation of tested PLL circuit and output branch road select to be configured finish and stable clock signal after, said Test Switchboard just is activated, to start the work of said counter.
3. ATE test circuit according to claim 1 and 2 is characterized in that, the termination time of said Test Switchboard is to calculate according to the current output clock frequency of tested PLL circuit and the external clock frequency that is input to said PLL circuit.
4. ATE test circuit according to claim 3 is characterized in that, said calculating comprises:
Inverse with the current output clock frequency of tested PLL circuit multiply by the respective standard value parameter that is input in the comparator, can obtain Test Switchboard from being opened to the total time of closing;
With said total time divided by the inverse of said external clock frequency to obtain the termination time of Test Switchboard.
5. ATE test circuit according to claim 1 and 2; It is characterized in that; Said tested PLL circuit output multichannel output signal; The comparative result output signal of the comparator corresponding with every road output signal in the said multichannel output signal is used as the external pin that one group of test result directly outputs to the chip that said ATE test circuit and tested PLL circuit be positioned at jointly respectively, and confession ATE observes.
6. ATE test circuit according to claim 1 and 2; It is characterized in that; Said tested PLL circuit output multichannel output signal, the comparative result of all comparators that will be corresponding with said multichannel output signal obtains a final testing result through carrying out " logical AND " computing with door; And this final testing result outputed to the external pin of the chip that said ATE test circuit and tested PLL circuit be positioned at jointly separately, supply ATE to observe.
7. ATE method of testing to the PLL circuit, it is following to comprise step:
(1) parameter of the tested PLL circuit of configuration and the preassigned value parameter of test circuit;
(2) start Test Switchboard;
(3) after Test Switchboard starts, all counters begin counting to the saltus step up and down of each road output signal of tested PLL circuit respectively simultaneously;
(4) close Test Switchboard;
(5) output numerical value and the corresponding standard value parameter with each counter compares;
(6) output test result.
8. ATE method of testing according to claim 7 is characterized in that, be positioned at the start-up time of Test Switchboard said tested PLL circuit be configured finish and stable clock signal after.
9. ATE method of testing according to claim 7 is characterized in that, the shut-in time of Test Switchboard is to calculate according to the current output clock frequency of tested PLL circuit and the external clock frequency that is input to said PLL circuit.
10. ATE method of testing according to claim 9 is characterized in that, said calculating comprises:
Inverse with the current output clock frequency of tested PLL circuit multiply by the respective standard value parameter that is input in the comparator, can obtain Test Switchboard from being opened to the total time of closing;
With said total time divided by the inverse of said external clock frequency to obtain the termination time of Test Switchboard.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010607240XA CN102571079A (en) | 2010-12-27 | 2010-12-27 | ATE (Automatic Test Equipment) test circuit for PLL (Phase Locked Loop) and test method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010607240XA CN102571079A (en) | 2010-12-27 | 2010-12-27 | ATE (Automatic Test Equipment) test circuit for PLL (Phase Locked Loop) and test method thereof |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104660256A (en) * | 2015-03-04 | 2015-05-27 | 上海华岭集成电路技术股份有限公司 | Method for measuring locking time of phase-locked loop |
| CN105093001A (en) * | 2014-05-20 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Automatic analysis test system for characteristics of high-speed PLL and clock chip |
| CN105182067A (en) * | 2015-09-30 | 2015-12-23 | 上海大学 | SOC frequency testing method |
| CN105807205A (en) * | 2016-03-11 | 2016-07-27 | 福州瑞芯微电子股份有限公司 | PLL automatic test circuit and test method |
| CN109361567A (en) * | 2018-11-14 | 2019-02-19 | 北京中电华大电子设计有限责任公司 | A kind of method and device of test lot product UART communication compatibility |
| WO2019144671A1 (en) * | 2018-01-24 | 2019-08-01 | 晶晨半导体(上海)股份有限公司 | Method for measuring stability of phase locked loop within central processing unit by using frequency meter |
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| JP2002300029A (en) * | 2001-03-29 | 2002-10-11 | Nec Corp | Pll circuit and its lock decision circuit, and test method and device |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105093001A (en) * | 2014-05-20 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Automatic analysis test system for characteristics of high-speed PLL and clock chip |
| CN104660256A (en) * | 2015-03-04 | 2015-05-27 | 上海华岭集成电路技术股份有限公司 | Method for measuring locking time of phase-locked loop |
| CN104660256B (en) * | 2015-03-04 | 2017-10-31 | 上海华岭集成电路技术股份有限公司 | The measuring method of phase lock loop lock on time |
| CN105182067A (en) * | 2015-09-30 | 2015-12-23 | 上海大学 | SOC frequency testing method |
| CN105182067B (en) * | 2015-09-30 | 2018-03-06 | 上海大学 | SOC frequency test method |
| CN105807205A (en) * | 2016-03-11 | 2016-07-27 | 福州瑞芯微电子股份有限公司 | PLL automatic test circuit and test method |
| CN105807205B (en) * | 2016-03-11 | 2018-07-03 | 福州瑞芯微电子股份有限公司 | PLL automatic testing circuits and test method |
| WO2019144671A1 (en) * | 2018-01-24 | 2019-08-01 | 晶晨半导体(上海)股份有限公司 | Method for measuring stability of phase locked loop within central processing unit by using frequency meter |
| US10868549B2 (en) | 2018-01-24 | 2020-12-15 | Amlogic (Shanghai) Co., Ltd. | Method for measuring stability of internal phase locked loop of central processing unit by frequency meter |
| CN109361567A (en) * | 2018-11-14 | 2019-02-19 | 北京中电华大电子设计有限责任公司 | A kind of method and device of test lot product UART communication compatibility |
| CN109361567B (en) * | 2018-11-14 | 2020-09-15 | 北京中电华大电子设计有限责任公司 | Method and device for testing UART (universal asynchronous receiver/transmitter) communication compatibility of batch products |
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Application publication date: 20120711 |