CN111123083A

CN111123083A - Test system and method for FPGA PLL IP core

Info

Publication number: CN111123083A
Application number: CN201911244497.0A
Authority: CN
Inventors: 周芝梅; 万勇; 冯晨; 徐浩; 韩圣亚; 黄振; 王飞
Original assignee: State Grid Sigi Ziguang Qingdao Microelectronics Technology Co Ltd; State Grid Corp of China SGCC; Beijing Smartchip Microelectronics Technology Co Ltd; Information and Telecommunication Branch of State Grid Shandong Electric Power Co Ltd
Current assignee: Qingdao Zhixin Semiconductor Technology Co ltd; State Grid Corp of China SGCC; Beijing Smartchip Microelectronics Technology Co Ltd; Information and Telecommunication Branch of State Grid Shandong Electric Power Co Ltd
Priority date: 2019-12-06
Filing date: 2019-12-06
Publication date: 2020-05-08
Anticipated expiration: 2039-12-06
Also published as: CN111123083B

Abstract

The invention provides a test system and a test method for an FPGA PLL IP core, which comprise the following steps: the device comprises a circuit board to be tested, and a signal source and a PC (personal computer) which are respectively connected with the circuit board to be tested; the PC is also connected with a signal source; the FPGA chip to be tested is arranged on the circuit board to be tested; the PC is used for triggering a signal source to generate a clock signal based on a preset test case; the test bit stream code is also used for generating a test bit stream code based on the test case and downloading the test bit stream code to the FPGA chip to be tested through the circuit board to be tested; the circuit board to be tested is used for transmitting an output signal generated by the FPGA chip to be tested through operation based on the test bit stream code and the clock signal to the PC; and the PC is also used for analyzing the output signal of the FPGA chip to be tested to complete the test. The invention realizes the automatic test of the PLL IP core in the FPGA chip, and the test platform can carry out comprehensive test on the PLL IP core without the built-in self-test circuit and can also carry out supplementary test on the PLL IP core with the built-in self-test circuit.

Description

Test system and method for FPGA PLL IP core

Technical Field

The invention relates to the technical field of integrated circuit measurement, in particular to a test system and a test method for an FPGA PLL IP core.

Background

The FPGA is a digital integrated circuit which is programmed by a user to realize the required logic function, has the advantages of flexible design, high performance, high speed and the like, and has short development period and low cost, thereby being widely applied in the field of digital signal processing. However, as the operating frequency of digital systems is continuously increased and the data processing requirement of higher throughput is increased, the digital systems are required to operate at higher frequency and have higher reliability and stability. Therefore, the clock system will directly affect the reliability and stability of the whole system, and as the FPGA scale becomes larger, the number of PLLs embedded in the FPGA is also increasing, so how to improve the reliability and stability of the FPGA clock system and perform a comprehensive and effective test becomes a problem that designers must face.

The built-in self-test system of the phase-locked loop can realize on-chip self-test and output results so as to be convenient for viewing, and can accurately position the defect position of a chip which does not pass the test, but the additionally added built-in self-test circuit can increase the area and the design difficulty of the chip on one hand and also can influence the normal work and the test accuracy of the phase-locked loop on the other hand. The method for testing the functional parameters of the phase-locked loop by using the testing instrument outside the chip can effectively ensure that a circuit passing the test is qualified, but because the functional parameters of the phase-locked loop are more, the test on each parameter cannot be carried out, the test time is long, the test cost is high, and the method is difficult to be used in engineering practice.

Disclosure of Invention

In order to solve the problems that the traditional test method in the prior art cannot effectively and accurately test the phase-locked loop and the test time is long, the invention provides the test system and the test method aiming at the FPGA PLL IP core, the test time is short, and the internal space is saved.

The technical scheme provided by the invention is as follows:

in a test system for an FPGA PLL IP core, the improvement comprising: the device comprises a circuit board to be tested, and a signal source and a PC (personal computer) which are respectively connected with the circuit board to be tested; the PC is also connected with a signal source; the FPGA chip to be tested is arranged on the circuit board to be tested;

the PC is used for triggering a signal source to generate a clock signal based on a preset test case; the test bit stream code is also used for generating a test bit stream code based on the test case and downloading the test bit stream code to the FPGA chip to be tested through the circuit board to be tested;

the circuit board to be tested is used for transmitting an output signal generated by the FPGA chip to be tested through operation based on the test bit stream code and the clock signal to the PC;

and the PC is also used for analyzing the output signal of the FPGA chip to be tested to complete the test.

Preferably, the test bitstream code includes:

a test bit stream code for frequency testing, a test bit stream code for placeholder testing, and a test bit stream code for phase testing.

Preferably, the circuit board to be tested comprises a plurality of interfaces, a plurality of FPGA chips to be tested can be installed through the interfaces, and input and output signals of the FPGA chips to be tested are transmitted.

Preferably, the test cases are plural and are set based on an input/output frequency range, a duty ratio, and a phase of the PLL.

Preferably, the system further comprises a logic analyzer; the circuit board to be tested is connected with a PC through the logic analyzer;

and the logic analyzer samples the output signal of the FPGA chip to be tested based on the test circuit board and transmits the sampled output signal to the PC.

Preferably, the system further comprises a power source;

and the power supply is connected with the PC and the circuit board to be tested respectively and is used for providing a core and an I/O power supply for the circuit board to be tested according to the control command of the PC.

Based on the same inventive concept, the invention also provides a test method for FPGA PLL IP cores, and the improvement comprises the following steps:

the PC generates a test bit stream code based on a preset test case, and downloads the test bit stream code to the FPGA chip to be tested through the circuit board to be tested;

meanwhile, a signal source is controlled to output a clock signal to the circuit board to be tested based on the test case;

the FPGA chip to be tested performs operation on the basis of the test bit stream code and the clock signal acquired by the circuit board to be tested to generate an output signal, and transmits the output signal to the PC;

and the PC machine analyzes the output signal to complete the test.

Preferably, the test bitstream code includes:

Preferably, when the test bit stream code is a test bit stream code for frequency testing, the PC analyzes the output signal to complete the testing, including:

the PC calculates the time of each period of the output signal;

calculating a time average value according to the time of each period;

and comparing the difference between the time of each period of the output signal and the time average value, if the difference exceeds a preset time threshold value, judging that the frequency of the output signal is unstable, and otherwise, calculating the frequency value of the output signal according to the time average value.

Preferably, when the test bit stream code is a test bit stream code for a space-occupying ratio test, the PC analyzes the output signal to complete the test, including:

the duty ratio of each period of the output signal of the PC;

calculating the average value of the duty ratio according to the duty ratio of each period;

and comparing the difference value of the duty ratio of each period of the output signal with the average value of the duty ratio, if the difference value exceeds a preset duty ratio threshold value, judging that the duty ratio of the output signal is unstable, and otherwise, calculating the duty ratio of the output signal according to the average value of the duty ratio.

Preferably, when the test bit stream code is a test bit stream code for phase test, the PC analyzes the output signal to complete the test, including:

the PC calculates the phase of each period of the output signal;

calculating a phase average value according to the phase of each period;

and comparing the difference between the phase of each period of the output signal and the average value of the phase, if the difference exceeds a preset phase threshold, judging that the phase of the output signal is unstable, and otherwise, calculating the phase of the output signal according to the average value of the phase.

Preferably, the calculation of the phase includes:

setting three paths of output signals of the PLL to be at the same frequency, and setting one path of output signal as a reference signal;

and calculating the offset of the remaining two paths of output signals relative to the reference signal to obtain the phase of the output signals.

Preferably, the PC generates a test bit stream code based on a preset test case, and includes:

the PC generates a test bit stream code in an FPGA integrated development environment through software with a recording and playback function based on a preset test case;

or generating a test bit stream code according to preset generation software based on a preset test case.

Compared with the prior art, the invention has the beneficial effects that:

the invention provides a test system and a test method for an FPGA PLL IP core, which comprise the following steps: the device comprises a circuit board to be tested, and a signal source and a PC (personal computer) which are respectively connected with the circuit board to be tested; the PC is also connected with a signal source; the FPGA chip to be tested is arranged on the circuit board to be tested; the PC is used for triggering a signal source to generate a clock signal based on a preset test case; the test bit stream code is also used for generating a test bit stream code based on the test case and downloading the test bit stream code to the FPGA chip to be tested through the circuit board to be tested; the circuit board to be tested is used for transmitting an output signal generated by the FPGA chip to be tested through operation based on the test bit stream code and the clock signal to the PC; and the PC is also used for analyzing the output signal of the FPGA chip to be tested to complete the test. The invention realizes the automatic test of the PLLIP core in the FPGA chip, and the test platform can carry out comprehensive test on the PLL IP core without the built-in self-test circuit and can also carry out supplementary test on the PLL IP core with the built-in self-test circuit.

The invention can ensure that the circuit passing the test is qualified, can test the input and output frequency range, the duty ratio and the phase position of the PLL IP core with higher coverage rate in a short time by reasonably selecting the test case, and can gradually increase the test cases to continuously improve the test coverage rate. And the test platform can also simultaneously test multiple PLL, and the test efficiency is high.

The invention provides two methods for automatically generating a test bit stream code. The first method is to generate a test bit stream code from an FPGA integrated development environment according to the requirements of test conditions through software with a recording and playback function. The second is to write a test bit stream code generation software by itself, and the software can modify the corresponding test bit stream code in the configuration file according to the requirement of the test condition to realize the change of the test condition. The test bit stream code generation speed of the second method may be significantly higher than that of the first method.

The invention carries out the work of electrifying, exciting, downloading test bit stream codes, sampling output signals, analyzing sampling files, saving test results and the like of the circuit board to be tested through the PC and the internal software, thereby realizing the full automation of the whole test process.

After each circuit is tested, the voltage and the current value of the power supply are recorded, the voltage and the current value of the power supply are detected, and the power supply is powered off and then powered on again when the voltage or the current value of the power supply is abnormal. Therefore, the circuit board to be tested is effectively protected, the normal test of the next circuit is effectively ensured, and the result analysis after the test is finished is facilitated.

The invention separately tests the frequency, duty ratio and phase of the PLL IP core, reduces the complexity of test case design, makes the test more orderly and makes the test result more convenient to analyze.

When the phase test is carried out, one output signal is taken as a reference, and the phases of the other two output signals are tested, so that the phase of the output signal is very simple to calculate.

Drawings

FIG. 1 is a schematic diagram of a basic structure of a test system for an FPGA PLL IP core according to the present invention;

FIG. 2 is a schematic structural diagram of an embodiment of a test system for FPGA PLL IP cores according to the present invention;

FIG. 3 is a flow chart of a testing method for FPGA PLL IP cores according to the present invention;

FIG. 4 is a schematic diagram of a logic analyzer sample file in an embodiment of the present invention;

fig. 5 is a schematic diagram of PLL output waveforms when the frequencies of c0, c1, and e0 are 2 times of the input frequency and the phases are all 0 ° in the embodiment of the present invention;

fig. 6 is a schematic diagram of PLL output waveforms when the frequencies of c0, c1, and e0 are set to be 2 times of the input frequency (the phases of c0 and c1 are 90 ° and e0 are 0 °) in the embodiment of the present invention.

Detailed Description

For a better understanding of the present invention, reference is made to the following description taken in conjunction with the accompanying drawings and examples.

In order to overcome the defects of the prior art, the technical scheme adopted by the invention is shown in fig. 1, and the test system for FPGA PLL IP cores comprises: the device comprises a circuit board to be tested, and a signal source and a PC (personal computer) which are respectively connected with the circuit board to be tested; the PC is also connected with a signal source; the FPGA chip to be tested is arranged on the circuit board to be tested; the PC is used for triggering a signal source to generate a clock signal based on a preset test case; the test bit stream code is also used for generating a test bit stream code based on the test case and downloading the test bit stream code to the FPGA chip to be tested through the circuit board to be tested; the circuit board to be tested is used for transmitting an output signal generated by the FPGA chip to be tested through operation based on the test bit stream code and the clock signal to the PC; and the PC is also used for analyzing the output signal of the FPGA chip to be tested to complete the test.

More specifically, in the FPGA PLL IP core-oriented test system, an FPGA chip to be tested is installed on a circuit board to be tested, an input signal and an output signal of the FPGA chip are led to a test point on the circuit board to be tested, so that the FPGA chip is stimulated and an output signal of the FPGA chip is observed, a power supply provides a core and an I/O power supply for the circuit board to be tested, a signal source provides an input clock signal for the circuit board to be tested, a logic analyzer samples and stores the output signal of a PLL in the FPGA chip to be tested on the circuit board to be tested as a file for analysis, a PC is a control center of a test verification platform, and the completed work comprises that ① downloads a test bit stream code into the FPGA chip to be tested on the circuit board to be tested, ② controls output voltage, current limiting and records a power output voltage value and an output current value, ③ controls waveform, frequency and duty ratio of the output signal of the signal source, ④ controls the logic analyzer to sample the output signal on the circuit board to be tested and store the sampled signal in the file, and ⑤ analyzes the file to obtain information of locking condition, frequency, duty ratio, phase and storage of the output.

The PLL is a phase-locked loop of the FPGA chip and is stored in the form of an IP core;

the phase of the phase-locked loop refers to a difference value of an output signal relative to an input signal, clock periods may be different due to different frequencies of the output signal and the input signal of the phase-locked loop, and in addition, factors such as delay from an input signal observation point on a circuit board to an FPGA chip pin, delay from input and output inside the chip, delay from the FPGA chip output pin to a circuit board output signal observation point and the like need to be calculated during phase calculation. The original method of calculating the phase is therefore complex.

In the invention, three paths of output signals are set to be the same frequency, one path of output signal is used as a reference signal, and the offset of the other two paths of output signals relative to the reference signal is tested, so that the phase can be simply and conveniently calculated, and the delay of various circuit boards and chips in the conventional method does not need to be considered, thus the calculation of the phase of the output signal is very simple and accurate.

Example 1:

a specific embodiment of a test system for the FPGA PLL IP core is provided below, as shown in fig. 2.

The FPGA chip in the test is selected from self-developed FPGA chips, each FPGA chip comprises 8 PLLs with the same design and mutually independent, each PLL has a locked signal for marking the locking condition and three clock output signals of c0, c1 and e0, each PLL is designed with a common mode, a zero delay mode and an uncompensated mode, c0 feedback or c1 feedback can be selected in the common mode, e0 feedback is selected in the zero delay mode, and the common mode and the zero delay mode are collectively called as the compensated mode. The input frequency range is 15.625 MHz-60 MHz under the compensation mode, and 15.625 MHz-420 MHz under the uncompensated mode. The output frequency range of the VCO is 300 MHz-800 MHz, the output frequency ranges of c0, c1 and e0 are 9.375 MHz-800 MHz, the duty ratio ranges of c0, c1 and e0 are 0-100%, the phase shift ranges of c0, c1 and e0 are 0-360 degrees, and the highest frequency of signals on an I/O pin of the FPGA chip is not more than 200 MHz.

The power supply selects E3631A of Agilent, the signal source selects AFG3102 of Thank, the logic analyzer selects TLA7016 of Thank, the TLA7016 has the highest sampling rate of 50GHz, 256 sampling channels and the maximum sampling depth of 2M of each channel can meet the testing requirement and ensure the testing precision. During testing, one PLL can be tested at a time, and a plurality of PLLs can also be tested simultaneously in the same method as that of testing one PLL.

The upper computer is a PC, an FPGA EDA tool for generating the bit stream code of the FPGA to be tested is installed on the PC, the EDA tool generates the bit stream code used for testing, the FPGA chip to be tested is configured in real time through a download cable, configuration data enter a configuration controller (CFGC) of the chip through a special IO of the FPGA to be tested, and the configuration controller distributes the configuration data to an FPGA internal module comprising a PLL. In addition, the upper computer also controls the power supply E3631A and the signal source AFG3102 through a GPIB bus to generate a power supply required by the normal work of the FPGA to be detected and an input clock of a FPGA PLL IP core to be detected, and reads the current value and the voltage value of the power supply applied to the chip to be detected by the power supply E3631A in real time, so as to monitor whether the chip to be detected still works normally, once the current value and the voltage value are abnormal, the upper computer controls the power supply and the signal source to be closed through the GPIB bus, and the power supply and the clock signal are not output any more. The upper computer is also connected to and controls the logic analyzer through a network cable, the logic analyzer collects pin signals of the FPGA chip to be tested through a signal cable special for the logic analyzer, and the collected data are sent back to the upper computer for storage. The power supply is connected to the circuit board to be tested through a power line and used for providing power for the circuit board to be tested; the signal source is connected to the circuit board to be tested through the shielded twisted pair, and further connected to the PLL IP input end of the FPGA to be tested.

Example 2:

the invention also provides a test method aiming at the FPGA PLL IP core, which comprises the following steps:

step 1: the PC generates a test bit stream code based on a preset test case, and downloads the test bit stream code to the FPGA chip to be tested through the circuit board to be tested;

step 2: meanwhile, a signal source is controlled to output a clock signal to the circuit board to be tested based on the test case;

and step 3: the FPGA chip to be tested performs operation on the basis of the test bit stream code and the clock signal acquired by the circuit board to be tested to generate an output signal, and transmits the output signal to the PC;

and 4, step 4: and the PC machine analyzes the output signal to complete the test.

Specifically, the test is divided into two stages, wherein the first stage is a test preparation stage and comprises the formulation of a test file and the generation of an FPGA code matching file. The second phase is a testing phase, which includes specific testing and test data analysis.

The test file formulation comprises frequency selection of input signals, PLL working mode selection, frequency selection, duty ratio selection and phase selection of output signals, the selection is made according to a specific PLL structure, and the selection criteria are as follows: the maximum test coverage is achieved by using the fewest test cases as possible.

During test file preparation, testing of the PLL is divided into three aspects, in the first aspect, a PLL input and output frequency range is tested, for each working mode of the PLL, a plurality of test points are selected from the lowest input frequency to the highest input frequency in the input frequency range, and all values or partial values of the output frequency corresponding to each selected input frequency are tested. In a second aspect, the duty cycle of the output clock of the PLL is tested, several sets of fixed input and output frequencies are selected for each operating mode of the PLL, and each selectable duty cycle is tested for each selected set of input and output frequency combinations. In the third aspect, the phase of the PLL is tested, several groups of fixed input and output frequencies are selected for each operating mode of the PLL, each optional phase is tested for each selected group of input and output frequency combination, for analysis, the duty ratios of three output signals are all set to 50%, the frequencies are always consistent, and the phase shift of the other two paths is tested by taking one path as a reference (i.e., the phase of the output signal is always set to 0 °).

And establishing a test file for each aspect of the PLL test, and respectively selecting an Excel file as a record file of the test conditions and the test results. Because the maximum frequency of the signal on the I/O pin of the FPGA chip does not exceed 200MHz, when the input and output frequency range of the PLL is tested, when the output frequency of the PLL exceeds 200MHz, the PLL is divided (for example, divided by 4) to within 200MHz and then output to the I/O pin of the FPGA chip, and the frequency division parameters are recorded in a test file so as to be applied during result analysis. The output frequency is set to not exceed 200MHz when testing the PLL duty cycle and phase.

After the test file is customized, the FPGA code allocation file can be generated according to the test file, wherein the code allocation in this embodiment is a test bit stream code. The first method is to select a software (such as Ranorex Studio) with a recording and playback function, record the process of setting relevant parameters to generate corresponding code matching files under an FPGA chip integrated development environment, then bind the relevant parameters with test files, and then enable the software to automatically generate all code matching files required by the test files. The second method is that firstly, related parameters are manually set in an FPGA chip integrated development environment to generate a corresponding code matching file, then, software is developed, the software can change corresponding code matching bits in the code matching file according to the parameters in the test file, and all code matching files required by the test file can be automatically generated by running the software. The first method can be selected to generate the code matching file under the condition that the FPGA code matching file is not known, and the second method can be selected to quickly obtain the required code matching file under the condition that the FPGA code matching file is known.

After the test preparation is completed, the test can be started, and the test steps are as follows:

① the control software in PC sets the voltage and current of power supply to make it work under relevant state.

② the control software in PC reads the test condition from the test file and sets the signal source to work in corresponding state according to the input signal frequency in the test condition.

③ the control software in PC finds the matching code file from the test file, and downloads the matching code for FPGA chip.

④ the logic analyzer samples the output signal at a sampling rate of 50GHz and saves the sampled signal as a file.

⑤ the control software in PC analyzes the sampling file obtained by the logic analyzer, and writes the analysis result into the test file, and writes the power voltage and current into the test file.

⑥ writing the power voltage and current into the test file, and detecting the power voltage and current, if the power voltage is lower than the preset voltage value or the power current reaches the current-limiting value, the power is cut off again and then powered on.

And repeating the steps ② - ⑥, and continuing to test the next test item until the test of all test items in the test file is completed.

In step ③, the downloading of the configuration code includes:

acquiring a configuration code, configuring the FPGA to be tested through an external interface, and judging whether the configuration is successful;

if the configuration is successful, the successfully configured configuration codes are converted into test signal source files which can be identified and executed by the test equipment through controlling a test algorithm and a conversion tool, and reusable test signal source codes of the multiple equipment are generated;

and the test signal source file is automatically loaded to the FPGA to be tested in real time, so that the FPGA is rapidly configured under the condition of no power failure.

Between

steps

① and ②, the method further comprises:

checking hardware in the test system;

receiving frame data fed back by the hardware, and if the received frame data is wrong, rechecking the hardware in the test system until the received frame data is correct;

loading a test configuration to meet test requirements of the PLL;

implementing an open-circuit short-circuit test to check whether the interfaces among the hardware work normally;

implementing a configuration of functional pin assignments to instruct associated devices to complete testing for satisfaction of the PLL;

setting relevant test parameters of a power supply, a signal source and a logic analyzer;

triggering a logic analyzer to carry out testing;

and acquiring and analyzing test data returned by the logic analyzer, if the test result does not meet the requirements, re-triggering the logic analyzer to perform the test, and if the re-triggering of the logic analyzer for a preset number of times still does not meet the requirements, re-setting the relevant test parameters of the power supply, the signal source and the logic analyzer until the test result meets the requirements.

The control software in the PC and the logic analyzer run cooperatively, and software with recording and playback functions is adopted to control, so that the test process is recorded once, the test conditions and the test files are well bound, and the whole test process can be automatically completed. After the test is finished, the finished test conditions and the corresponding test results can be known clearly only by calling the test file.

PLL lock-in condition, calculation of output frequency:

as shown in fig. 4, the logic analyzer sampling file is easy to determine the PLL locking condition, and checks the locked output signal, and if a low level appears, it is determined that the PLL is not locked, otherwise, it is determined that the PLL enters a locked state. During frequency analysis, the time of each period of the output signal is calculated, the maximum 10% and the minimum 10% of the data are discarded, the rest 80% of the data are averaged, then the 80% of the data are compared with the average value, if the difference between the data and the average value exceeds 10%, the frequency of the output signal in the path is considered to be unstable, otherwise, the frequency value of the output signal is calculated according to the average value.

Calculation of the PLL duty cycle:

in the analysis of the sampling file of the logic analyzer, the PLL locking condition and the output frequency are analyzed, and when the PLL is in a locking state and the frequency output is normal, the duty ratio analysis is carried out. And during duty ratio analysis, calculating the duty ratio of each period of the output signal, discarding the maximum 10% and the minimum 10% of the data, averaging the rest 80% of the data, comparing the 80% of the data with the average value, and if the difference between the data and the average value exceeds 10%, determining that the duty ratio of the output signal in the path is unstable, otherwise, taking the average value as the duty ratio value of the output signal in the path.

Calculation of the PLL phase:

in the analysis of the sampling file of the logic analyzer, the PLL locking condition and the output frequency are analyzed, and when the PLL is in a locking state and the frequency output is normal, the phase analysis of the output signal is performed. During phase analysis, the phase of each period of the output signal is calculated, the maximum 10% and the minimum 10% of the data are discarded, the rest 80% of the data are averaged, the 80% of the data are compared with the average value, if the difference between the data and the average value exceeds 10%, the phase of the output signal is considered to be unstable, otherwise, the average value is used as the phase value of the output signal.

The phase testing and calculating method for each cycle is exemplified below, and the phase of c0 and c1 is tested by taking e0 as a reference.

(1) First, the frequencies of c0, c1, and e0 are set to 2 times the input frequency, the phases of c0, c1, and e0 are all set to 0 °, and the PLL output waveform is shown in fig. 5.

(2) Find a rising edge of e0, find the first rising edge of c0, c1 backward respectively, the time is t1, t2 respectively.

(3) Then, the frequencies of c0, c1, and e0 are set to 2 times the input frequency, the phases of c0 and c1 are set to 90 °, the phase of e0 is set to 0 °, and the PLL output waveform is as shown in fig. 6.

(4) Find a rising edge of e0, find the first rising edge of c0, c1 backward respectively, the time is t3, t4 respectively.

(5) The times of T1, T2, T3, T4, and the periods T1 for c0, T2 for c1 are easily calculated from the logic analyzer sample file.

(6) The phase calculation method of c0 is as follows:

if t3-t1<0, then the phase of c0 is:

PhaseC0 360 ° × (T3-T1+ T1)/T1 equation (1)

If t3-t1>0, then the phase of c0 is:

PhaseC0 ═ 360 ° × (T3-T1)/T1 equation (2)

(7) The phase calculation method of c1 is as follows:

if t4-t2<0, then the phase of c1 is:

phaseC1 ═ 360 ° × (T4-T2+ T2)/T2 equation (3)

If t4-t2>0, then the phase of c1 is:

phaseC1 ═ 360 ° × (T4-T2)/T2 equation (4)

The present invention is not limited to the above embodiments, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention are included in the scope of the claims of the present invention which are filed as the application.

Claims

1. A test system for an FPGA PLL IP core, comprising: the device comprises a circuit board to be tested, and a signal source and a PC (personal computer) which are respectively connected with the circuit board to be tested; the PC is also connected with a signal source; the FPGA chip to be tested is arranged on the circuit board to be tested;

2. The test system of claim 1, wherein the test bit stream code comprises:

3. The test system of claim 1, wherein the circuit board under test comprises a plurality of interfaces through which a plurality of FPGA chips under test can be mounted and which pass input and output signals of the FPGA chips under test.

4. The test system of claim 1, wherein the test case is a plurality of, each based on an input-output frequency range, a duty cycle, and a phase setting of the PLL.

5. The test system of claim 1, further comprising a logic analyzer; the circuit board to be tested is connected with a PC through the logic analyzer;

6. The test system of claim 1, further comprising a power supply;

7. A method of testing an FPGA PLL IP core, comprising:

and the PC machine analyzes the output signal to complete the test.

8. The test method of claim 7, wherein the test bitstream code comprises:

9. The method of claim 8, wherein when the test bit stream code is a test bit stream code for frequency testing, the PC analyzes the output signal to complete the test, comprising:

the PC calculates the time of each period of the output signal;

calculating a time average value according to the time of each period;

10. The method of claim 9, wherein when the test bit stream code is a bit stream code for a placeholder test, the PC analyzes the output signal to complete the test, comprising:

the duty ratio of each period of the output signal of the PC;

11. The method of claim 9, wherein when the test bit stream code is a test bit stream code for phase test, the PC analyzes the output signal to complete the test, comprising:

the PC calculates the phase of each period of the output signal;

calculating a phase average value according to the phase of each period;

12. The test method of claim 11, wherein the calculating of the phase comprises:

13. The method as claimed in claim 8, wherein the PC generating the test bit stream code based on the predetermined test case comprises: