CN116859210A

CN116859210A - Communication chip reliability test method, device and system

Info

Publication number: CN116859210A
Application number: CN202310576272.5A
Authority: CN
Inventors: 曲晨冰; 王乃晔; 侯波; 王力纬; 孙宸; 恩云飞; 黄云; 路国光
Original assignee: China Electronic Product Reliability and Environmental Testing Research Institute
Current assignee: China Electronic Product Reliability and Environmental Testing Research Institute
Priority date: 2023-05-19
Filing date: 2023-05-19
Publication date: 2023-10-10

Abstract

The application relates to a method, a device and a system for testing the reliability of a communication chip, which are characterized in that an original clock waveform of the communication chip to be tested is obtained, a fault injection clock waveform is generated according to a preset fault test case list based on the original clock waveform, then the fault injection clock waveform is input to the communication chip to be tested, an output signal of the communication chip to be tested is obtained, and finally a test result of the communication chip to be tested is obtained by comparing the output signal with the preset output signal. According to the application, the fault injection clock waveform is automatically generated according to the preset fault test case list and injected into the communication chip to be tested, so that the functions of automatic control and monitoring of the whole fault injection process, automatic checking and judging of the test result, automatic analysis of the test data and the like are realized, and the convenience and the test efficiency of the reliability test of the communication chip are improved.

Description

Communication chip reliability test method, device and system

Technical Field

The present application relates to the field of communications chips, and in particular, to a method, an apparatus, and a system for testing reliability of a communications chip.

Background

In recent years, the communication chip is widely applied to the mobile communication, wireless internet and wireless data transmission industries, and is about to become the biggest application market of the global semiconductor chip industry in the beginning of the 21 st century. The CAN communication chip has a high application proportion as a communication chip with a high data processing capability requirement. However, at the same time, the CAN communication chip has higher requirements on clock frequency precision, stability performance and the like, and any unstable factor in the communication process CAN possibly have certain influence on the stability and the function of communication, so that the reliability of the CAN communication chip under the condition of abnormal clock is detected and verified, and the CAN communication chip has important significance for ensuring the safety and the reliability of the chip.

In the conventional manner, a clock fault injection technology is often adopted, and the operation capability of the chip in an abnormal state is checked by injecting a specific clock fault into a communication chip circuit. However, in the existing clock fault injection technology, the clock signal of the chip is manually interfered, so that the waveform of the clock signal is randomly changed to realize clock fault injection, and the reliability test result of the communication chip is not accurate enough.

Disclosure of Invention

In view of the foregoing, it is desirable to provide a communication chip reliability test method, apparatus, and system that can accurately perform reliability test on a communication chip.

In a first aspect, the present application provides a method for testing reliability of a communication chip. The method comprises the following steps:

acquiring an original clock waveform of a communication chip to be tested;

generating a fault injection clock waveform according to a preset fault test case list based on the original clock waveform;

inputting the fault injection clock waveform to the communication chip to be tested, and obtaining an output signal of the communication chip to be tested;

and comparing the output signal with a preset output signal to obtain a test result of the communication chip to be tested.

In one embodiment, the preset fault test case list includes at least one fault test case; generating a fault injection clock waveform according to a preset fault test case list based on the original clock waveform comprises the following steps:

Sequentially acquiring fault test cases in the preset fault test case list according to the sequence of the cases;

and generating a corresponding fault injection clock waveform based on the acquired case information of the fault test case.

In one embodiment, the case information of each fault test case includes a fault test type, a fault test parameter, and a fault test parameter value; the generating a corresponding fault injection clock waveform based on the obtained case information of the fault test case comprises the following steps:

generating a corresponding steady-state fault injection clock waveform based on the acquired fault test parameters and fault test parameter values of the fault test cases under the condition that the fault test types of the fault test cases are steady-state test types;

and under the condition that the fault test type of the fault test case is the burr test type, generating a corresponding burr fault injection clock waveform based on the acquired fault test parameters and fault test parameter values of the fault test case.

In one embodiment, in the case that the fault test type of the fault test case is a steady-state test type, the fault test parameter of the fault test case includes at least one of an amplitude and a frequency of a clock waveform;

And under the condition that the fault test type of the fault test case is a burr test type, the fault test parameters of the fault test case comprise at least one of amplitude, frequency, duty ratio and phase of a clock waveform.

In one embodiment, the inputting the fault injection clock waveform to the communication chip to be tested and obtaining the output signal of the communication chip to be tested includes:

inputting fault injection clock waveforms of the fault test cases to the communication chip to be tested, and obtaining output signals of the communication chip to be tested corresponding to the fault test cases;

comparing the output signal with a preset output signal to obtain a test result of the communication chip to be tested, wherein the test result comprises:

comparing the output signals of the communication chip to be tested corresponding to each fault test case with preset output signals to obtain comparison results corresponding to each fault test case;

and counting based on the comparison results corresponding to the fault test cases to obtain the test result of the communication chip to be tested.

Inputting the fault injection clock waveform to the communication chip to be tested according to preset cycle times, and obtaining output signals of the communication chip to be tested corresponding to the preset cycle times;

comparing the output signals of the communication chip to be tested corresponding to the preset cycle times with preset output signals to obtain comparison results corresponding to the preset cycle times;

and counting based on comparison results corresponding to the preset cycle times to obtain a test result of the communication chip to be tested.

In a second aspect, the application further provides a device for testing the reliability of the communication chip. The device comprises:

the original clock waveform acquisition module is used for acquiring an original clock waveform of the communication chip to be tested;

the fault injection clock waveform generation module is used for generating a fault injection clock waveform according to a preset fault test case list based on the original clock waveform;

the fault injection clock waveform injection module is used for inputting the fault injection clock waveform to the communication chip to be tested and obtaining an output signal of the communication chip to be tested;

And the output signal comparison module is used for comparing the output signal with a preset output signal to obtain a test result of the communication chip to be tested.

In a third aspect, the application further provides a communication chip reliability test system. The system comprises a clock detection module, a clock fault setting module, a fault injection control module and a fault injection detection module, wherein the clock detection module is connected with a communication chip to be detected and the clock fault setting module, the clock fault setting module is connected with the fault injection module and the fault injection control module, the fault injection control module is connected with the fault injection module and the fault injection detection module, and the fault injection module and the fault injection detection module are both connected with the communication chip to be detected;

the clock detection module is used for acquiring an original clock waveform of the communication chip to be detected;

the fault injection control module is used for controlling the clock fault setting module to generate a fault injection clock waveform according to a preset fault test case list based on the original clock waveform, controlling the fault injection module to input the fault injection clock waveform to the communication chip to be tested, and controlling the fault injection detection module to acquire an output signal of the communication chip to be tested;

The fault injection control module is further used for comparing the output signal with a preset output signal to obtain a test result of the communication chip to be tested.

In one embodiment, the clock detection module is an oscilloscope.

In one embodiment, the fault injection module is a signal generator.

According to the method, the device and the system for testing the reliability of the communication chip, the original clock waveform of the communication chip to be tested is obtained, the fault injection clock waveform is generated according to the preset fault test case list based on the original clock waveform, then the fault injection clock waveform is input to the communication chip to be tested, the output signal of the communication chip to be tested is obtained, and finally the test result of the communication chip to be tested is obtained by comparing the output signal with the preset output signal. According to the application, the fault injection clock waveform is automatically generated according to the preset fault test case list and injected into the communication chip to be tested, so that the functions of automatic control and monitoring of the whole fault injection process, automatic checking and judging of the test result, automatic analysis of the test data and the like are realized, and the convenience and the test efficiency of the reliability test of the communication chip are improved.

Drawings

FIG. 1 is a flow chart of a method for testing reliability of a communication chip according to an embodiment;

FIG. 2 is a flow chart illustrating steps for generating a fault injection clock waveform in one embodiment;

FIG. 3 is a flow chart illustrating steps for generating a steady-state fault injection clock waveform or a glitch fault injection clock waveform in one embodiment;

FIG. 4 is a flowchart illustrating steps for obtaining a test result of a communication chip under test in one embodiment;

FIG. 5 is a flowchart illustrating a step of obtaining a test result of a communication chip to be tested according to another embodiment;

FIG. 6 is a block diagram of a communication chip reliability test apparatus in one embodiment;

FIG. 7 is an internal block diagram of a computer device in one embodiment;

FIG. 8 is a system block diagram of a communication chip reliability test system in one embodiment;

FIG. 9 is a schematic diagram of a test board structure and fault injection connection of a communication chip under test in one embodiment;

FIG. 10 is a flow diagram of the creation of a fault injection clock waveform in one embodiment;

FIG. 11 is a waveform diagram of a fault injection clock waveform in one embodiment;

FIG. 12 is a schematic diagram illustrating analysis of reliability test results of a communication chip under test in one embodiment.

Detailed Description

The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.

As described in the background art, the communication chip is widely used in mobile communication, wireless internet and wireless data transmission industries, and is about to become the biggest application market of the global semiconductor chip industry in the beginning of the 21 st century. The CAN communication chip has a high application proportion as a communication chip with a high data processing capability requirement. However, at the same time, the CAN communication chip has higher requirements on clock frequency precision, stability performance and the like, and any unstable factor in the communication process CAN possibly have certain influence on the stability and the function of communication, so that the reliability of the CAN communication chip under the condition of abnormal clock is detected and verified, and the CAN communication chip has important significance for ensuring the safety and the reliability of the chip.

In the conventional manner, a clock fault injection technology is often adopted, and the operation capability of the chip in an abnormal state is checked by injecting a specific clock fault into a communication chip circuit. The current clock fault injection technology mainly comprises an analog voltage injection method, an artificial interference injection method, a clock generator injection method and the like. The analog voltage injection method is a technology for rapidly determining whether a clock fault exists in a chip by injecting an analog voltage signal on a clock line to simulate the clock fault of the chip. The artificial interference injection method is a method for realizing clock fault injection by manually interfering a chip clock signal so as to randomly change the frequency, the phase, the amplitude and other characteristics of the clock signal. The clock generator injection method is a method for implementing accurate control of a chip clock signal by modifying the frequency of a chip clock generator to perform clock fault injection, and can simulate more complicated clock fault conditions. However, the current clock fault injection technology basically uses manual interference to the clock signal of the chip, so that the waveform of the clock signal is randomly changed to realize clock fault injection, and the reliability test result of the communication chip is not accurate enough.

Based on the above, the communication chip reliability test method provided by the embodiment of the application CAN be applied to communication chips of the type such as CAN communication chips, and CAN effectively realize accurate design and injection of clock waveforms by applying a high-precision mathematical model and combining an automatic fault injection technology, thereby improving the accuracy and reliability of chip test.

In one embodiment, as shown in fig. 1, there is provided a communication chip reliability test method, including the following S200 to S800, wherein:

s200: and acquiring an original clock waveform of the communication chip to be tested.

Specifically, the communication chip to be tested characterizes the communication chip to be tested for reliability, the original clock waveform of the communication chip to be tested is the clock waveform output by the clock module of the communication chip to be tested, and the communication chip to be tested is characterized as the clock waveform before fault injection. The original clock waveform acquisition mode of the communication chip to be tested is not unique, and can be determined according to the position set by the clock module of the communication chip to be tested. For example, in the case that the clock module of the communication chip to be tested is built in the chip, the manner of obtaining the original clock waveform of the communication chip to be tested may be to use pins or the like to draw the original clock waveform from the clock pins of the communication chip to be tested. In the case that the clock module of the communication chip to be tested is external to the communication chip to be tested, the mode of obtaining the original clock waveform of the communication chip to be tested may be to directly lead out the original clock waveform of the external clock module through a circuit.

S400: generating a fault injection clock waveform according to a preset fault test case list based on the original clock waveform.

The preset fault test case list comprises at least one preset fault test case, wherein the preset fault test case is used for describing a reliability test task of the communication chip to be tested, and the preset fault test case list is a task set for performing the reliability test of the communication chip to be tested.

Specifically, the preset fault test case needs to include a policy to be used for performing reliability test on the communication chip to be tested, and may include a fault test type, a fault test parameter, a test parameter value range corresponding to the fault test parameter, and the like. The content of the preset fault test cases can be set according to the specific model of the communication chip to be tested, or the corresponding relation between the preset fault test case list and the specific model of the communication chip to be tested can be set in the clock fault setting module in advance, and then after the specific model of the communication chip to be tested is determined, the corresponding preset fault test case list can be directly extracted from the database. In addition, based on different preset fault test cases, the communication chip reliability test method provided by the application can be applied to the factory test stage of the communication chip to be tested to obtain the reliability test result of the communication chip to be tested. The method can also be applied to a test research stage of the communication chip to be tested, detect potential security threat of the communication chip to be tested, evaluate the security performance of the chip, and provide basis for improving the security of the communication chip to be tested, thereby better improving the reliability and stability of the communication chip to be tested so as to meet the requirements of different application scenes.

Further, the clock fault setting module may generate a fault injection waveform based on the extracted preset fault test cases in the preset fault test case list. It can be understood that a preset fault test case can correspondingly generate a fault injection clock waveform for implementing a corresponding reliability test task for the communication chip to be tested. The fault injection clock waveform can be obtained by carrying out waveform adjustment of corresponding parameters according to a preset fault test case on the basis of the original clock waveform so as to simulate possible fault conditions of the communication chip to be tested under the actual running condition. At this time, the processor of the communication chip to be tested is not completely turned off, but enters an undefined state or causes some type of undefined behavior, and the purpose of the present application is to monitor the change of behavior or performance of the communication chip to be tested.

S600: and inputting the fault injection clock waveform to the communication chip to be tested, and obtaining an output signal of the communication chip to be tested.

Correspondingly, the mode of inputting the fault injection clock waveform to the communication chip to be tested can also be determined according to the position set by the clock module of the communication chip to be tested. For example, in the case where the clock module of the communication chip to be tested is built in the chip, after the connection line of the clock module of the communication chip to be tested is cut off, a fault injection clock waveform may be input from the clock pin of the communication chip to be tested to the communication chip to be tested by using a pin or the like. In the case that the clock module of the communication chip to be tested is external to the communication chip to be tested, the fault injection module provided by the application can be directly inserted and connected between the external clock module of the communication chip to be tested and the clock pin, and after the original clock waveform is obtained, the fault injection module can directly generate the fault injection clock waveform according to a preset fault test case list based on the original clock waveform and then input the fault injection clock waveform to the communication chip to be tested through the clock pin.

Further, after the fault injection clock waveform is input to the communication chip to be tested, the communication test can be performed on the communication chip to be tested, so that an output signal of the communication chip to be tested is obtained, and a data base is provided for obtaining a test result of the communication chip to be tested. The output signal of the communication chip to be tested can be obtained from a communication signal output pin of the communication chip to be tested, and the output signal can represent the communication behavior or the communication performance of the communication chip to be tested.

S800: and comparing the output signal with a preset output signal to obtain a test result of the communication chip to be tested.

Specifically, the preset output signal represents an output signal of the communication chip to be tested in a normal communication state, and the output signal can be stored in the fault injection control module in advance. And the fault injection control module can compare the actual output signal of the communication chip to be tested with a preset output signal to obtain a test result of the communication chip to be tested, namely, judge whether the communication behavior or the communication performance of the communication chip to be tested is good or bad.

According to the communication chip reliability test method, the original clock waveform of the communication chip to be tested is obtained, the fault injection clock waveform is generated according to the preset fault test case list based on the original clock waveform, then the fault injection clock waveform is input to the communication chip to be tested, the output signal of the communication chip to be tested is obtained, and finally the test result of the communication chip to be tested is obtained by comparing the output signal with the preset output signal. According to the application, the fault injection clock waveform is automatically generated according to the preset fault test case list and injected into the communication chip to be tested, so that the functions of automatic control and monitoring of the whole fault injection process, automatic checking and judging of the test result, automatic analysis of the test data and the like are realized, and the convenience and the test efficiency of the reliability test of the communication chip are improved.

In one embodiment, as shown in fig. 2, S400 includes S420 to S440, wherein:

s420: sequentially acquiring fault test cases in a preset fault test case list according to the sequence of the cases. The sequence of the cases is that the sequence of the fault test cases in the fault test case list is preset, and it can be understood that the sequence can be adjusted according to the actual content of the fault test cases and the specific model of the communication chip to be tested in the actual test process.

S440: and generating a corresponding fault injection clock waveform based on the acquired use case information of the fault test case.

The case information of the fault test case represents a strategy to be used for reliability test of the communication chip to be tested, for example, a parameter to be tested can be represented, and a test range of the parameter can be represented. The case information of the fault test case can be obtained based on fault configuration information, the fault configuration information can be obtained by configuration of technicians before each test, and the fault configuration information can also be pre-stored in a clock fault setting module.

Specifically, the fault configuration information may include a fault test type, a fault test parameter, and a test range value and an adjustment step corresponding to the fault test parameter, which are required to perform a reliability test on the communication chip to be tested. The fault test type is used for characterizing what type of test can be performed by the generated fault injection clock waveform, and may include a steady-state fault injection clock waveform, a glitch fault injection clock waveform, and the like. It can be understood that the test of the steady-state fault injection clock waveform can reflect whether the communication chip to be tested has an abnormal fault under the action of the long-time fault injection clock waveform, and the test of the burr fault injection clock waveform can reflect whether the communication chip to be tested has an abnormal fault under the action of the sudden fault injection clock waveform. In addition, the fault test parameters, that is, waveform parameters corresponding to the original clock waveform of the communication chip to be tested, may include waveform parameters such as frequency, amplitude, phase, duty cycle, and the like. The test range value and the adjusting step length corresponding to the fault test parameters are used for obtaining the fault test parameter value of the fault test parameters of each fault test case.

Further, the case information of each fault test case includes a fault test type, a fault test parameter, and a fault test parameter value. And then after obtaining the case information of the fault test case according to the fault configuration information, determining a target mathematical model for generating the fault injection clock waveform based on the fault test parameters in the obtained case information of the fault test case. For example, the clock fault setting module stores mathematical models of fault injection clock waveforms corresponding to waveform parameters such as frequency, amplitude, phase and duty cycle, when the fault test parameter in the obtained case information of the fault test case is frequency, the mathematical model corresponding to the frequency can be determined as a target mathematical model, and when the fault test parameter in the obtained case information of the fault test case is a combination of the parameters, for example, the combination of the frequency and the duty cycle, the mathematical model corresponding to the frequency and the duty cycle can be determined as target mathematical models. And inputting the fault test parameter values into the determined target mathematical model to calculate and generate corresponding fault injection clock waveforms.

It will be appreciated that the fault test type may be used to determine the waveform duration required for the fault injection clock waveform. In one embodiment, as shown in fig. 3, S440 includes S442 to S444, wherein:

S442: and under the condition that the fault test type of the fault test case is a steady-state test type, generating a corresponding steady-state fault injection clock waveform based on the acquired fault test parameters and fault test parameter values of the fault test case.

Specifically, under the condition that the fault test type of the fault test case is a steady-state test type, whether the communication chip to be tested has abnormal faults under the action of the long-time fault injection clock waveform is characterized, and a corresponding steady-state fault injection duration waveform is required to be generated. It can be understood that the steady-state fault injection clock waveform is a clock waveform with a waveform duration exceeding a period T of the original clock waveform by a preset multiple, where the preset multiple may be determined according to an actual test requirement, for example, may be a multiple of 500, 800, 1000 or 1200, and in this embodiment, the preset multiple is set to 1000.

Further, under the condition that the fault test type of the fault test case is a steady-state test type, a target mathematical model can be determined based on the fault test parameters of the obtained fault test case, and the fault injection clock waveform with the waveform duration exceeding the period T preset times of the original clock waveform is calculated and obtained by inputting the fault test parameter values into the target mathematical model.

S444: and under the condition that the fault test type of the fault test case is the burr test type, generating a corresponding burr fault injection clock waveform based on the acquired fault test parameters and fault test parameter values of the fault test case.

Specifically, under the condition that the fault test type of the fault test case is the burr test type, whether the communication chip to be tested has abnormal faults under the action of the sudden fault injection clock waveform is characterized, and then the corresponding burr fault injection clock waveform is required to be generated. It will be appreciated that the glitch fault injection clock waveform is a clock waveform in which a sudden change in waveform parameters occurs within one to two periods T of the original clock waveform, wherein the sudden change in waveform parameters may be a sudden rise or fall.

Further, under the condition that the fault test type of the fault test case is the burr test type, a target mathematical model can be determined based on the acquired fault test parameters of the fault test case, and the fault injection clock waveform with the waveform parameter mutation in one to two periods T of the original clock waveform is calculated after the fault test parameter values are input into the target mathematical model.

It will be appreciated that different fault test types may be adapted to different fault test parameters for better reliability test results. For example, in one embodiment, in the case where the fault test type of the fault test case is a steady-state test type, the fault test parameters of the fault test case include at least one of an amplitude and a frequency of the clock waveform. Under the condition that the fault test type of the fault test case is the burr test type, the fault test parameters of the fault test case comprise at least one of amplitude, frequency, duty cycle and phase of a clock waveform.

In one embodiment, S600 includes: and inputting the fault injection clock waveform of each fault test case to the communication chip to be tested, and obtaining the output signal of the communication chip to be tested corresponding to each fault test case.

Specifically, after generating the event injection clock waveform based on the case information of each fault test case, the generated fault injection waveform can be injected to the communication chip to be tested through the clock pin.

Further, after the fault injection clock waveform is input to the communication chip to be tested, the communication test can be performed on the communication chip to be tested, so that an output signal of the communication chip to be tested is obtained, and a data base is provided for obtaining a test result of the communication chip to be tested. It can be understood that when the types of fault tests are different, the time point of obtaining the output signal of the communication chip to be tested also needs to be correspondingly adjusted. For example, in the case that the fault test type of the fault test case is a steady-state test type, the output signal of the communication chip to be tested needs to be obtained after the duration exceeding the period T of the original clock waveform by a preset multiple. Under the condition that the fault test type of the fault test case is the burr test type, the output signal of the communication chip to be tested can be obtained after one to two periods T of the original clock waveform.

Correspondingly, in one embodiment, as shown in fig. 4, S800 includes the following S820 to S840, wherein:

s820: and comparing the output signals of the communication chip to be tested corresponding to each fault test case with preset output signals to obtain comparison results corresponding to each fault test case.

It can be understood that the preset output signal characterizes the output signal of the communication chip to be tested in the normal communication state, and then the fault injection control module can compare the actual output signal obtained by the communication test with the preset output signal according to the effect of each fault test case of the communication chip to be tested, so as to obtain the comparison result corresponding to each fault test case. The comparison result may be a representation of whether there is a difference between the actual output signal and the preset output signal, or whether there is a difference in the transmission content.

S840: and counting based on the comparison results corresponding to the fault test cases to obtain the test result of the communication chip to be tested. Specifically, when the comparison results corresponding to the fault test cases represent that the communication chip to be tested is still in a state capable of normal communication, the test result of the communication chip to be tested can be obtained to pass the reliability test. And when the comparison result corresponding to any fault test case represents that the communication chip to be tested is not in a state capable of normal communication, the test result of the communication chip to be tested can be obtained to be the failure reliability test.

In one embodiment, S600 includes: and inputting the fault injection clock waveform to the communication chip to be tested according to the preset cycle times, and obtaining output signals of the communication chip to be tested corresponding to the preset cycle times.

The preset cycle times represent the times of carrying out reliability test on the communication chip to be tested by the fault injection clock waveform correspondingly generated by the same fault test case. The parameter may be pre-stored by the tester after the fault injection module is configured, for example, in this embodiment, it may be set to 1000 times.

Specifically, after generating the event injection clock waveform based on the case information of each fault test case, the generated fault injection waveform can be injected to the communication chip to be tested through the clock pin. Further, after the fault injection clock waveform is input to the communication chip to be tested, the communication test can be performed on the communication chip to be tested, so that an output signal of the communication chip to be tested is obtained, and a data base is provided for obtaining a test result of the communication chip to be tested. It can be understood that after the output signal of the communication chip to be tested is obtained each time, the same fault injection clock waveform can be injected into the communication chip to be tested again and the output signal is obtained until the injection frequency meets the preset cycle frequency.

In this embodiment, by performing repeated tests multiple times based on the preset cycle number, stability and reliability of the reliability test result of the communication chip to be tested are improved. In addition, more test data and information can be obtained, so that parameter optimization in the production and test processes is assisted, and the communication capacity of the communication chip is more accurate and reliable.

Correspondingly, in one embodiment, as shown in fig. 5, S800 includes the following S830 to S850, wherein:

s830: and comparing the output signals of the communication chips to be tested corresponding to the preset cycle times with preset output signals to obtain comparison results corresponding to the preset cycle times. It can be understood that the preset output signal characterizes the output signal of the communication chip to be tested in the normal communication state, and then the fault injection control module can compare the actual output signal obtained by the communication test with the preset output signal according to the fault test cases of the communication chip to be tested in each preset cycle number, so as to obtain a comparison result corresponding to the fault test cases of each preset cycle number.

S850: and counting based on comparison results corresponding to the preset cycle times to obtain a test result of the communication chip to be tested. Specifically, when the comparison results corresponding to the fault test cases with preset cycle times represent that the communication chip to be tested is still in a state capable of normal communication, the test result of the communication chip to be tested can be obtained to pass the reliability test. And when the comparison result corresponding to the fault test case with any preset cycle number represents that the communication chip to be tested is not in a state capable of normal communication, the test result of the communication chip to be tested can be obtained to be failed in the reliability test.

It should be understood that, although the steps in the flowcharts related to the embodiments described above are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the flowcharts described in the above embodiments may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily performed sequentially, but may be performed alternately or alternately with at least some of the other steps or stages.

Based on the same inventive concept, the embodiment of the application also provides a communication chip reliability testing device for realizing the above related communication chip reliability testing method. The implementation of the solution provided by the device is similar to the implementation described in the above method, so the specific limitation in the embodiments of the device for testing the reliability of one or more communication chips provided below may be referred to the limitation of the method for testing the reliability of a communication chip hereinabove, and will not be repeated herein.

In one embodiment, as shown in fig. 6, there is provided a communication chip reliability test apparatus, comprising: the original clock waveform acquisition module 110, the fault injection clock waveform generation module 120, the fault injection clock waveform injection module 130, and the output signal comparison module 140, wherein:

an original clock waveform obtaining module 110, configured to obtain an original clock waveform of a communication chip to be tested;

the fault injection clock waveform generation module 120 is configured to generate a fault injection clock waveform according to a preset fault test case list based on an original clock waveform;

the fault injection clock waveform injection module 130 is configured to input a fault injection clock waveform to a communication chip to be tested, and obtain an output signal of the communication chip to be tested;

the output signal comparing module 140 is configured to compare the output signal with a preset output signal to obtain a test result of the communication chip to be tested.

In one embodiment, the preset fault test case list includes at least one fault test case;

the fault injection clock waveform generating module 120 is further configured to sequentially obtain fault test cases in a preset fault test case list according to a case sequence; and generating a corresponding fault injection clock waveform based on the acquired use case information of the fault test case.

In one embodiment, the case information of each fault test case includes a fault test type, a fault test parameter, and a fault test parameter value;

the fault injection clock waveform generating module 120 is further configured to generate a corresponding steady-state fault injection clock waveform based on the obtained fault test parameters and the fault test parameter values of the fault test case when the fault test type of the fault test case is a steady-state test type; and under the condition that the fault test type of the fault test case is the burr test type, generating a corresponding burr fault injection clock waveform based on the acquired fault test parameters and fault test parameter values of the fault test case.

In one embodiment, in the case where the fault test type of the fault test case is a steady-state test type, the fault test parameters of the fault test case adopted by the fault injection clock waveform generation module 120 include at least one of an amplitude and a frequency of the clock waveform; in the case that the fault test type of the fault test case is the glitch test type, the fault test parameters of the fault test case adopted by the fault injection clock waveform generation module 120 include at least one of the amplitude, the frequency, the duty cycle and the phase of the clock waveform.

In one embodiment, the fault injection clock waveform injection module 130 is further configured to input a fault injection clock waveform of each fault test case to the communication chip to be tested, and obtain an output signal of the communication chip to be tested corresponding to each fault test case;

the output signal comparison module 140 is further configured to compare an output signal of the communication chip to be tested corresponding to each fault test case with a preset output signal, so as to obtain a comparison result corresponding to each fault test case; and counting based on the comparison results corresponding to the fault test cases to obtain the test result of the communication chip to be tested.

In one embodiment, the fault injection clock waveform injection module 130 is further configured to input a fault injection clock waveform to the to-be-tested communication chip according to a preset cycle number, and obtain an output signal of the to-be-tested communication chip corresponding to each preset cycle number;

the output signal comparison module 140 is further configured to compare an output signal of the to-be-detected communication chip corresponding to each preset cycle number with a preset output signal to obtain a comparison result corresponding to each preset cycle number; and counting based on comparison results corresponding to the preset cycle times to obtain a test result of the communication chip to be tested.

The modules in the communication chip reliability test device can be all or partially realized by software, hardware and a combination thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.

In one embodiment, a computer device is provided, which may be a terminal, and the internal structure of which may be as shown in fig. 7. The computer device includes a processor, a memory, an input/output interface, a communication interface, a display unit, and an input means. The processor, the memory and the input/output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input/output interface. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The input/output interface of the computer device is used to exchange information between the processor and the external device. The communication interface of the computer device is used for carrying out wired or wireless communication with an external terminal, and the wireless mode can be realized through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. The computer program, when executed by a processor, implements a method for testing the reliability of a communication chip. The display unit of the computer device is used for forming a visual picture, and can be a display screen, a projection device or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, can also be a key, a track ball or a touch pad arranged on the shell of the computer equipment, and can also be an external keyboard, a touch pad or a mouse and the like.

It will be appreciated by those skilled in the art that the structure shown in FIG. 7 is merely a block diagram of some of the structures associated with the present inventive arrangements and is not limiting of the computer device to which the present inventive arrangements may be applied, and that a particular computer device may include more or fewer components than shown, or may combine some of the components, or have a different arrangement of components.

In one embodiment, a computer device is provided comprising a memory having a computer program stored therein and a processor that implements the steps of the method described above when the computer program is executed.

In one embodiment, a computer readable storage medium is provided having a computer program stored thereon, which when executed by a processor, implements the steps of the above method.

In an embodiment, a computer program product is provided comprising a computer program which, when executed by a processor, implements the steps of the above method.

In one embodiment, a communication chip reliability test system is provided to implement the communication chip reliability test method described in any of the above embodiments, and the specific limitations of one or more embodiments of the communication chip reliability test system provided below may form the limitations of the communication chip reliability test method described above. As shown in fig. 8, the system includes a clock detection module 110, a clock fault setting module 120, a fault injection module 130, a fault injection control module 140 and a fault injection detection module 150, wherein the clock detection module 110 is connected with a communication chip to be tested and the clock fault setting module 120, the clock fault setting module 120 is connected with the fault injection module 130 and the fault injection control module 140, the fault injection control module 140 is connected with the fault injection module 130 and the fault injection detection module 150, and the fault injection module 130 and the fault injection detection module 150 are both connected with the communication chip to be tested; the clock detection module 110 is configured to obtain an original clock waveform of a communication chip to be detected; the fault injection control module 140 is configured to control the clock fault setting module 120 to generate a fault injection clock waveform according to a preset fault test case list based on the original clock waveform, control the fault injection module 130 to input the fault injection clock waveform to the communication chip to be tested, and control the fault injection detection module 150 to obtain an output signal of the communication chip to be tested; the fault injection control module 140 is further configured to compare the output signal with a preset output signal to obtain a test result of the communication chip to be tested.

Specifically, the clock detection module 110 may acquire an original clock waveform of the communication chip to be tested using pins. The fault injection control module 140 is configured to control the clock fault setting module 120 to generate a fault injection clock waveform according to a preset fault test case list based on the original clock waveform. It can be understood that a preset fault test case can correspondingly generate a fault injection clock waveform for implementing a corresponding reliability test task for the communication chip to be tested. The fault injection clock waveform can be obtained by carrying out waveform adjustment of corresponding parameters according to a preset fault test case on the basis of the original clock waveform so as to simulate possible fault conditions of the communication chip to be tested under the actual running condition. At this time, the processor of the communication chip to be tested is not completely turned off, but enters an undefined state or causes some type of undefined behavior, and the purpose of the present application is to monitor the change of behavior or performance of the communication chip to be tested.

Further, the fault injection control module 140 is further configured to control the fault injection module 130 to input a fault injection clock waveform to the communication chip under test. And further performs communication test on the communication chip to be tested and controls the fault injection detection module 150 to obtain an output signal of the communication chip to be tested. The preset output signal represents an output signal of the communication chip to be tested in a normal communication state, and may be stored in the fault injection control module 140 in advance. The fault injection control module 140 can compare the actual output signal of the communication chip to be tested with the preset output signal to obtain the test result of the communication chip to be tested, i.e. determine whether the communication behavior or the communication performance of the communication chip to be tested is good or bad.

In this embodiment, an original clock waveform of a communication chip to be tested is obtained, a fault injection clock waveform is generated according to a preset fault test case list based on the original clock waveform, then the fault injection clock waveform is input to the communication chip to be tested, an output signal of the communication chip to be tested is obtained, and finally a test result of the communication chip to be tested is obtained by comparing the output signal with a preset output signal. According to the application, the fault injection clock waveform is automatically generated according to the preset fault test case list and injected into the communication chip to be tested, so that the functions of automatic control and monitoring of the whole fault injection process, automatic checking and judging of the test result, automatic analysis of the test data and the like are realized, and the convenience and the test efficiency of the reliability test of the communication chip are improved.

In one embodiment, taking the communication chip to be tested as a CAN communication chip, the clock detection module as an oscilloscope and the fault injection module as a signal generator as an example, the steps of the reliability test of the communication chip to be tested, which are applied to the test research stage of the communication chip to be tested, are explained for detecting the potential security threat of the communication chip to be tested, and evaluating the security performance of the chip, thereby providing a basis for improving the security of the communication chip to be tested, and further improving the reliability and stability of the communication chip to be tested so as to meet the requirements of different application scenes. Specifically, the method comprises the following steps:

Step 1: and determining capturing and injecting positions of the original clock waveform according to the actual circuit condition of the CAN communication chip to be tested. For example, a clock pin as shown in fig. 9.

Step 2: and capturing an original clock waveform of the CAN communication chip to be tested by using an oscilloscope, and importing the captured original clock waveform into a fault injection control module containing arbitrary waveform generator software for further editing so as to simulate the test chip under the real condition.

Step 3: specific fault configuration information is set according to the characteristics of the CAN communication chip to be tested, various fault injection clock waveforms are preset, and the clock waveforms are described by adopting a high-precision mathematical model for all possible parameters which CAN influence the normal operation of the CAN communication chip, so that the pertinence of fault injection and the accuracy of functional test are improved, and the accurate calculation and optimization of the waveforms are realized.

Wherein the abnormal waveform of the clock frequency adopts f (t) =f _nom (1+ksin(2πf _mod t)) calculation, f _nom Represents the nominal frequency of the clock, k represents the amplitude of the frequency anomaly, f _mod The modulation frequency representing the frequency variation, t representing time. By setting k and f _mod To control the amplitude and modulation frequency of the frequency anomaly. Voltage and phase anomaly waveform adoptionCalculation of V _nom Represents the rated level of the clock, A represents the amplitude of the voltage abnormality, f _clk Represents clock frequency, +.>Indicating the phase of the voltage anomaly. By setting A and +.>To control the amplitude and phase of the voltage anomaly. The clock burr duty cycle setting waveform adopts f (t) =f _nom +∑(a _k t ^k )+∑(b _k sin(2πkf _mod t)) (d+1) calculation, a _k And b _k Representing coefficients in the polynomial function and the sine function, respectively, d representing the adjustment coefficient of the duty cycle. The duty cycle of the clock glitch is controlled by varying the value of d.

The amplitude, frequency, phase, duty ratio and the like of the clock signal of the CAN communication chip are reduced or increased in a planned way through any waveform generator software, steady-state fault waveform injection, clock voltage burr injection, clock frequency burr injection and the like are comprehensively carried out to simulate possible fault conditions under actual operation conditions, so that a processor cannot be completely shut down, but enters an undefined state or causes undefined behavior of a certain type, the behavior or performance change of the undefined state is monitored, and a fault injection control module creates a waveform for a time Zhong Maoci as shown in fig. 10.

1) Steady state test: the waveform amplitude and frequency are increased or decreased by arbitrary waveform generator software based on the imported original clock waveform. The clock glitch waveform setting is shown in fig. 11, where clock is a normal clock waveform captured by an oscilloscope, and notch clock1 is a clock waveform after changing the amplitude of the clock voltage, and notch clock2 is a clock waveform after changing the clock frequency, and the steady-state fault injection clock waveform is injected into the signal generator for a time sufficient to simulate a fault that may occur when the chip operates in an abnormal situation for a long time.

2) The clock voltage amplitude fault setting method comprises the following steps: the clock voltage of the CAN communication chip to be tested is reduced or increased temporarily, the instability and the misoperation of the chip CAN be caused, therefore, any signal generator software is used, the normal clock waveform shown in the clock of fig. 11 is increased or reduced in the normal voltage working range of the CAN communication chip through a mathematical calculation tool, the clock voltage burr waveform shown in the glitch clock3 is obtained, and the fault signal is injected into the signal generator to simulate the clock burr fault caused by the clock voltage change in the chip.

3) Clock frequency glitch test: the clock signal has instantaneous frequency fluctuation, which may cause abnormal behavior of the CAN communication chip to be tested. In order to consider the influence of the fault frequency and time of the clock frequency burr on the CAN communication chip to be tested, adding part of abnormal clock frequency burr in the clock frequency of the normal operation of the CAN communication chip and adjusting the duty ratio of the abnormal clock burr. Presetting clock glitch frequency according to chip clock parameter information, calculating the clock period length corresponding to the preset clock frequency, editing the normal clock waveform shown in the clock of fig. 11 by using any signal generator software through an editor, and increasing or decreasing the frequency of part of the clock waveform on the basis of the normal working frequency of the CAN communication chip to obtain the clock frequency glitch waveform shown in the glitch clock 4.

The clock frequency burr waveform in a period of time is selected on the basis, the duty ratio of the abnormal clock burr is adjusted through the editor, and then a continuous method is adopted to continuously output clock frequency burr signals, so that the clock frequency burr can be tested more comprehensively through a plurality of influence parameters.

4) Clock frequency, voltage and duty ratio burr comprehensive test: in order to more comprehensively perform clock burr test, all the influence parameters are combined for test so as to verify the sensitivity of the chip to each influence parameter and the influence of interaction among the influence parameters on the clock burr, thereby providing a beneficial reference for the design and optimization of the chip. And using any signal generator software, editing a normal clock waveform through a mathematical model, and simultaneously changing parameters such as clock frequency, voltage amplitude, duty ratio and the like. The clock glitch waveform shown in the glitch clock5 in fig. 11 is obtained, and the influence of a plurality of influence parameters on the clock frequency glitch can be more comprehensively tested by continuously adjusting the model control parameters.

Step 4: the signal generator is used for importing the calculated fault injection clock waveform, a complete clock waveform injection method is developed by utilizing an automation technology, automatic control and monitoring of the whole injection process are realized, the waveform is automatically selected from fault injection equipment, the waveform is switched, and fault injection is carried out at the determined clock signal position. And an automatic data storage analysis method is provided, so that the functions of automatic checking and judging of test results, automatic analysis of test data and the like are realized.

Step 5: and carrying out communication test on the CAN communication chip to be tested, and screening out parameters which have functional influence on the CAN communication chip to be tested.

Step 6: and setting a test threshold range for the influence parameters of the CAN communication chip to be tested, and setting preset cycle times to perform multiple communication tests. For example, when clock fault injection test is performed, the fault injection control module is ensured to transmit data for more than 1000 times to perform a large number of tests, and the accuracy and reliability of the tests are improved. And repeated tests are carried out for a plurality of times to verify the stability of the test result and improve the credibility of the test result. In addition, more test data and information are obtained through a large number of tests, so that test parameters are optimized in the test process, and the test result is more accurate and reliable.

Step 7: and automatically detecting and analyzing the digital signal after fault injection to obtain accurate and effective influence parameters and fault parameter ranges, thereby completing functional safety test of the CAN communication chip to be tested.

According to the clock fault waveform setting method, through a large number of fault injection tests, the functional safety test result of the CAN communication chip to be tested is obtained as shown in figure 12. The clock frequency is in the range of 15.79-16.2 MHz, and under the clock jitter condition that the burr occupies less than 20% of the clock period, the safety of the chip is not easy to be influenced. The error rate is higher and higher with the increase and decrease of the clock frequency on the basis of the normal working frequency and with the increase of the ratio of the burrs to the clock period until the transmission is impossible. In addition, the chip is insensitive to clock voltage.

The test shows that the communication chip reliability test system can cover a large enough clock burr test range; according to the working characteristics of the chip data communication pins and the time sequence of the test circuit, fault injection waveforms with multiple influencing parameters are set, and the coverage is comprehensive. The method is based on a prototype system, is closer to an actual operation result than a simulation-based method, and improves accuracy to a great extent. In addition, the hardware fault injection method has the characteristics of high system failure speed, short data acquisition time, easy control of fault injection position and duration time and the like, and the target system is hardly affected. Through the test, the influence of clock voltage burrs, clock burr frequency, clock burr duty ratio and the like on the data transmission result can be observed, and the influence factors are comprehensively covered. Meanwhile, automatic testing and automatic checking are adopted to judge the data transmission result, and accuracy, convenience and testing efficiency are all improved.

It should be noted that, the user information (including but not limited to user equipment information, user personal information, etc.) and the data (including but not limited to data for analysis, stored data, presented data, etc.) related to the present application are information and data authorized by the user or sufficiently authorized by each party, and the collection, use and processing of the related data need to comply with the related laws and regulations and standards of the related country and region.

Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, database, or other medium used in embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high density embedded nonvolatile Memory, resistive random access Memory (ReRAM), magnetic random access Memory (Magnetoresistive Random Access Memory, MRAM), ferroelectric Memory (Ferroelectric Random Access Memory, FRAM), phase change Memory (Phase Change Memory, PCM), graphene Memory, and the like. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory, and the like. By way of illustration, and not limitation, RAM can be in the form of a variety of forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), and the like. The databases referred to in the embodiments provided herein may include at least one of a relational database and a non-relational database. The non-relational database may include, but is not limited to, a blockchain-based distributed database, and the like. The processor referred to in the embodiments provided in the present application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic unit, a data processing logic unit based on quantum computing, or the like, but is not limited thereto.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The foregoing examples illustrate only a few embodiments of the application and are described in detail herein without thereby limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of the application should be assessed as that of the appended claims.

Claims

1. A method for testing the reliability of a communication chip, the method comprising:

acquiring an original clock waveform of a communication chip to be tested;

2. The method of claim 1, wherein the list of pre-set fault test cases comprises at least one fault test case; generating a fault injection clock waveform according to a preset fault test case list based on the original clock waveform comprises the following steps:

3. The method of claim 2, wherein the case information for each of the fault test cases includes a fault test type, a fault test parameter, and a fault test parameter value; the generating a corresponding fault injection clock waveform based on the obtained case information of the fault test case comprises the following steps:

4. The method of claim 3, wherein the step of,

under the condition that the fault test type of the fault test case is a steady-state test type, the fault test parameters of the fault test case comprise at least one of the amplitude and the frequency of a clock waveform;

5. The method of claim 2, wherein inputting the fault injection clock waveform to the communication chip under test and obtaining an output signal of the communication chip under test comprises:

6. The method according to any one of claims 1 to 5, wherein inputting the fault injection clock waveform to the communication chip under test and obtaining an output signal of the communication chip under test includes:

7. A communication chip reliability test apparatus, the apparatus comprising:

8. The system is characterized by comprising a clock detection module, a clock fault setting module, a fault injection control module and a fault injection detection module, wherein the clock detection module is connected with a communication chip to be tested and the clock fault setting module, the clock fault setting module is connected with the fault injection module and the fault injection control module, the fault injection control module is connected with the fault injection module and the fault injection detection module, and the fault injection module and the fault injection detection module are both connected with the communication chip to be tested;

9. The system of claim 8, wherein the clock detection module is an oscilloscope.

10. The system of claim 8, wherein the fault injection module is a signal generator.