CN101793941A

CN101793941A - Creation method of FPGA (Field Programmable Gate Array ) configuration file

Info

Publication number: CN101793941A
Application number: CN200910200706A
Authority: CN
Inventors: 叶守银; 张志勇; 祁建华; 徐惠
Original assignee: Sino IC Technology Co Ltd
Current assignee: Sino IC Technology Co Ltd
Priority date: 2009-12-24
Filing date: 2009-12-24
Publication date: 2010-08-04
Anticipated expiration: 2029-12-24
Also published as: CN101793941B

Abstract

The invention discloses a creation method of an FPGA configuration file, comprising the following steps of: (1) establishing a new design file by using a software tool; (2) manually realizing at least one logic design of a configurable logic module or an input and output module; (3) creating a bit stream file of the configurable logic module or the input and output module; and (4) extracting and shifting the bit stream file in step (3) into the FPGA configuration file by using special software for analyzing bit stream data. The invention avoids a test configuration design from being limited by some design rules and directly processes the configuration file to achieve the purpose of rapidly creating the test configuration file.

Description

The generation method of FPGA configuration file

Technical field

The present invention relates to a kind of field programmable gate array method of testing of (Field Programmable Gate Array is called for short FPGA), be specifically related to a kind of generation method of testing the FPGA configuration file of usefulness.

Background technology

The FPGA field programmable device is widely used in fields such as communication, automobile, aviation, national defence.Utilization FPGA development product finally all can generate the bit stream configuration file with specific function, and (FPGA need read configuration data from the outside when starting, this file that comprises configuration data is referred to as configuration file), configuration file is downloaded among the FPGA when system start-up, makes FPGA have our desired specific function.The generation of configuration file is the key of FPGA product development.FPGA Products Development process generally has: several flow processs such as generation of design input, emulation, comprehensive, automatic placement and routing, configuration file.Finishing of this a series of actions need be by means of the dedicated development tool system, as the ISE of Xilinx company, the QuartusII of altera corp, the development systems such as IspLever of Lattice company.

FPGA is a kind of electric erasable, the electrically rewritable device, though similar with the standard gate array, have special architecture and logical block, the method for testing of general DLC (digital logic circuit) does not fit into the test of fpga chip.The FPGA electric erasable, the architecture that the electrically rewritable device is special, make completeness test and fault analysis, the assessment of failure of circuit become complicated more, because its internal structure has highly repeatability, thereby measurability is very strong, have very high difficulty but will finish the high fault coverage test, must carry out accurate design structure, make each test profile have the highest testing efficiency test file by limited test configurations.The limitation that conventional automatic placement and routing is subjected to the FPGA design rule can not satisfy this designing requirement, must seek a kind of test profile of FPGA efficiently generation method.

As shown in Figure 1, the design of traditional F PGA configuration file generates, and need carry out design synthesis then according to test request at first through repeatedly design input, functional simulation, modification optimization, design realizes processes such as (automatic placement and routings), thereby the generation configuration file carries out the FPGA test.Input is designed in the place of workload maximum exactly in this flow process, error message can constantly appear in simulation process, need to optimize step by step to revise, each step in the process all must meet the various rules of FPGA design, in case violated these rules, just can't proceed, this rule has been limited to the design of FPGA test profile, the design of test profile is the logical design of carrying out at the fpga chip selftest, rather than Application Design.

Summary of the invention

Technical matters to be solved by this invention provides a kind of generation method of FPGA configuration file, and it need can not realize the quick generation of configuration file by the complicated approach of tradition, is mainly used in the generation of the test profile of fpga chip.

In order to solve above technical matters, the invention provides a kind of generation method of FPGA configuration file, comprise the steps:

(1) sets up new design document with Software tool;

(2) manually realize the logical design of at least one configurable logic blocks (CLB) or input/output module (IO);

(3) bit stream file of described configurable logic blocks of generation or input/output module;

(4) with bit stream data dedicated analysis software the described bit stream file of step (3) is extracted and moves in the described FPGA configuration file.

Preferably, the generation method of FPGA configuration file of the present invention, step (4) are according to data and resource mapping relation, extract and move with the mode of duplicating, and make each resource among the FPGA meet test request.

Preferably, the generation method of FPGA configuration file of the present invention, described configuration file is a test profile.

The present invention has avoided the restriction of some design rules to the test configurations design, directly configuration file is handled, and reaches the purpose of quick generation test profile.

Description of drawings

Below in conjunction with the drawings and specific embodiments the present invention is described in further detail.

Fig. 1 is the process flow diagram that prior art generates the FPGA configuration file;

Fig. 2 is the process flow diagram of the generation method of FPGA configuration file of the present invention;

Fig. 3 is a synoptic diagram of setting up new design document in the embodiments of the invention with the FPGA edit tool;

Fig. 4 is a synoptic diagram of manually realizing the logical design of CLB in the embodiments of the invention;

Fig. 5 is the synoptic diagram that generates the CLB bit stream file in the embodiments of the invention;

Fig. 6 is the synoptic diagram that carries out the CLB configuration extraction in the embodiments of the invention with bit stream data dedicated analysis software;

Fig. 7 carries out the synoptic diagram that the CLB configuration is moved with bit stream data dedicated analysis software in the embodiments of the invention;

Fig. 8 is a synoptic diagram of preserving the final test configuration file in the embodiments of the invention.

Embodiment

In order to improve test failure coverage rate and the calculating of being convenient to fault coverage, the modular arrangements mode is taked in the design of FPGA test configurations, in a configuration file, design the configuration module of at least a CLB or IO, in whole FPGA, repeat such configuration module (we know that FPGA comprises many identical in structure CLB matrixes and IO matrix), the test coverage of the configurable resource of each CLB or IO is easy to through calculating, and the test coverage of the configurable resource of so whole FPGA also is easy to calculate.Present technique is by one or a few CLB in the extraction configuration file or the configuration data of IO, on the CLB module of under the help of bit stream data dedicated analysis software it being moved any appointment of FPGA, re-construct the FPGA configuration file, can generate new test configurations fast like this.

Be illustrated in figure 2 as the flow process of designing and developing of the present invention, mainly comprise: analytical test requires to set up configuration file; Manually carry out modular design such as CLB, IO; Carry out data extract and move (will carry out), finish configuration file, can carry out the FPGA test at last as required according to data and resource mapping relation.

Method of the present invention has been avoided the restriction of some design rules to the test configurations design, reaches the purpose of quick generation test profile.Directly with test request manual connection and generation CLB or IO modules configured data of realizing in FPGA edit tool (EDITOR), the means of moving of duplicating by bit stream data dedicated analysis software, obtain the test profile of all configurable resources among the FPGA, and generate test patterns.

See also Fig. 3 to a specific embodiment shown in Figure 8.Comprise the steps:

(1) sets up the design document (as Fig. 3) that new name is called XC2S100 with FPGA EDITOR.

(2) manually realize the logical design (as Fig. 4) of CLB.

(3) generate the CLB bit stream file, this document name is called CLBR1C15.Bit (as Fig. 5).

(4) carry out the CLB configuration extraction and move with bit stream data dedicated analysis software.Specifically comprise:

Open the step (as Fig. 6) of CLBR1C15.Bit bit stream file;

The CLB data field is chosen in click, according to data and resource mapping relation, extracts or move the CLB data with the mode of copy, makes each resource among the FPGA meet the step (as Fig. 7) of the requirement of expectation.

(5) preserve definitive document and generate new test profile test-bitstream.bit (as Fig. 8).

The present invention has following characteristics:

(1) accurately designed the CLB configuration module;

(2) mapping relations of CLB module and IO module and configuration file have been taken into full account.

(3) avoided of the restriction of some design rules, directly configuration file has been handled, reached the purpose of quick generation test profile the test configurations design.

Claims

1. the generation method of a FPGA configuration file is characterized in that, comprises the steps:

(1) sets up new design document with Software tool;

(2) manually realize the logical design of at least one configurable logic blocks or input/output module;

2. the generation method of FPGA configuration file as claimed in claim 1 is characterized in that, step (4) is according to data and resource mapping relation, extracts and moves with the mode of duplicating, and makes each resource among the FPGA meet test request.

3. the generation method of FPGA configuration file as claimed in claim 1 or 2 is characterized in that, described configuration file is a test profile.