CN101793941B - Creation method of FPGA (Field Programmable Gate Array ) configuration file - Google Patents

Abstract

The invention discloses a method for generating an FPGA configuration file, comprising the following steps: (1) establishing a new design file with a software tool; (2) manually implementing the logic design of at least one configurable logic module or input-output module; (3) ) generating the bit stream file of the configurable logic module or the input/output module; (4) extracting and moving the bit stream file described in step (3) into the FPGA configuration file with special analysis software for bit stream data. The invention avoids the limitation of some design rules on the test configuration design, directly processes the configuration files, and achieves the purpose of quickly generating the test configuration files.

Description

How to generate FPGA configuration files

technical field

The present invention relates to a method for testing a field programmable gate array (Field Programmable Gate Array, referred to as FPGA), in particular to a method for generating an FPGA configuration file for testing.

Background technique

FPGA field programmable devices are widely used in communication, automobile, aviation, national defense and other fields. Products developed using FPGA will eventually generate a bit stream configuration file with specific functions (the configuration data needs to be read from the outside when the FPGA is started, and this file containing configuration data is called a configuration file), and the configuration file is downloaded when the system starts Into the FPGA, so that the FPGA has the special functions we expect. The generation of configuration files is the key to FPGA product development. The development process of FPGA products generally includes several processes such as design input, simulation, synthesis, automatic layout and routing, and configuration file generation. The completion of this series of actions requires the help of special development tool systems, such as Xilinx's ISE, Altera's QuartusII, Lattice's IspLever and other development systems.

FPGA is an electrically erasable and electrically rewritable device. Although it is similar to a standard gate array, it has a special architecture and logic unit. The general digital logic circuit test method is not suitable for FPGA chip testing. The special architecture of FPGA electrically erasable and electrically rewritable devices makes the integrity test, fault analysis and fault evaluation of the circuit more complicated. Because its internal structure is highly repeatable, it is highly measurable, but it must be It is very difficult to complete the high fault coverage test through limited test configurations, and the test files must be precisely designed and constructed so that each test configuration file has the highest test efficiency. Conventional automatic placement and routing is limited by FPGA design rules and can no longer meet this design requirement, so an efficient FPGA test configuration file generation method must be sought.

As shown in Figure 1, the design generation of traditional FPGA configuration files requires repeated design input, function simulation, modification and optimization according to test requirements, and then design synthesis, design implementation (automatic layout and routing) and other processes to generate configuration files , for FPGA testing. The biggest workload in this process is the design input. During the simulation process, error messages will continue to appear, and it needs to be optimized and modified step by step. Each step in the process must comply with various rules of FPGA design. Once these rules are violated, the It is impossible to continue. This rule limits the design of the FPGA test configuration file. The design of the test configuration file is a logic design for the FPGA chip itself, not an application design.

Contents of the invention

The technical problem to be solved by the present invention is to provide a method for generating FPGA configuration files, which can realize the rapid generation of configuration files without traditional complicated approaches, and is mainly used in the generation of test configuration files for FPGA chips.

In order to solve the above technical problems, the invention provides a method for generating an FPGA configuration file, comprising the steps of:

(1) Create new design files with software tools;

(2) Manually implement the logic design of at least one configurable logic block (CLB) or input-output module (IO);

(3) generating the bit stream file of the configurable logic module or the input/output module;

(4) Extract and move the bit stream file described in step (3) into the FPGA configuration file with special analysis software for bit stream data.

Preferably, the generation method of FPGA configuration file of the present invention, step (4) is to extract and move with the mode of copying according to the mapping relation of data and resource, makes each resource in FPGA meet test requirement.

Preferably, in the method for generating FPGA configuration files of the present invention, the configuration files are test configuration files.

The invention avoids the limitation of some design rules on the test configuration design, directly processes the configuration files, and achieves the purpose of quickly generating the test configuration files.

Description of drawings

The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

Fig. 1 is the flow chart that prior art generates FPGA configuration file;

Fig. 2 is the flowchart of the generating method of FPGA configuration file of the present invention;

Fig. 3 is the schematic diagram that establishes new design file with FPGA editing tool in the embodiment of the present invention;

Fig. 4 is the schematic diagram of the logic design that realizes CLB manually in the embodiment of the present invention;

Fig. 5 is the schematic diagram that generates CLB bit stream file in the embodiment of the present invention;

Fig. 6 is a schematic diagram of extracting CLB configuration with special analysis software for bit stream data in an embodiment of the present invention;

Fig. 7 is a schematic diagram of moving CLB configuration with special analysis software for bit stream data in an embodiment of the present invention;

Fig. 8 is a schematic diagram of saving the final test configuration file in the embodiment of the present invention.

Detailed ways

In order to improve the test fault coverage and facilitate the calculation of the fault coverage, the FPGA test configuration design adopts a modular configuration method. In a configuration file, at least one CLB or IO configuration module is designed, and such configuration modules are repeated in the entire FPGA. (We know that FPGA includes many CLB matrices and IO matrices with exactly the same structure), the test coverage of configurable resources of each CLB or IO is easy to calculate, and the test coverage of configurable resources of the entire FPGA is also easy to calculate out. This technology extracts the configuration data of one or several CLBs or IOs in the configuration file, and moves it to any designated CLB module of the FPGA with the help of bit stream data analysis software to reconstruct the FPGA configuration file, which can quickly generate New test configuration.

As shown in Figure 2, it is the design and development process of the present invention, which mainly includes: analyzing and testing requirements to set up configuration files; manually carrying out module design such as CLB and IO; carrying out data extraction and moving (carrying out according to the mapping relationship between data and resources), and completing Configuration files, and finally FPGA testing can be done as needed.

The method of the invention avoids the limitation of some design rules on the test configuration design, and achieves the purpose of rapidly generating test configuration files. Directly connect the test requirements manually in the FPGA editing tool (EDITOR) and generate the configuration data of the CLB or IO module, and obtain the test configuration files of all configurable resources in the FPGA through the copying and moving means of the special analysis software for bit stream data, and Generate test code.

Please refer to a specific embodiment shown in FIG. 3 to FIG. 8 . Including the following steps:

(1) Use FPGA EDITOR to create a new design file named XC2S100 (as shown in Figure 3).

(2) Manually implement the logic design of the CLB (as shown in Figure 4).

(3) Generate a CLB bit stream file, the file name is CLBR1C15.Bit (as shown in Figure 5).

(4) Use special analysis software for bit stream data to extract and move CLB configuration. Specifically include:

The steps of opening the CLBR1C15.Bit bit stream file (as shown in Figure 6);

Click to select the CLB data area, and according to the mapping relationship between data and resources, use copy to extract or move CLB data, so that each resource in the FPGA meets the expected requirements (as shown in Figure 7).

(5) Save the final file to generate a new test configuration file test-bitstream.bit (as shown in Figure 8).

The present invention has the following characteristics:

(1) The CLB configuration module is precisely designed;

(2) The mapping relationship between the CLB module and the IO module and the configuration file is fully considered.

(3) It avoids the restrictions of some design rules on the test configuration design, and directly processes the configuration files to achieve the purpose of quickly generating test configuration files.

Claims (3)

1. a generation method for FPGA configuration file, is characterized in that, comprise the steps:

(1) new design document is set up with Software tool;

(2) logical design of at least one configurable logic blocks or input/output module is manually realized;

(3) bit stream file of described configurable logic blocks or input/output module is generated;

(4) with bit stream data dedicated analysis software the bit stream file described in step (3) extracted and move in described FPGA configuration file, wherein, step (4) is the mapping relations according to data and resource, one or a few configurable logic blocks in extraction configuration file, i.e. described bit stream file or the configuration data of input/output module, described configuration data is moved on configurable logic blocks that FPGA specifies arbitrarily and construct described FPGA configuration file, generate new test configurations.

2. the generation method of FPGA configuration file as claimed in claim 1, it is characterized in that, step (4) is the mapping relations according to data and resource, is undertaken extracting and moving by the mode copied, and makes each resource in FPGA meet test request.

3. the generation method of FPGA configuration file as claimed in claim 1 or 2, it is characterized in that, described configuration file is test profile.