CN101793941B - Creation method of FPGA (Field Programmable Gate Array ) configuration file - Google Patents
Creation method of FPGA (Field Programmable Gate Array ) configuration file Download PDFInfo
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Abstract
本发明公开了一种FPGA配置文件的生成方法,包括如下步骤:(1)用软件工具建立新的设计文件;(2)手动实现至少一个可配置逻辑模块或输入输出模块的逻辑设计;(3)生成所述可配置逻辑模块或输入输出模块的位流文件;(4)用位流数据专用分析软件将步骤(3)所述的位流文件提取并搬移到所述FPGA配置文件中。本发明避免了一些设计规则对测试配置设计的限制,直接对配置文件进行处理,达到快速生成测试配置文件的目的。
The invention discloses a method for generating an FPGA configuration file, comprising the following steps: (1) establishing a new design file with a software tool; (2) manually implementing the logic design of at least one configurable logic module or input-output module; (3) ) generating the bit stream file of the configurable logic module or the input/output module; (4) extracting and moving the bit stream file described in step (3) into the FPGA configuration file with special analysis software for bit stream data. The invention avoids the limitation of some design rules on the test configuration design, directly processes the configuration files, and achieves the purpose of quickly generating the test configuration files.
Description
技术领域 technical field
本发明涉及一种现场可编程门阵列(Field Programmable Gate Array,简称FPGA)的测试方法,具体涉及一种测试用的FPGA配置文件的生成方法。The present invention relates to a method for testing a field programmable gate array (Field Programmable Gate Array, referred to as FPGA), in particular to a method for generating an FPGA configuration file for testing.
背景技术 Background technique
FPGA现场可编程器件广泛应用于通信、汽车、航空、国防等领域。运用FPGA开发的产品最终都会生成具有特定功能的位流配置文件(FPGA启动时需要从外部读取配置数据,这种包含配置数据的文件称之为配置文件),配置文件在系统启动时被下载到FPGA中,使得FPGA具有我们所期望的特殊功能。配置文件的生成是FPGA产品开发的关键。FPGA产品的开发过程一般有:设计输入、仿真、综合、自动布局布线、配置文件的生成等几个流程。这一系列动作的完成需要借助于专用开发工具系统,如Xilinx公司的ISE、Altera公司的QuartusII、Lattice公司的IspLever等开发系统。FPGA field programmable devices are widely used in communication, automobile, aviation, national defense and other fields. Products developed using FPGA will eventually generate a bit stream configuration file with specific functions (the configuration data needs to be read from the outside when the FPGA is started, and this file containing configuration data is called a configuration file), and the configuration file is downloaded when the system starts Into the FPGA, so that the FPGA has the special functions we expect. The generation of configuration files is the key to FPGA product development. The development process of FPGA products generally includes several processes such as design input, simulation, synthesis, automatic layout and routing, and configuration file generation. The completion of this series of actions requires the help of special development tool systems, such as Xilinx's ISE, Altera's QuartusII, Lattice's IspLever and other development systems.
FPGA是一种电可擦除,电可改写器件,虽然与标准门阵列类似,但却具有特殊的体系结构和逻辑单元,一般数字逻辑电路的测试方法不适应于FPGA芯片的测试。FPGA电可擦除,电可改写器件特殊的体系结构,使电路的完备性测试和故障分析、故障评估变得更加复杂,由于其内部构造具有高度重复性,因而可测性很强,但要通过有限的测试配置完成高故障覆盖率测试具有很高的难度,必须对测试文件进行精确设计构造,使每个测试配置文件具有最高测试效率。常规的自动布局布线受到FPGA设计规则的局限已不能满足这一设计要求,必须寻求一种高效的FPGA测试配置文件生成方法。FPGA is an electrically erasable and electrically rewritable device. Although it is similar to a standard gate array, it has a special architecture and logic unit. The general digital logic circuit test method is not suitable for FPGA chip testing. The special architecture of FPGA electrically erasable and electrically rewritable devices makes the integrity test, fault analysis and fault evaluation of the circuit more complicated. Because its internal structure is highly repeatable, it is highly measurable, but it must be It is very difficult to complete the high fault coverage test through limited test configurations, and the test files must be precisely designed and constructed so that each test configuration file has the highest test efficiency. Conventional automatic placement and routing is limited by FPGA design rules and can no longer meet this design requirement, so an efficient FPGA test configuration file generation method must be sought.
如图1所示,传统FPGA配置文件的设计生成,需要根据测试要求首先经过反复的设计输入、功能仿真、修改优化,然后进行设计综合、设计实现(自动布局布线)等过程,从而生成配置文件,进行FPGA测试。此流程中工作量最大的地方就是设计输入,在仿真过程中会不断出现错误信息,需要一步步优化修改,过程中的每一步都必须符合FPGA设计的各种规则,一旦违反了这些规则,就无法继续进行,这种规则局限了FPGA测试配置文件的设计,测试配置文件的设计是针对FPGA芯片自身测试进行的逻辑设计,而不是应用设计。As shown in Figure 1, the design generation of traditional FPGA configuration files requires repeated design input, function simulation, modification and optimization according to test requirements, and then design synthesis, design implementation (automatic layout and routing) and other processes to generate configuration files , for FPGA testing. The biggest workload in this process is the design input. During the simulation process, error messages will continue to appear, and it needs to be optimized and modified step by step. Each step in the process must comply with various rules of FPGA design. Once these rules are violated, the It is impossible to continue. This rule limits the design of the FPGA test configuration file. The design of the test configuration file is a logic design for the FPGA chip itself, not an application design.
发明内容 Contents of the invention
本发明所要解决的技术问题是提供一种FPGA配置文件的生成方法,它不需通过传统复杂的途径而能实现配置文件的快速生成,主要应用于FPGA芯片的测试配置文件的生成。The technical problem to be solved by the present invention is to provide a method for generating FPGA configuration files, which can realize the rapid generation of configuration files without traditional complicated approaches, and is mainly used in the generation of test configuration files for FPGA chips.
为了解决以上技术问题,本发明提供了一种FPGA配置文件的生成方法,包括如下步骤:In order to solve the above technical problems, the invention provides a method for generating an FPGA configuration file, comprising the steps of:
(1)用软件工具建立新的设计文件;(1) Create new design files with software tools;
(2)手动实现至少一个可配置逻辑模块(CLB)或输入输出模块(IO)的逻辑设计;(2) Manually implement the logic design of at least one configurable logic block (CLB) or input-output module (IO);
(3)生成所述可配置逻辑模块或输入输出模块的位流文件;(3) generating the bit stream file of the configurable logic module or the input/output module;
(4)用位流数据专用分析软件将步骤(3)所述的位流文件提取并搬移到所述FPGA配置文件中。(4) Extract and move the bit stream file described in step (3) into the FPGA configuration file with special analysis software for bit stream data.
优选地,本发明的FPGA配置文件的生成方法,步骤(4)是根据数据与资源的映射关系,用复制的方式进行提取和搬移,使FPGA中的每一个资源符合测试要求。Preferably, the generation method of FPGA configuration file of the present invention, step (4) is to extract and move with the mode of copying according to the mapping relation of data and resource, makes each resource in FPGA meet test requirement.
优选地,本发明的FPGA配置文件的生成方法,所述的配置文件为测试配置文件。Preferably, in the method for generating FPGA configuration files of the present invention, the configuration files are test configuration files.
本发明避免了一些设计规则对测试配置设计的限制,直接对配置文件进行处理,达到快速生成测试配置文件的目的。The invention avoids the limitation of some design rules on the test configuration design, directly processes the configuration files, and achieves the purpose of quickly generating the test configuration files.
附图说明 Description of drawings
下面结合附图和具体实施方式对本发明作进一步详细说明。The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.
图1是现有技术生成FPGA配置文件的流程图;Fig. 1 is the flow chart that prior art generates FPGA configuration file;
图2是本发明的FPGA配置文件的生成方法的流程图;Fig. 2 is the flowchart of the generating method of FPGA configuration file of the present invention;
图3是本发明的实施例中用FPGA编辑工具建立新的设计文件的示意图;Fig. 3 is the schematic diagram that establishes new design file with FPGA editing tool in the embodiment of the present invention;
图4是本发明的实施例中手动实现CLB的逻辑设计的示意图;Fig. 4 is the schematic diagram of the logic design that realizes CLB manually in the embodiment of the present invention;
图5是本发明的实施例中生成CLB位流文件的示意图;Fig. 5 is the schematic diagram that generates CLB bit stream file in the embodiment of the present invention;
图6是本发明的实施例中用位流数据专用分析软件进行CLB配置提取的示意图;Fig. 6 is a schematic diagram of extracting CLB configuration with special analysis software for bit stream data in an embodiment of the present invention;
图7是本发明的实施例中用位流数据专用分析软件进行CLB配置搬移的示意图;Fig. 7 is a schematic diagram of moving CLB configuration with special analysis software for bit stream data in an embodiment of the present invention;
图8是本发明的实施例中保存最终测试配置文件的示意图。Fig. 8 is a schematic diagram of saving the final test configuration file in the embodiment of the present invention.
具体实施方式 Detailed ways
为了提高测试故障覆盖率和便于故障覆盖率的计算,FPGA测试配置设计采取模块化配置方式,在一个配置文件中,设计至少一种CLB或IO的配置模块,在整个FPGA内重复这样的配置模块(我们知道FPGA包括许多结构完全相同的CLB矩阵和IO矩阵),每个CLB或IO的可配置资源的测试覆盖率很容易经过计算得到,那么整个FPGA的可配置资源的测试覆盖率也易于计算出。本技术通过提取配置文件中的一块或几块CLB或IO的配置数据,在位流数据专用分析软件的帮助下将其搬移到FPGA任意指定的CLB模块上重新构造FPGA配置文件,这样可以快速生成新的测试配置。In order to improve the test fault coverage and facilitate the calculation of the fault coverage, the FPGA test configuration design adopts a modular configuration method. In a configuration file, at least one CLB or IO configuration module is designed, and such configuration modules are repeated in the entire FPGA. (We know that FPGA includes many CLB matrices and IO matrices with exactly the same structure), the test coverage of configurable resources of each CLB or IO is easy to calculate, and the test coverage of configurable resources of the entire FPGA is also easy to calculate out. This technology extracts the configuration data of one or several CLBs or IOs in the configuration file, and moves it to any designated CLB module of the FPGA with the help of bit stream data analysis software to reconstruct the FPGA configuration file, which can quickly generate New test configuration.
如图2所示为本发明的设计开发流程,主要包括:分析测试要求建立配置文件;手动进行CLB、IO等模块设计;进行数据提取与搬移(要根据数据与资源的映射关系进行),完成配置文件,最后根据需要可以进行FPGA测试。As shown in Figure 2, it is the design and development process of the present invention, which mainly includes: analyzing and testing requirements to set up configuration files; manually carrying out module design such as CLB and IO; carrying out data extraction and moving (carrying out according to the mapping relationship between data and resources), and completing Configuration files, and finally FPGA testing can be done as needed.
本发明的方法避免了一些设计规则对测试配置设计的限制,达到快速生成测试配置文件的目的。直接将测试要求在FPGA编辑工具(EDITOR)中手工实现连接并生成CLB或IO模块的配置数据,通过位流数据专用分析软件的复制搬移手段,得到FPGA中所有可配置资源的测试配置文件,并生成测试码。The method of the invention avoids the limitation of some design rules on the test configuration design, and achieves the purpose of rapidly generating test configuration files. Directly connect the test requirements manually in the FPGA editing tool (EDITOR) and generate the configuration data of the CLB or IO module, and obtain the test configuration files of all configurable resources in the FPGA through the copying and moving means of the special analysis software for bit stream data, and Generate test code.
请参见图3至图8所示的一个具体实施例。包括如下步骤:Please refer to a specific embodiment shown in FIG. 3 to FIG. 8 . Including the following steps:
(1)用FPGA EDITOR建立新的名称为XC2S100的设计文件(如图3)。(1) Use FPGA EDITOR to create a new design file named XC2S100 (as shown in Figure 3).
(2)手动实现CLB的逻辑设计(如图4)。(2) Manually implement the logic design of the CLB (as shown in Figure 4).
(3)生成CLB位流文件,该文件名称为CLBR1C15.Bit(如图5)。(3) Generate a CLB bit stream file, the file name is CLBR1C15.Bit (as shown in Figure 5).
(4)用位流数据专用分析软件进行CLB配置提取与搬移。具体包括:(4) Use special analysis software for bit stream data to extract and move CLB configuration. Specifically include:
打开CLBR1C15.Bit位流文件的步骤(如图6);The steps of opening the CLBR1C15.Bit bit stream file (as shown in Figure 6);
点击选取CLB数据区,根据数据与资源的映射关系,用copy的方式提取或搬移CLB数据,使FPGA中的每一个资源符合期待的要求的步骤(如图7)。Click to select the CLB data area, and according to the mapping relationship between data and resources, use copy to extract or move CLB data, so that each resource in the FPGA meets the expected requirements (as shown in Figure 7).
(5)保存最终文件生成新的测试配置文件test-bitstream.bit(如图8)。(5) Save the final file to generate a new test configuration file test-bitstream.bit (as shown in Figure 8).
本发明具有以下特点:The present invention has the following characteristics:
(1)精确设计了CLB配置模块;(1) The CLB configuration module is precisely designed;
(2)充分考虑了CLB模块和IO模块与配置文件的映射关系。(2) The mapping relationship between the CLB module and the IO module and the configuration file is fully considered.
(3)避免了一些设计规则对测试配置设计的限制,直接对配置文件进行处理,达到快速生成测试配置文件的目的。(3) It avoids the restrictions of some design rules on the test configuration design, and directly processes the configuration files to achieve the purpose of quickly generating test configuration files.
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CN102156789B (en) * | 2011-04-27 | 2013-01-02 | 迈普通信技术股份有限公司 | System and method for automatically generating constraint file of field programmable gate array (FPGA) |
CN102288870B (en) * | 2011-05-16 | 2013-07-03 | 中国电子科技集团公司第五十八研究所 | Testing method for FPGA (field programmable gate array) single long wire and directly connected switch |
CN102253329B (en) * | 2011-06-17 | 2013-04-17 | 中国电子科技集团公司第五十八研究所 | Method for testing field programmable gate array (FPGA) single-long line slant switches |
CN102445636B (en) * | 2011-09-02 | 2013-11-13 | 中国电子科技集团公司第五十八研究所 | Method for testing Hex lines and diagonal interconnect switches thereof in FPGA (field-programmable gate array) |
CN103164228B (en) * | 2013-03-29 | 2015-12-23 | 北京经纬恒润科技有限公司 | A kind of generation method of field programmable gate array program and device |
CN106777729A (en) * | 2016-12-26 | 2017-05-31 | 中核控制系统工程有限公司 | A kind of algorithms library simulation and verification platform implementation method based on FPGA |
CN107895087B (en) * | 2017-11-29 | 2021-02-26 | 中科亿海微电子科技(苏州)有限公司 | Method and system for automatically generating module-level simulation configuration code of programmable logic circuit |
CN111123083B (en) * | 2019-12-06 | 2022-04-29 | 国家电网有限公司 | A test system and method for FPGA PLL IP core |
CN111142013B (en) * | 2019-12-31 | 2021-12-07 | 无锡市同飞科技有限公司 | MAX7000 series CPLD (Complex programmable logic device) based logic reduction method |
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