CN101793941B

CN101793941B - Creation method of FPGA (Field Programmable Gate Array ) configuration file

Info

Publication number: CN101793941B
Application number: CN200910200706.1A
Authority: CN
Inventors: 叶守银; 张志勇; 祁建华; 徐惠
Original assignee: Sino IC Technology Co Ltd
Current assignee: Sino IC Technology Co Ltd
Priority date: 2009-12-24
Filing date: 2009-12-24
Publication date: 2015-04-01
Anticipated expiration: 2029-12-24
Also published as: CN101793941A

Abstract

The invention discloses a creation method of an FPGA configuration file, comprising the following steps of: (1) establishing a new design file by using a software tool; (2) manually realizing at least one logic design of a configurable logic module or an input and output module; (3) creating a bit stream file of the configurable logic module or the input and output module; and (4) extracting and shifting the bit stream file in step (3) into the FPGA configuration file by using special software for analyzing bit stream data. The invention avoids a test configuration design from being limited by some design rules and directly processes the configuration file to achieve the purpose of rapidly creating the test configuration file.

Description

The generation method of FPGA configuration file

Technical field

The present invention relates to the method for testing of a kind of field programmable gate array (Field Programmable Gate Array is called for short FPGA), be specifically related to a kind of generation method of FPGA configuration file of testing.

Background technology

FPGA field programmable device is widely used in the fields such as communication, automobile, aviation, national defence.(when FPGA starts, needs read configuration data from outside to use the product of FPGA exploitation finally all can generate the bitstream configuration file with specific function, this file comprising configuration data is referred to as configuration file), configuration file is downloaded in FPGA when system starts, and makes FPGA have specific function desired by us.The generation of configuration file is the key of FPGA product development.The performance history of FPGA product generally has: several flow processs such as the generation of design input, emulation, comprehensive, automatic placement and routing, configuration file.Completing of this series of actions needs by means of dedicated development tool system, as the development system such as IspLever of the ISE of Xilinx company, QuartusII, Lattice company of altera corp.

FPGA is a kind of electric erasable, electrically rewritable device, although similar with standard gate array, has special architecture and logical block, and the method for testing of general DLC (digital logic circuit) is not suitable for the test of fpga chip.FPGA electric erasable, the architecture that electrically rewritable device is special, the integrity test of circuit and fault analysis, assessment of failure is made to become more complicated, because its internal structure has high reproducibility, thus measurability is very strong, but high fault coverage test to be completed by limited test configurations there is very high difficulty, precise design configuration must be carried out to test file, make each test profile have the highest testing efficiency.The limitation that conventional automatic placement and routing is subject to FPGA design rule can not meet this designing requirement, must seek a kind of FPGA test profile generation method efficiently.

As shown in Figure 1, the design of traditional F PGA configuration file generates, need according to test request first through design input repeatedly, functional simulation, amendment optimization, then carry out design synthesis, design realizes processes such as (automatic placement and routings), thus generating configuration file, carry out FPGA test.The place that in this flow process, workload is maximum is exactly design input, constantly error message can be there is in simulation process, need to optimize amendment step by step, each step in process all must meet the various rules of FPGA design, once violate these rules, just cannot proceed, this rule has limited to the design of FPGA test profile, the design of test profile is the logical design carried out for fpga chip selftest, instead of application design.

Summary of the invention

Technical matters to be solved by this invention is to provide a kind of generation method of FPGA configuration file, and it does not need the quick generation that can be realized configuration file by the complicated approach of tradition, is mainly used in the generation of the test profile of fpga chip.

In order to solve above technical matters, the invention provides a kind of generation method of FPGA configuration file, comprising the steps:

(1) new design document is set up with Software tool;

(2) logical design of at least one configurable logic blocks (CLB) or input/output module (IO) is manually realized;

(3) bit stream file of described configurable logic blocks or input/output module is generated;

(4) with bit stream data dedicated analysis software, the bit stream file described in step (3) is extracted and moves in described FPGA configuration file.

Preferably, the generation method of FPGA configuration file of the present invention, step (4) is the mapping relations according to data and resource, is undertaken extracting and moving by the mode copied, and makes each resource in FPGA meet test request.

Preferably, the generation method of FPGA configuration file of the present invention, described configuration file is test profile.

Present invention, avoiding the restriction that some design rules design test configurations, directly configuration file is processed, reach the object generating test profile fast.

Accompanying drawing explanation

Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.

Fig. 1 is the process flow diagram that prior art generates FPGA configuration file;

Fig. 2 is the process flow diagram of the generation method of FPGA configuration file of the present invention;

Fig. 3 is the schematic diagram setting up new design document in embodiments of the invention with FPGA edit tool;

Fig. 4 is the schematic diagram of the logical design manually realizing CLB in embodiments of the invention;

Fig. 5 is the schematic diagram generating CLB bit stream file in embodiments of the invention;

Fig. 6 is the schematic diagram carrying out CLB configuration extraction in embodiments of the invention with bit stream data dedicated analysis software;

Fig. 7 carries out CLB with bit stream data dedicated analysis software in embodiments of the invention to configure the schematic diagram moved;

Fig. 8 is the schematic diagram preserving final test configuration file in embodiments of the invention.

Embodiment

In order to improve test failure coverage rate and the calculating being convenient to fault coverage, modular arrangements mode is taked in the design of FPGA test configurations, in a configuration file, the configuration module of design at least one CLB or IO, such configuration module (we know that FPGA comprises the identical CLB matrix of many structures and IO matrix) is repeated in whole FPGA, the test coverage of the configurable resource of each CLB or IO is easy to through calculating, and the test coverage of the configurable resource of so whole FPGA is also easy to calculate.This technology is by extracting the configuration data of one or a few CLB or IO in configuration file, moved under the help of bit stream data dedicated analysis software in CLB module that FPGA specifies arbitrarily and re-constructed FPGA configuration file, new test configurations can be generated fast like this.

Be illustrated in figure 2 and of the present inventionly design and develop flow process, mainly comprise: analytical test requires to set up configuration file; Manually carry out the modular design such as CLB, IO; Carry out data to extract and move (will carry out according to the mapping relations of data and resource), complete configuration file, finally can carry out FPGA test as required.

Present method avoids the restriction that some design rules design test configurations, reach the object generating test profile fast.Directly test request manual realization in FPGA edit tool (EDITOR) is connected and generates the configuration data of CLB or I/O module, the means of moving are copied by bit stream data dedicated analysis software, obtain the test profile of all configurable resources in FPGA, and generate test patterns.

Refer to the specific embodiment of shown in Fig. 3 to Fig. 8.Comprise the steps:

(1) set up with FPGA EDITOR the design document (as Fig. 3) that new name is called XC2S100.

(2) logical design (as Fig. 4) of CLB is manually realized.

(3) generate CLB bit stream file, this file name is CLBR1C15.Bit (as Fig. 5).

(4) carry out CLB configuration extraction with bit stream data dedicated analysis software and move.Specifically comprise:

Open the step (as Fig. 6) of CLBR1C15.Bit bit stream file;

CLB data field is chosen in click, according to the mapping relations of data and resource, extracts or moves CLB data, make each resource in FPGA meet the step (as Fig. 7) of the requirement of expectation by the mode of copy.

(5) preserve definitive document and generate new test profile test-bitstream.bit (as Fig. 8).

The present invention has following characteristics:

(1) careful design CLB configuration module;

(2) mapping relations of CLB module and I/O module and configuration file have been taken into full account.

(3) avoid the restriction that some design rules design test configurations, directly configuration file is processed, reach the object generating test profile fast.

Claims

1. a generation method for FPGA configuration file, is characterized in that, comprise the steps:

(1) new design document is set up with Software tool;

(2) logical design of at least one configurable logic blocks or input/output module is manually realized;

(4) with bit stream data dedicated analysis software the bit stream file described in step (3) extracted and move in described FPGA configuration file, wherein, step (4) is the mapping relations according to data and resource, one or a few configurable logic blocks in extraction configuration file, i.e. described bit stream file or the configuration data of input/output module, described configuration data is moved on configurable logic blocks that FPGA specifies arbitrarily and construct described FPGA configuration file, generate new test configurations.

2. the generation method of FPGA configuration file as claimed in claim 1, it is characterized in that, step (4) is the mapping relations according to data and resource, is undertaken extracting and moving by the mode copied, and makes each resource in FPGA meet test request.

3. the generation method of FPGA configuration file as claimed in claim 1 or 2, it is characterized in that, described configuration file is test profile.