CN110874517A

CN110874517A - Method for rapidly verifying connection correctness of FPGA (field programmable Gate array) interconnection line

Info

Publication number: CN110874517A
Application number: CN201810906785.7A
Authority: CN
Inventors: 严伟; 胡凯; 范继聪; 徐彦峰; 惠锋
Original assignee: Peking University
Current assignee: Peking University
Priority date: 2018-08-10
Filing date: 2018-08-10
Publication date: 2020-03-10

Abstract

The invention relates to a method for rapidly verifying connection correctness of FPGA (field programmable gate array) interconnecting wires, which is based on a formal verification thought and adopts topological structure comparison to verify the connection correctness of the interconnecting wires. The method specifically starts from two aspects, firstly, a perfect interconnection line specification is made at the initial stage of FPGA design, and an interconnection resource generation tool is customized according to the specification to generate an interconnection resource file. Secondly, in the chip design process, a hierarchical design method is adopted to carry out rule naming on all INSTANCEs, each SWB in the FPGA has a unique identifier, and after the circuit design is successful, a netlist analysis tool is developed to analyze and obtain interconnection resources of the actual circuit. And comparing the two interconnection resource files to find out the problems existing in the design and realize the verification of the connection correctness of the interconnection line. The method provided by the invention can quickly finish the verification of the connection correctness of the FPGA interconnection line, the coverage rate is up to 100 percent, and the design time is greatly shortened.

Description

Method for rapidly verifying connection correctness of FPGA (field programmable Gate array) interconnection line

Technical Field

The invention belongs to the technical field of electronics. In particular to a method for quickly verifying an interconnection line of a programmable logic device (FPGA).

Background

At present, with the continuous improvement of the level of the integrated circuit manufacturing process, the characteristic size of a device is continuously reduced, the FPGA scale is larger and larger, more and more integrated modules are provided, and more complex functions can be realized. Currently, the mainstream FPGA is designed based on the SRAM, and downloads configuration information to a corresponding configuration RAM, and controls the corresponding switch to be turned on and off by configuring a value of the RAM, so as to implement connection of a corresponding circuit. The FPGA mainly comprises programmable input and output, programmable interconnections and programmable logic, wherein the programmable interconnections comprise programmable interconnection lines and programmable interconnection switches. Compared with modules such as IO/CLB/DSP/BRAM/SWB, the FPGA interconnection line verification faces a great challenge. Different from the automatic layout and wiring design adopted by some ASIC chips, the interconnection of FPGA needs to be designed in a customized way, the short circuit and open circuit of the interconnection line are easy to occur in the design process, and it is very difficult to check the errors. Therefore, a verification method capable of quickly realizing the correct connection of the FPGA interconnection line is urgently needed. The method for verifying the FPGA interconnection correctness based on the topological structure can effectively check the open circuit and short circuit conditions of the interconnection lines in a schematic diagram, and has the advantages of high implementation speed and high coverage rate (up to 100% theoretically).

Disclosure of Invention

The invention aims to overcome the defects of the existing FPGA interconnection verification method, provides a method for quickly realizing FPGA interconnection verification based on a formal verification thought, can quickly and effectively realize FPGA interconnection verification, and can effectively check the short circuit and open circuit conditions in the interconnection process.

The interconnection verification method provided by the invention comprises the following specific steps:

(1) and acquiring a GOLDEN file of FPGA interconnection resources as a reference. At the initial stage of FPGA design, a perfect interconnection specification is made, and the type and the number of interconnection lines adopted by a chip are specified. As the size of FPGAs is increasing, the number and type of interconnect lines required is increasing. However, it is not always better to have more interconnection resources, which requires to comprehensively consider the aspects of the traffic distribution rate, the speed and the resource utilization, and finally to make feasible interconnection resources. The interconnect line type generally contains information about the direction and the span of the line, and the direction of the interconnect line generally refers to the direction from the driving point to the load point, and the direction is defined as the direction of the map, i.e., North (North), South (South), West (West), and East (East). The span generally refers to the number of CLBs spanned by the interconnection lines, and the common lines include 2-fold lines, 4-fold lines, 5-fold lines, 6-fold lines, long lines and the like. According to the specification of the interconnection lines, a corresponding interconnection resource generation program can be written according to the interconnection specification, wherein the interconnection resources are interconnection lines with the driving point of each SWB as the starting point, and the interconnection lines with the driving points of all the SWBs as the starting points form the interconnection resources of the whole FPGA chip.

Therefore, when generating the interconnection resource file of the whole FPGA chip, the ARCH file of the FPGA needs to be provided, where the ARCH file refers to a file containing information of the number of rows and columns of the SWB in the FPGA chip. In the FPGA, the SWBs are distributed in a two-dimensional form, and the interconnection resource generation program reads the ARCH file to acquire the SWB row information of the whole FPGA chip, so that the interconnection resource file of the whole FPGA chip can be generated and used as a GOLDEN file.

(2) And analyzing the circuit netlist to obtain an interconnection resource file of the actual design circuit. At present, the interconnection design of the FPGA still needs to adopt a schematic diagram design method, and a hierarchical design method is generally adopted in circuit design based on the characteristic of high repeatability of modules in the FPGA. The hierarchical design method can accelerate the design speed, effectively reduce the file size of the schematic diagram and improve the design development speed. For hierarchical design, each instruction in the circuit diagram needs to be named meaningfully, each instruction name needs to contain a module name and corresponding coordinate information, and because the whole circuit is multi-level, the coordinate information in the instruction name is relative coordinates. In this way, the absolute coordinate information of each SWB can be obtained from the relative coordinate relationship.

And obtaining a finished FPGA whole circuit netlist file through Virtuoso, designing a netlist analysis program, wherein the netlist analysis program can track the connection relation from each SWB driving point according to the connection relation of the whole circuit netlist, so that all interconnection resources in the whole FPGA chip can be obtained, and the tracked interconnection resources are concentrated into one file, so that the interconnection resource file corresponding to the actual design circuit can be obtained.

(3) And comparing interconnection resources. And (3) comparing the GOLDEN interconnection file generated in the step (1) with the interconnection resource file extracted from the actual FPGA circuit in the step (2). For the open circuit phenomenon, the path obtained by analyzing the circuit netlist is shorter than the corresponding path in the GOLDEN file, and the connection after the open circuit is lost. For the short circuit phenomenon, the path obtained by analyzing the circuit netlist is longer than the corresponding path in the GOLDEN file, and branches connected with the short circuit are added. Therefore, the short circuit and open circuit phenomena in the design process can be effectively checked.

The interconnection verification method provided by the design is based on an interconnection topological structure, comparison is carried out in a text mode, all interconnection resources in the FPGA chip can be covered by one hundred percent, and meanwhile, the whole verification process can be completed only in a short time, so the method is called as a method for quickly verifying the connection correctness of the FPGA interconnection lines.

Technical effects

The technical method provided by the invention is already realized in practical application. Experiments show that the method can effectively check the problems of short circuit and open circuit of the interconnection line caused in the FPGA design process. Compared with the traditional verification method based on dynamic simulation, the method can greatly improve the verification speed, simultaneously can cover hundreds of all interconnection line resources in the FPGA, and greatly improves the design speed of the chip.

Drawings

FIG. 1 is a flow chart of the method of the present invention.

FIG. 2 is a schematic diagram of an interconnect line according to the present invention.

FIG. 3 is an exemplary diagram of an interconnection resource file generated according to an interconnection rule in the present invention.

FIG. 4 is an expanded design SWB azimuth diagram.

FIG. 5 is a schematic diagram of hierarchical design naming according to the present invention.

FIG. 6 is an exemplary diagram of an interconnection resource file obtained by parsing a circuit according to the present invention.

Detailed Description

The method for rapidly verifying the connection correctness of the FPGA interconnection line provided by the present invention is described in detail below with reference to the accompanying drawings and the embodiments.

As shown in fig. 1, which is an overall flowchart of the verification method provided by the present invention, it can be seen from the figure that the method for quickly verifying the connection correctness of the FPGA interconnection line provided by the present invention mainly starts from two aspects, namely, generating an interconnection resource file as a GOLDEN model according to the interconnection rule and the ARCH file information of the designed chip, and analyzing the designed chip netlist to obtain an interconnection resource file corresponding to the actual circuit, and comparing the obtained interconnection resource file with the GOLDEN model file to verify the interconnection correctness of the actual designed circuit.

To obtain the interconnection resource GOLDEN file, the ARCH file and the interconnection rule need to be provided. The ARCH file generally provides the row number and column number information of the SWB in the FPGA chip, the SWB is distributed in two dimensions in the FPGA chip, and the row number and column number information is provided, so that all SWB position information in the whole FPGA chip can be obtained. The directional names of interconnect lines in an FPGA generally consist of 4 parts, respectively:

1. the direction is as follows: the directions of the interconnection lines in the FPGA adopt the same definition as the map directions, namely north (N) above and south (S) below and west (W) left and east (E) right.

2. Span: the span refers to the number of CLCs spanned by the interconnect lines, and is typically 2, 5, and 6, commonly referred to as 2-fold, 5-fold, and 6-fold. Sometimes long lines (spans 18, 24, etc.).

3. Position: typically one interconnect line comprises a start point (SRC) and an end point (DST), the start point being the drive point. Some interconnects also include a midpoint, which is a tap between the starting and ending points, and may be more flexible, and is often referred to as a Midpoint (MID), where "midpoint" is not strictly a midpoint, and for a 5-fold line, a midpoint is typically at a span of 3 from the starting point.

4. Numbering: generally, there are many types of interconnection lines in an FPGA, and lines are numbered for distinction.

Fig. 2 is a schematic diagram of a common interconnection line, and the interconnection rule can be easily obtained according to the name of the interconnection line. With the ARCH information and interconnection rules of the chip, an interconnection resource generation program can be designed to obtain an ideal interconnection resource file, i.e., an interconnection GOLDEN file, and the content of the obtained GOLDEN file is shown in fig. 3.

The SWBs are uniformly distributed in the whole FPGA chip, as shown in fig. 4, each SWB has a unique name, and can mark the row and column information where it is located. If the expanded design is adopted when the FPGA chip is designed, each SWB name can be named by adopting absolute coordinates, so that the interconnection information in the whole chip can be easily extracted according to netlist information. However, with the increasing scale of FPGA chips, the expansion design is not suitable, and currently, a hierarchical circuit design is mainly adopted, and compared with the expansion design, the hierarchical design has reusability, so that the size of a circuit file can be greatly reduced, the design speed is increased, and the design cycle is shortened. By adopting the hierarchical design, meaningful names need to be adopted for all the hierarchical modules of the circuit, and the absolute coordinates of each SWB can be obtained through analysis. The method provided by the invention adopts hierarchical naming as shown in fig. 5, the name of each module contains coordinate information, the coordinate information is relative coordinate information relative to the hierarchy, and the absolute coordinate information of each SWB can be obtained by substituting the relative coordinate information into a corresponding absolute coordinate solving formula. All interconnection resource files contained in the design FPGA can be obtained through a netlist analysis program, the content of each SWB is shown in FIG. 6, and each SWB is started with an SWB and is accompanied with coordinate information. The two generated interconnected resource files are compared, and then the problems in the design can be found. If the open circuit phenomenon of the interconnection line exists in the design, incomplete interconnection lines exist in the interconnection resource file obtained through design analysis, and nodes after the open circuit is lost. If the short circuit phenomenon of the interconnection line exists in the design, the lengthened interconnection line exists in the interconnection resource file obtained through the design analysis, and node information is added relative to the normal interconnection line.

The method for rapidly verifying the connection correctness of the FPGA interconnection line is applied and realized in actual work, and the phenomena of short circuit and open circuit of the interconnection line caused in the circuit design process can be effectively checked through experiments. The method has the advantages of high speed and high coverage rate, can quickly and effectively find interconnection line connection errors caused in the early stage of FPGA design, improves the development speed of FPGA products, shortens the whole design period, and has important reference and practical values.

Claims

1. A method for rapidly verifying the connection correctness of an FPGA interconnection line is characterized by comprising the following specific steps:

(1) and designing an interconnection resource generation program according to the specification of the interconnection line, and generating all interconnection resources of the FPGA chip according to the interconnection rule and the ARCH file of the FPGA, wherein the interconnection resources exist in a text format. The ARCH file refers to the information of the number of rows and columns of SWBs contained in an FPGA chip, and accordingly interconnection resources of FPGAs of different scales can be generated;

(2) in the design stage of the schematic diagram of the whole chip, a regular naming mode is adopted for naming each INSTANCE in a circuit, each SWB has a unique name, and the name comprises coordinate information. Deriving a netlist from the designed circuit general diagram, designing a netlist analysis tool, and analyzing the netlist to obtain interconnection resources of the actual design circuit;

(3) by comparing the interconnection resource files generated in the two steps, errors in interconnection in the circuit design process can be found, and the circuit schematic diagram of the whole FPGA chip can be correctly interconnected.

2. The schematic design phase instruction naming of claim 1 is suitable for hierarchical design and increases design speed. And obtaining absolute coordinate information of all SWBs according to the relative coordinate information in the INSTANCE name, thereby obtaining the interconnection resources of the whole chip.