CN104679628A - Field-programmable gate array testing method - Google Patents
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Abstract
The invention discloses a field-programmable gate array testing method and belongs to integrated circuit design in the field of microelectronics and the field of electronic design automation. The method includes generating a testing circuit file according to a field-programmable gate array chip structure; generating a testing circuit constraint file according to the field-programmable gate array chip structure; obtaining an integrated net list according to the testing circuit constraint file; obtaining a mapping circuit net list according to the testing circuit constraint file and the integrated net list; completing routing of the testing circuit file according to a post-layout circuit unit and the testing circuit constraint file; obtaining a code stream file; testing an FPGA chip according to the code stream file. According to the field-programmable gate array testing method, the testing circuit is subjected to integration, mapping, layout, routing and code stream generation under constraint of the circuit constraint file, and the code stream file required by verification and testing is generated. The field-programmable gate array testing method is capable of effectively achieving wafer testing after FPGA layout verification and tape-out.
Description
Technical field
The invention belongs to the integrated circuit (IC) design in microelectronic and field of electron design automation, particularly a kind of method of testing of field programmable gate array.
Background technology
Current applications is FPGA(Field Programmable Gate Arrays widely, namely field programmable gate array) development is rapidly, FPGA product based on SRAM mainly adopts body silicon to design, and main product substantially by minority major company as Xilinx, Altera etc. monopolize, and it is relatively less for the advanced FPGA product of particular surroundings as radioresistance environment, domestic procurement can be limited by abroad, and this situation makes the national defence of China, aviation is in passive minus advantage on this extraordinary fpga chip of buying.
Be different from ASIC(Application Specific Integrated Circuit) test of chip, the test of fpga chip has larger complexity and difficulty, and its reason mainly comes from the complex heterogeneous structure of FPGA.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of method of testing of field programmable gate array, solves the technical matters that in prior art, field programmable gate array chip test accuracy and validity are not high.
For solving the problems of the technologies described above, the invention provides a kind of method of testing of field programmable gate array, specifically comprising the steps:
Step 101: according to the structure of field programmable gate array chip, produces test circuit file;
Step 102: according to the structure of described field programmable gate array chip, produces test circuit unbound document;
Step 103: according to described test circuit unbound document, carries out comprehensively, obtaining comprehensive network table to described test circuit file;
Step 104: according to described test circuit unbound document and described comprehensive network table, map, set up mapping table to described test circuit file, according to described mapping table, obtains mapping circuit net table;
Step 105: according to described mapping circuit net table and described test circuit unbound document, layout is carried out to described test circuit file, obtains the circuit unit after layout;
Step 106: according to the circuit unit after described layout and test circuit unbound document, completes wiring to described test circuit file;
Step 107: the circuit meshwork list and described test circuit unbound document that obtain according to connecting up, carries out code stream to described test circuit file, obtains ASCII stream file ASCII;
Step 108: fpga chip is tested according to described ASCII stream file ASCII.
Further, described test circuit file comprises the description of logical block class testing circuit, input-output unit class testing circuit describes, general interconnection resource class testing circuit describes and the resources-type test circuit of global routing describes.
Further, described test circuit unbound document comprises description unit mapping mode information, description unit layout information, describes signal routing information and describe input-output unit attribute information.
Further, described comprehensive method is: carried out comprehensively test circuit by synplify instrument.
Further, the method of described mapping is: according to the unit descriptor of described comprehensive network table, test circuit unbound document, test the mappings constraint information of this unit corresponding in described test circuit unbound document respectively, set up mapping table, according to institute's mapping table, the packing of the elementary cell of the input-output unit class testing circuit of described test circuit file, and set the attribute of described elementary cell.
Further, the method for described layout is: according to cell layout's information of described mapping circuit net table and described test circuit unbound document, sets up the position constraint of the circuit unit after mapping and cell layout.
Further, the method of described wiring is: according to the signal routing constraint in the circuit unit after layout and described test circuit unbound document, set up the constraint information mapping table of test cell signal and signal routing, according to described constraint information mapping table and signal routing rule, complete wiring, obtain the circuit meshwork list based on fpga chip positional information;
Further, the method that described code stream produces is: the constraint information produced according to code stream in the described circuit meshwork list based on fpga chip positional information and described test circuit unbound document, completing code stream and produces, finally generating the ASCII stream file ASCII for testing.
The invention provides a kind of method of testing of field programmable gate array, test circuit is produced through comprehensive, mapping, placement-and-routing, code stream under the constraint of circuit constraint file, generate for verifying and testing required ASCII stream file ASCII, ASCII stream file ASCII realizes checking and test as the input file of checking and test.Experimental result shows, this method of testing effectively can meet the wafer test after FPGA layout verification and flow.
Accompanying drawing explanation
The method of testing flow chart of steps of the field programmable gate array that Fig. 1 provides for the embodiment of the present invention;
Fig. 2 is the UCF form of the test logic unit LB module carry chain pattern that the embodiment of the present invention provides;
Fig. 3 is chip structure figure after the carry chain test circuit placement-and-routing that provides of the embodiment of the present invention;
Fig. 4 is the FPGA switch module test pattern that the embodiment of the present invention provides;
Fig. 5 is the UCF rule of the interconnection resource test breaker in middle module that the embodiment of the present invention provides;
Fig. 6 is the signal routing schematic diagram of the interconnection resource test that the embodiment of the present invention provides;
Fig. 7 is structure diagram and the placement-and-routing result figure of the switch module of the three types that the embodiment of the present invention provides.
Embodiment
See Fig. 1, the method for testing of a kind of field programmable gate array that the embodiment of the present invention provides, comprises the steps:
Step 101: according to the structure of field programmable gate array chip, produces test circuit file;
Step 102: according to the structure of field programmable gate array chip, produces test circuit unbound document;
Step 103: according to test circuit unbound document, carries out comprehensively, obtaining comprehensive network table to test circuit file;
Step 104: according to test circuit unbound document and comprehensive network table, map, set up mapping table to test circuit file, according to mapping table, obtains mapping circuit net table;
Step 105: according to mapping circuit net table and test circuit unbound document, layout is carried out to test circuit file, obtain the circuit unit after layout;
Step 106: according to the circuit unit after layout and test circuit unbound document, wiring is completed to test circuit file;
Step 107: the circuit meshwork list and test circuit unbound document that obtain according to connecting up, carries out code stream to test circuit file, obtains ASCII stream file ASCII;
Step 108: fpga chip is tested according to described ASCII stream file ASCII.
Embodiment 1:
Step 201: according to the function of test circuit and the structure of fpga chip to be measured, produce test circuit file, in embodiments of the present invention, the logical block class testing circuit that test circuit file comprises VS1000FPGA inside describes, input-output unit class testing circuit describes, general interconnection resource class testing circuit describes and the resources-type test circuit of global routing describes, wherein, logical block class testing circuit comprises this cell operation patterns all, input-output unit class testing circuit comprises the attribute of this unit all, general interconnection resource class testing circuit comprises the wiring rule of line and switch enclosure, the resources-type test circuit of global routing comprises the wiring rule of branch of all global routings,
Step 202: according to the structure of described field programmable gate array chip, produces test circuit unbound document; In practice, also need to consider the function of test circuit and the structure of fpga chip to be measured, produce test circuit unbound document, in embodiments of the present invention, test circuit unbound document comprises description unit mapping mode information, description unit layout information, describes signal routing information and describe input-output unit attribute information;
Step 203: according to test circuit unbound document, carries out comprehensively to test circuit file, and this testing tool adopts the synthesis tool-synplify of industry member main flow to do comprehensively, obtains the comprehensive network table of edif form.
Step 204: according to comprehensive network table and the test circuit unbound document of edif form, test circuit is mapped.Wherein, the method for mapping is: first according to the unit descriptor in the comprehensive network table of edif form, the mappings constraint information of this unit corresponding in corresponding matching test circuit constraint file, and sets up mapping table; According to this mapping table, the packing of the elementary cell of the input-output unit class testing circuit of test circuit file, and set the attribute of elementary cell;
In embodiments of the present invention, common mapping process is all full automatic, and which elementary cell, logical block are packetized in together, and packaged with what form is all very rambunctious.Given this, develop the mapping of navigation-type, its thought realized is by verilog hdl and UCF file on the impact of mapping process, thus mapping tool is produced LB mode of operation that user or tester want and combination.Wherein devise a set of describing method in verilog hdl, except circuit function is provided, also provide navigation.The content of UCF file comprises the content of two broad aspect: the constraint content of pack, i.e. which elementary unit groups combinator unit, and the unit of these combinations is with what form and mode of operation combination; The constraint content of cluster, namely which logical block collection takes on into logical block, be illustrated in figure 2 the UCF form of test logic unit LB module carry chain pattern, by the constraint of this UCF, all logical blocks of VS1000 are configured to a carry chain of the snakelike connection in front and back as Fig. 3.For the test of logical block, constraint is divided into four classes: do not retrain, only retrain elementary cell, a constraint logic unit, constraint elementary cell and logical block.
Step 205: according to mapping circuit net table and test circuit unbound document, set up the placement position constraint information of the circuit unit after mapping and test circuit unbound document, set up the position constraint of the circuit unit after mapping and cell layout, layout is carried out to test circuit file.
Step 206: according to the circuit unit after layout and test circuit unbound document, particularly according to the signal routing constraint in test circuit unbound document, set up the constraint information mapping table of test cell signal and signal routing, press according to constraint information mapping table and signal routing rule, complete wiring, obtain the circuit meshwork list based on fpga chip positional information;
In embodiments of the present invention, the most scabrous problem of designing wiring resource module method of testing: design which type of test circuit and can cover each switch module of FPGA and six programmed point of each switch module as much as possible; Under the condition designing such test circuit, how to realize with placement-and-routing's instrument.This is developed a set of specially for the circuit structure of verilog hdl and the interconnection resource wiring rule of UCF of interconnection resource test, the implementation method of navigation-type placement-and-routing.Interconnection resource test point four large classes, wherein three classes as shown in Figure 4, and a class is in addition the connecting line of passage and the connection of various module pin.
Verilog hdl file describes the function of test circuit, UCF is the position of describing module on fpga chip and the mapping implementation of interconnection resource on fpga chip then, and in accordance with the wiring rule of the switch module developed and the rule of the signal routing process implementation in wiring.
The wiring rule of switch module be the routing model presetting switch module, Fig. 5 is the false code of a kind of wiring rule wherein, the wiring of the switch module SB of regulation different distributions, wiring unit can connect up according to this constraint rule, and the design sketch of final VS1000 configuration structure is as Fig. 7 (b).As shown in Figure 5, the wiring rule of SB is the setting to 9 class SB routing model: SB, the top SB of FPGA centronucleus, below SB, left side SB, the right SB, upper left corner SB, lower-left corner SB, right upper corner SB, lower right corner SB.The routing model of syntactic description SB can be identified with wiring unit, a certain namely in Fig. 4 Three models in UCF.
Signal routing rule principle is before wiring is carried out, just reserve the wiring channel resource required for wiring realization of signal in advance, specifically, pre-determine in UCF signal routing the node of process, theoretical based on VPR, routing path interconnection resource node (the Routing Resource Node of a signal, referred to as RR Node) describe, source node (Source Node) is comprised successively according to the direction of signal, the output node of module, gate contact (Channel Node), the input node of module, finally arrive drain junction point (Sink Node), as shown in Figure 6, wiring unit can according to the wiring of the prewiring rule treatments signal of UCF squadron signal.The test to interconnection resource can be realized like this based on the wiring rule of switch module and the rule of signal routing.Consider many fan-outs situation of signal in addition, propose all predetermined path and the predetermined path of part and without predetermined path.
The wiring rule of Fig. 7 (a) and (c) is the same with Fig. 7 (b).
Step 207: the circuit meshwork list and test circuit unbound document that obtain according to connecting up, code stream is carried out to test circuit file, obtain ASCII stream file ASCII, wherein, according to the constraint information produced based on code stream in the circuit meshwork list of fpga chip positional information and test circuit unbound document, completing code stream to produce, finally generating the ASCII stream file ASCII for testing;
Step 208: test fpga chip according to ASCII stream file ASCII, wherein, according to the constraint information produced based on code stream in the circuit meshwork list of fpga chip positional information and test circuit unbound document, completing code stream and produces, finally generating the ASCII stream file ASCII for testing.
Test result:
Adopt method of testing of the present invention, VS1000FPGA chip is tested, complete behavioral scaling test, transistor level test, wafer sort and irradiation test.The coverage rate of wherein testing is as shown in table 1, and the coverage rate of test function reaches 85%.
128 table with test results of the full chip testing of table 1
The method of testing of the field programmable gate array that the embodiment of the present invention provides, has following beneficial effect:
(1) FPGA design engineer can by the realization of this instrument to the test of the FPGA of behavioral scaling, transistor level, chip-scale and checking.
(2) correctness that realizes of result verification the method for checking and test and validity.
(3) this FPGA testing tool method for designing goes for the FPGA of other frameworks.
It should be noted last that, above embodiment is only in order to illustrate technical scheme of the present invention and unrestricted, although with reference to example to invention has been detailed description, those of ordinary skill in the art is to be understood that, can modify to technical scheme of the present invention or equivalent replacement, and not departing from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of right of the present invention.
Claims (8)
1. a method of testing for field programmable gate array, is characterized in that, comprises the steps:
Step 101: according to the structure of field programmable gate array chip, produces test circuit file;
Step 102: according to the structure of described field programmable gate array chip, produces test circuit unbound document;
Step 103: according to described test circuit unbound document, carries out comprehensively, obtaining comprehensive network table to described test circuit file;
Step 104: according to described test circuit unbound document and described comprehensive network table, map, set up mapping table to described test circuit file, according to described mapping table, obtains mapping circuit net table;
Step 105: according to described mapping circuit net table and described test circuit unbound document, layout is carried out to described test circuit file, obtains the circuit unit after layout;
Step 106: according to the circuit unit after described layout and test circuit unbound document, completes wiring to described test circuit file;
Step 107: the circuit meshwork list and described test circuit unbound document that obtain according to connecting up, carries out code stream to described test circuit file, obtains ASCII stream file ASCII;
Step 108: fpga chip is tested according to described ASCII stream file ASCII.
2. method according to claim 1, it is characterized in that, described test circuit file comprises the description of logical block class testing circuit, input-output unit class testing circuit describes, general interconnection resource class testing circuit describes and the resources-type test circuit of global routing describes.
3. method according to claim 1, is characterized in that, described test circuit unbound document comprises description unit mapping mode information, description unit layout information, describes signal routing information and describe input-output unit attribute information.
4. method according to claim 1, is characterized in that, described comprehensive method is: carried out comprehensively test circuit by synplify instrument.
5. method according to claim 1, it is characterized in that, the method of described mapping is: according to the unit descriptor of described comprehensive network table, test circuit unbound document, test the mappings constraint information of this unit corresponding in described test circuit unbound document respectively, set up mapping table, according to institute's mapping table, the packing of the elementary cell of the input-output unit class testing circuit of described test circuit file, and set the attribute of described elementary cell.
6. method according to claim 1, is characterized in that, the method for described layout is: according to cell layout's information of described mapping circuit net table and described test circuit unbound document, sets up the position constraint of the circuit unit after mapping and cell layout.
7. method according to claim 1, it is characterized in that, the method of described wiring is: according to the signal routing constraint in the circuit unit after layout and described test circuit unbound document, set up the constraint information mapping table of test cell signal and signal routing, according to described constraint information mapping table and signal routing rule, complete wiring, obtain the circuit meshwork list based on fpga chip positional information.
8. method according to claim 1, it is characterized in that, the method that described code stream produces is: the constraint information produced according to code stream in the described circuit meshwork list based on fpga chip positional information and described test circuit unbound document, completing code stream to produce, finally generating the ASCII stream file ASCII for testing.
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| CN112034331A (en) * | 2020-08-17 | 2020-12-04 | 北京时代民芯科技有限公司 | Circuit module testing method based on FPGA |
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| CN113761821A (en) * | 2021-09-15 | 2021-12-07 | 北京中科胜芯科技有限公司 | Modular semi-custom FPGA chip design method completed by automatic tool |
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