CN106202761B - The generation method of optimal netlist for large capacity FPGA circuitry functional simulation - Google Patents

The generation method of optimal netlist for large capacity FPGA circuitry functional simulation Download PDF

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CN106202761B
CN106202761B CN201610562716.XA CN201610562716A CN106202761B CN 106202761 B CN106202761 B CN 106202761B CN 201610562716 A CN201610562716 A CN 201610562716A CN 106202761 B CN106202761 B CN 106202761B
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resource
netlist
fpga
swb
optimal
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CN106202761A (en
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丛红艳
于宗光
闫华
胡凯
刘瑛
单悦尔
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Wuxi Zhongwei Yixin Co Ltd
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CETC 58 Research Institute
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Abstract

The present invention relates to a kind of generation methods of optimal netlist for large capacity FPGA circuitry functional simulation, can use the optimal netlist of resource dynamic generation according to FPGA circuitry.This method needs to obtain all unit names of top layer unit and example unit name in full chip netlist, obtains the configuration file of full chip netlist.Then it according to the resource distribution of FPGA circuitry placement-and-routing, by the mating corresponding configuration file of FPGA Software Create, is ready for navigating to the module resource of utilized FPGA, interconnection resource and configuration resource.Finally, the configuration file of required resource is added in full chip netlist, the optimal netlist for generating FPGA circuitry used resource is handled by script.The present invention can be pre-configured with certain function using FPGA, by taking different configuration files to obtain optimal netlist according to checking case demand.The present invention has the function of flexible dynamic configuration netlist, can save artificial resource, improves the emulator speed of service and verification efficiency, improves the coverage rate of verifying circuit to greatest extent.

Description

The generation method of optimal netlist for large capacity FPGA circuitry functional simulation
Technical field
The present invention relates to a kind of full chip netlist intercept method of verifying, especially a kind of function for large capacity FPGA circuitry The generation method for the optimal netlist that can be emulated, belongs to the technical field of programmable logic device.
Background technique
With the continuous fast development of semiconductor processing technology, the integrated level of chip is higher and higher, function is also increasingly stronger Greatly, the following chip checking complexity is also continuously improved, and the test case of a block system chip is just frightened enough in quantity It is also increasing to verify importance of the work in entire chip R&D process by people.
It include digital circuit and analog circuit, the electricity of circuit and semi-custom designs including custom design in fpga chip Road, while including a large amount of programmable resource.It must be done largely to verify the correctness of the logic function of entire fpga chip Verifying work, but the scale of circuit is bigger, net meter file up to 700MB, using based on candence company The emulation tool of the vcs of ncverilog and synosys company runs the functional simulation of large capacity circuit, needed for one-time authentication The time wanted may be up to one week, and verifying needs to spend the same time again again after discovery mistake.Meanwhile occupying a large amount of service Device resource.It is, therefore, desirable to provide one kind obtains optimal netlist method, this method should save artificial resource, can improve again imitative The true device speed of service improves verification efficiency.
Summary of the invention
The purpose of the present invention is overcoming the deficiencies in the prior art, artificial resource is saved, emulator operation speed is improved Degree improves verification efficiency, provides a kind of full chip netlist intercept method of large-scale circuit, this method can be according to different use-cases Flexible dynamic configuration netlist.
According to technical solution provided by the invention, the life of the optimal netlist for large capacity FPGA circuitry functional simulation The basic process executed at method is as follows:
Step 1: matching firstly the need of all unit names of acquisition and top layer unit example assumed name's word, the netlist for generating full chip Set file；
Step 2: then according to FPGA be pre-configured with logic function used in placement-and-routing's resource, generate needed for unit configuration Resource, and pass through the mating corresponding configuration file of FPGA Software Create；
Step 3: finally by taking different configuration files to obtain optimal netlist, specially by the configuration text of required resource Part is added in full chip netlist, and the optimal netlist for generating FPGA circuitry used resource is handled by script.
Specifically, step 2 is pre-configured with certain function by FPGA, each concrete use case is navigated to, and by mating FPGA software after placement-and-routing, selects each modular unit service condition, and defines the configuration module for needing to define, according to use-case Module resource, interconnection resource and configuration resource used, generates corresponding configuration file.
The modular unit service condition includes three kinds of situations, wherein adds " _ NULL " to indicate that this module is after unit name Sky, after unit name plus " _ SWB " indicates to only use the switch matrix of this module, and after unit name plus " _ ALL " expression is utilized The resource of the module.
FPGA is needed into process resource: programmable logic cells CLB, Digital Signal Processing DSP, storage unit BRAM, point For three types: CLB_ALL, CLB_NULL, CLB_SWB, DSP_ALL, DSP_NULL, DSP_SWB, BRAM_ALL, BRAM_ NULL, BRAM_SWB, and CLB_NULL, CLB_SWB, DSP_NULL, DSP_SWB, BRAM_ for needing to define configuration resource are described SWB, BRAM_NULL, and pass through the mating corresponding configuration file of FPGA Software Create.
The invention has the advantages that can be pre-configured with using FPGA according to checking case demand and just be able to achieve certain function, By taking different configuration files to obtain optimal netlist.The present invention has the function of flexible dynamic configuration netlist, can save imitative True resource improves the emulator speed of service, improves verification efficiency, improves the coverage rate of verifying circuit, Neng Gouman to greatest extent The demand of sufficient large-scale circuit functional simulation.
Detailed description of the invention
Fig. 1 large capacity FPGA circuitry top layer cellular construction schematic diagram.
Fig. 2 large capacity FPGA circuitry utilization of resources schematic diagram.
The product process figure of the optimal netlist of the full chip circuit of Fig. 3 large capacity.
BRAM resource structures schematic diagram used in Fig. 4 large capacity FPGA of the present invention.
Specific embodiment
The present invention will be further explained below with reference to the attached drawings and specific examples.
In order to save artificial resource, the emulator speed of service is improved.The invention proposes one kind to be used for large capacity The generation method of the optimal netlist of the functional simulation of FPGA circuitry.
As shown in Figure 1, being large capacity FPGA circuitry top layer cellular construction schematic diagram, since FPGA is integrated with programmable logic Unit (CLB), Digital Signal Processing (DSP), Clock management (CMT), storage unit (Block RAM, BRAM), clock module (CLK), the units such as system control module (CTRL), high-speed interface, wherein switch matrix Switch box (SWB) is connection CLB, DSP, BRAM, IO, CLK, the interconnection hinge between the modules such as high-speed interface, it is switched by a large amount of MUX, and (data select Device), SRAM (static random access memory) and coiling composition are configured, is dispersed throughout each position of fpga chip, therefore verify whole Net meter file required for the correctness of the logic function of a fpga chip is very big, and the time required for one-time authentication is also very It is long.The present invention can select automatically resource used, wherein Fig. 1 dash area is a certain concrete use case institute according to different use-cases The resource used generates optimal function netlist, the efficiency of Lai Tisheng simulation velocity and debugging.It can be matched in advance using FPGA Certain function is set, by taking different configuration files to obtain optimal netlist.
The full resources of chip of large capacity is using schematic diagram as shown in Fig. 2, the present invention can automatically select out from fpga chip netlist Unit therefor resource configures resource and interconnection resource, generates optimal netlist resource, can greatly save artificial resource, improves imitative The true device speed of service improves verification efficiency.
The optimal netlist specific flow chart of the full chip circuit of large capacity is generated as shown in figure 3, first by cadence company The netlist that virtuoso software extracts extensive full chip circuit generates module.list by script 1, and searches large capacity Each functional module name in the netlist of full chip circuit, the module of its submodule is searched further according to the module name of top-level module, Such recurrence carries out, the net until all these modules module and submodule module all to be covered to full chip Table generates the configuration file of full chip netlist.The configuration file includes all modular unit names of FPGA and example assumed name, module list Member be broadly divided into needs process resource be mainly (CLB, DSP, BRAM), be not required to resource to be processed be mainly (IO, CLK, CTRL)。
Secondly, needing to configure resource according to FPGA circuitry used resource by the selection of script 2, mainly navigating to each use Example, is pre-configured with certain function according to FPGA, after placement-and-routing, selects each modular unit service condition, (is generally divided into three kinds Situation wherein adds " _ NULL " to indicate this module as sky after unit name, after unit name plus " _ SWB " expression only uses opening for this module Matrix Switch box is closed, " _ ALL " is added to indicate the resource that the module is utilized after unit name), and define the configuration for needing to define Module.By taking BRAM as an example, as shown in figure 4, the entitled BRAM_ALL of unit indicates utilization of resources BRAM resource and adjacent SWB, BRAM_SWB are that BRAM resource is not used, and using the interconnection resource of adjacent S WB, BRAM_NULL indicates that BRAM money is not used Source and SWB.Process resource (CLB, DSP, BRAM) is needed to be divided into three types (CLB_ALL, CLB_NULL, CLB_ FPGA SWB, DSP_ALL, DSP_NULL, DSP_SWB, BRAM_ALL, BRAM_NULL, BRAM_SWB) and describe to need to define configuration money CLB_NULL, CLB_SWB, DSP_NULL, DSP_SWB, the BRAM_SWB in source, BRAM_NULL, by mating FPGA Software Create phase The configuration file answered.
Finally, the example assumed name for needing the unit optimized is searched according to corresponding configuration file by script 3, it is automatic excellent Change unit, generates the optimal net meter file of used resource.The optimal netlist generation method, just for specific case use-case, choosing FPGA resource used is selected, circuit simulation speed is greatly improved.
The script 1, script 2, script 3 are the program write in FPGA.
The present invention can be pre-configured with using FPGA according to checking case demand and just be able to achieve certain function, by taking Different configuration files obtains optimal netlist.The present invention has the function of flexible dynamic configuration netlist, can save artificial resource, mention The high emulator speed of service improves verification efficiency, improves the coverage rate of verifying circuit to greatest extent, can satisfy large capacity electricity The demand of road functional simulation.

Claims (3)

1. the generation method of the optimal netlist for large capacity FPGA circuitry functional simulation, it is characterized in that:
Step 1: firstly the need of all unit names and top layer unit example assumed name's word is obtained, generating the netlist configuration text of full chip Part；
Step 2: then according to FPGA be pre-configured with logic function used in placement-and-routing's resource, generate needed for unit configuration money Source, and pass through the mating corresponding configuration file of FPGA Software Create；
It is pre-configured with certain function by FPGA, navigates to each concrete use case, and pass through mating FPGA software, placement-and-routing Afterwards, each modular unit service condition is selected, and defines the configuration module for needing to define, the module resource according to used in use-case, cloth Line resource and configuration resource, generate corresponding configuration file；
Step 3: finally by taking different configuration files to obtain optimal netlist, specially adding the configuration file of required resource Enter into full chip netlist, the optimal netlist for generating FPGA circuitry used resource is handled by script.
2. the generation method of the optimal netlist according to claim 1 for large capacity FPGA circuitry functional simulation, special Sign is: the modular unit service condition includes three kinds of situations, and " _ NULL " is wherein added to indicate that this module is sky after unit name, After unit name plus " _ SWB " indicates to only use the switch matrix of this module, adds " _ ALL " expression that the mould is utilized after unit name The resource of block.
3. the generation method of the optimal netlist according to claim 2 for large capacity FPGA circuitry functional simulation, special Sign is: FPGA is needed process resource: programmable logic cells CLB, Digital Signal Processing DSP, storage unit BRAM are divided into three Seed type: CLB_ALL, CLB_NULL, CLB_SWB, DSP_ALL, DSP_NULL, DSP_SWB, BRAM_ALL, BRAM_NULL, BRAM_SWB, and CLB_NULL, CLB_SWB, DSP_NULL, DSP_SWB, BRAM_SWB for needing to define configuration resource are described, BRAM_NULL, and pass through the mating corresponding configuration file of FPGA Software Create.
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CN107122565B (en) * 2017-05-12 2019-08-30 山东大学 FPGA BRAM framework and design method based on nonvolatile memory
CN108052769A (en) * 2017-12-28 2018-05-18 天津芯海创科技有限公司 Netlist emulation verification method and device
CN110874517A (en) * 2018-08-10 2020-03-10 北京大学 Method for rapidly verifying connection correctness of FPGA (field programmable Gate array) interconnection line
CN110046394B (en) * 2019-03-20 2019-12-27 广东高云半导体科技股份有限公司 Integrated circuit network table generating method and device, computer equipment and storage medium
CN110889257B (en) * 2019-09-30 2023-02-24 深圳市紫光同创电子有限公司 Method for generating netlist through FPGA circuit verification and circuit logic verification platform
CN111027266A (en) * 2019-12-06 2020-04-17 思尔芯(上海)信息科技有限公司 Method, system, storage medium and terminal for designing and dividing multiple FPGAs
CN111142013B (en) * 2019-12-31 2021-12-07 无锡市同飞科技有限公司 MAX7000 series CPLD (Complex programmable logic device) based logic reduction method
CN112632884B (en) * 2020-12-23 2023-03-03 海光信息技术股份有限公司 Gate-level netlist generation method and device and electronic equipment
CN112651199B (en) * 2020-12-24 2023-08-29 山东高云半导体科技有限公司 Quality Verification Platform and Quality Verification Method
CN116011374B (en) * 2023-01-28 2024-04-05 广东高云半导体科技股份有限公司 Method, device, computer storage medium and terminal for realizing wiring resource verification

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