CN101753011B - Behavioral scaling model of charge pump circuit suitable for spice scaling emulation - Google Patents
Behavioral scaling model of charge pump circuit suitable for spice scaling emulation Download PDFInfo
- Publication number
- CN101753011B CN101753011B CN200810044105A CN200810044105A CN101753011B CN 101753011 B CN101753011 B CN 101753011B CN 200810044105 A CN200810044105 A CN 200810044105A CN 200810044105 A CN200810044105 A CN 200810044105A CN 101753011 B CN101753011 B CN 101753011B
- Authority
- CN
- China
- Prior art keywords
- control signal
- charge pump
- transmission gate
- transistor transmission
- spice
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Electronic Switches (AREA)
Abstract
The present invention discloses a modeling approach of a behavioral scaling model of a charge pump circuit suitable for spice scaling emulation, which at least comprises MOS transistor transmitting doors of two floating substrates which are connected in parallel for realizing the selection of output voltage for input voltage provided by a power source. By converting an input control signal of the charge pump circuit into a control signal which can correctly control the MOS transistor transmitting doors through a level converting circuit, the final output state of the MOS transistor transmitting doors is controlled.
Description
Technical field
The present invention relates to the modeling method of the behavioral scaling model of the grade simulated charge pump circuit of a kind of spice of being applicable to.
Background technology
In the process of emulation Flash (flash memory) circuit high-voltage performance, common way is charge pump (charge pump) directly to be introduced carry out emulation.And speed is slower can cause using the simulator emulation of spice level like this time; Because the mode of operation of flash is more; In audit function, also need check high pressure electric leakage (leakage) and discharge (discharge) time of flash, and the inspection of these performances often need be carried out boundary condition (corner) analysis.The length of system emulation time directly influences the cycle of design.Through analyzing, after emulation platform (test bench) is optimized, find that the emulation of charge pump is the principal element that influences simulation time.
In order to accelerate simulation velocity, just need provide " behavioral scaling " model to accelerate simulation velocity, because be performance simulation, so still adopt the simulator of spice level (spice level) to carry out emulation.Can adopt verilog A language to realize the behavioral scaling model of charge pump now, also can in eldo, use the particular functionality piece to realize the behavioral scaling model of charge pump.But the functional block of verilog A and eldo all depends on specific simulator.Verilog A and common circuit integrated emulation need be with high level softwares such as AMS, and the functional block among the eldo only is applicable to eldo, and be incompatible with other simulator.So above-mentioned charge pump behavioral scaling model can not be used on the simulator of spice level.
Summary of the invention
The technical problem that the present invention will solve provides the modeling method of the behavioral scaling model of the grade simulated charge pump circuit of a kind of spice of being applicable to, it can use in the grade simulated device of spice and improve simulation velocity.
For solving the problems of the technologies described above, said behavioral scaling model of the present invention comprises a nmos pass transistor transmission gate or a PMOS transistor transmission gate at least;
The negative voltage of the input voltage of said nmos pass transistor transmission gate for providing by spice power supply storehouse; The control signal of nmos pass transistor transmission gate gets through the conversion of first level shifting circuit for the input control signal by charge pump circuit; Make said nmos pass transistor transmission gate be output as input voltage or floating empty, thereby realize the behavior of negative voltage charge pump;
The positive voltage of the input voltage of said PMOS transistor transmission gate for providing by spice power supply storehouse; The control signal of PMOS transistor transmission gate gets through the conversion of second level shifting circuit for the input control signal by charge pump circuit; Make said PMOS transistor transmission gate be output as input voltage or floating empty, thereby realize the behavior of positive voltage charge pump.
The present invention also provides the modeling method of the behavioral scaling model of the grade simulated charge pump circuit of a kind of spice of being applicable to; At least comprise a group in two groups of MOS transistor transmission gates, two groups of MOS transistor transmission gates are respectively that nmos pass transistor transmission gate by two substrates of floating is formed in parallel and are formed in parallel by the PMOS transistor transmission gate of two substrates of floating;
The input voltage of said two nmos pass transistor transmission gates is respectively negative voltage VNEG1 and the VNEG2 that is provided by spice power supply storehouse; The control signal of said two nmos pass transistor transmission gates gets through the conversion of first level shifting circuit respectively for the input control signal by charge pump circuit; Make the nmos pass transistor transmission gate of the substrate of floating of said two parallel connections be output as selection or floating sky, thereby realize the behavior of negative voltage charge pump input voltage VNEG1 and VNEG2;
Positive voltage VPOS1 and the VPOS2 of the input voltage of said two PMOS transistor transmission gates for providing by spice power supply storehouse; The control signal of said two PMOS transistor transmission gates gets through the conversion of second level shifting circuit respectively for the input control signal by charge pump circuit; Make the PMOS transistor transmission gate of the substrate of floating of said two parallel connections be output as selection or floating sky, thereby realize the behavior of positive voltage charge pump input voltage VPOS1 and VPOS2.
The modeling method that is applicable to the behavioral scaling model of the charge pump circuit that spice is grade simulated of the present invention; Adopt the power supply storehouse that concrete potential value is provided; Utilize the transmission gate that transistor builds and level conversion (level shift) circuit of associated control signal; Utilize the state of each transmission gate of control signal control, finally realize the variation of output level.This model can substitute the high-voltage performance emulation that charge pump carries out the flash circuit, comprises function, electric leakage, the emulation of discharge time.Adopt this model and flash circuit to carry out collaborative simulation, accelerated simulation velocity greatly, reduced the design verification cycle.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:
Fig. 1 is the instantiation of nmos pass transistor transmission gate in the behavioral scaling model of the present invention;
Fig. 2 is the instantiation of PMOS transistor transmission gate in the behavioral scaling model of the present invention;
Fig. 3 is the module diagram of first level shifting circuit among the present invention;
Fig. 4 is the module diagram of second level shifting circuit among the present invention.
Embodiment
The modeling method that is applicable to the behavioral scaling model of the charge pump circuit that spice is grade simulated of the present invention; Adopt spice power supply storehouse that concrete potential value is provided; Utilize transistor to build the level conversion of transmission gate and associated control signal (level shift) circuit; Utilize the state of each transmission gate of control signal control, finally realize the variation of output level, accomplish emulation charge pump circuit.
The basic boom of behavioral scaling model of the present invention is: comprise a nmos pass transistor transmission gate or a PMOS transistor transmission gate at least; Wherein the input voltage of nmos pass transistor transmission gate is the negative voltage that is provided by spice power supply storehouse; The control signal of nmos pass transistor transmission gate gets through the conversion of first level shifting circuit for the input control signal by charge pump circuit; Make the nmos pass transistor transmission gate be output as input voltage or floating empty, thereby realize the behavior of negative voltage charge pump; Wherein the input voltage of PMOS transistor transmission gate is the positive voltage that is provided by spice power supply storehouse; The control signal of PMOS transistor transmission gate gets through the conversion of second level shifting circuit for the input control signal by charge pump circuit; Make PMOS transistor transmission gate be output as input voltage or floating empty, thereby realize the behavior of positive voltage charge pump.
The present invention also provides the framework of the behavioral scaling model of a kind of emulation charge pump behavior; It is: comprise in two groups of MOS transistor transmission gates one group at least; These two groups of MOS transistor transmission gates are respectively by two substrate nmos pass transistor transmission gates of floating and are formed in parallel and are formed in parallel by two substrate PMOS transistor transmission gates of floating; Wherein the nmos pass transistor transmission gate is used to transmit negative high voltage (for input control signal), and PMOS transistor transmission gate is used to transmit positive high voltage (for input control signal).The nmos pass transistor transmission gate (see figure 1) of the substrate of floating of two parallel connections; Utilize the control signal pen of transmission gate and the output VNEG of pent control transmission door to equal VNEG1 or VNEG2 or floating empty, wherein VNEG1 and VNEG2 negative voltage for providing by spice power supply storehouse.And the similar (see figure 2) of PMOS transistor transmission gate of the substrate of floating of two parallel connections; Utilize transmission gate control signal pep and pept to control the transistorized output of PMOS VPOS and be VPOS1 or VPOS2 or floating empty, wherein VPOS1 and VPOS2 positive voltage for providing by spice power supply storehouse.Control signal pen wherein, pent, pep and pept be respectively by the input control signal penin of charge pump circuit, pen2in, and pepin and pep2in convert through level shifting circuit.In the nmos pass transistor transmission gate; Control signal pen and pent are for converting (see figure 3) with the input control signal penin of charge pump circuit with pen2in warp first level shifting circuit respectively; Principle is: as said input control signal penin or (with) pen2in is zero level Vgnd, first level shifting circuit is used for converting this input control signal the control signal of a less value of the negative voltage VNEG1 that provided by spice power supply storehouse and VNEG2 as the nmos pass transistor transmission gate to; Like input control signal penin or pen2in is high level Vpwr, and first level shifting circuit is used for directly exporting the control signal of this high level Vpwr as the nmos pass transistor transmission gate.And in PMOS transistor transmission gate; Control signal pep and pept are for converting (see figure 4) with the input control signal pepin of charge pump circuit with pep2in warp second level shifting circuit respectively; As said input control signal pepin or (with) pep2in is zero level Vgnd, second level shifting circuit is used for converting this input control signal the control signal of a bigger value of the positive voltage VPOS1 that provided by said spice power supply storehouse and VPOS2 as PMOS transistor transmission gate to; Like input control signal pepin or pep2in is high level Vpwr, and second level shifting circuit is used for directly exporting the control signal of zero level Vgnd as PMOS transistor transmission gate.In charge pump circuit emulation; Input control signal penin; Pen2in; Pepin and pep2in are the category [being generally 0 (representing with vgnd) or 1 (representing with vpwr)] of the normal pressure in this area, and output voltage V NEG and VPOS belong to the category of negative high voltage and positive high voltage respectively with respect to input control signal.In the concrete Simulation Application, need export type and the number that number and output type (negative high voltage or positive high voltage) come the MOS transistor transmission gate group of design demand through designing requirement.
According to the design objective of charge pump circuit, set the power values that spice power supply storehouse provides, the size of design transmission gate, purpose is that output voltage is conformed to design objective, and conducting resistance is conformed to design objective with the pass resistance break.Charge pump like need emulation has a plurality of current potentials, just adopts the MOS transistor transmission gate of the substrate of floating of a plurality of parallel connections, and spice power supply storehouse provides a plurality of corresponding power supplys, promptly expands to the behavioral scaling model of many level outlet selector.Utilize the NMOS transmission gate and first level shifting circuit because of behavioral scaling model of the present invention and can describe the behavior of negative voltage charge pump; Utilize the PMOS transmission gate and second level shifting circuit can describe the behavior of positive voltage charge pump.The number that increases MOS transmission gate and level shifting circuit just can realize the adjusting of charge pump output level state: for example adopt two NMOS transmission gates and two first selections (VNEGl, VNEG2 or floating empty) that level shifting circuit just can be realized exporting.Thereby the charge pump behavioral scaling model that this transmission gate and level shifting circuit constitute can be extended to the behavioral scaling model of many level output select circuit.The behavioral scaling model of expansion negative voltage charge pump realizes the level selection behavior level circuit model of negative voltage; Expansion positive voltage charge pump is realized the level selection behavior level circuit model of positive voltage.Make up the level selection behavior level circuit model that these two kinds of behavioral scaling model can realize generating positive and negative voltage.
Behavioral scaling model of the present invention can substitute the high-voltage performance emulation that charge pump carries out the flash circuit, comprises function, electric leakage, the emulation of discharge time.Employing behavior level model and flash circuit carry out collaborative simulation, have accelerated simulation velocity greatly, have reduced the design verification cycle.
Simultaneously, because of behavioral scaling model of the present invention can be used the description of spice form net table, thereby can select the simulator emulation of any compatible spice form net table.The schematic view and the symbol view of this model can also be in the environment of cadence, generated, thereby the emulation of cadence ADE simulated environment can be utilized.Through the size of control transmission door, restriction electric current transmitted, thereby the method for detection load capacity.
Behavioral scaling model of the present invention realizes any node different time, the particular state under the different mode through control input signals.Such behavioral scaling model can substitute original charge pump circuit and carry out the high pressure conditions of flash circuit and the performance simulation of test pattern.
Can with the behavior level model symbol view and other circuit unite and build test bench, be convenient to third party's inspection, thereby accelerate the whole R&D cycle.The test bench that uses behavior model of the present invention and other circuit to form does not receive the restriction of simulator; And use behavior model model of the present invention can accelerate simulation speed greatly, shorten emulation and assessment cycle.
Claims (6)
1. modeling method that is applicable to the behavioral scaling model of the charge pump circuit that spice is grade simulated is characterized in that:
Said behavioral scaling model comprises a nmos pass transistor transmission gate or a PMOS transistor transmission gate at least;
The negative voltage of the input voltage of said nmos pass transistor transmission gate for providing by spice power supply storehouse; The control signal of nmos pass transistor transmission gate gets through the conversion of first level shifting circuit for the input control signal by charge pump circuit; Make said nmos pass transistor transmission gate be output as input voltage or floating empty, thereby realize the behavior of negative voltage charge pump;
The positive voltage of the input voltage of said PMOS transistor transmission gate for providing by spice power supply storehouse; The control signal of PMOS transistor transmission gate gets through the conversion of second level shifting circuit for the input control signal by charge pump circuit; Make said PMOS transistor transmission gate be output as input voltage or floating empty, thereby realize the behavior of positive voltage charge pump.
2. according to the modeling method of the described behavioral scaling model of claim 1, it is characterized in that: the input voltage that said spice power supply storehouse provides is according to wanting the designing requirement of the charge pump circuit of emulation to select.
3. modeling method that is applicable to the behavioral scaling model of the charge pump circuit that spice is grade simulated is characterized in that:
At least comprise a group in two groups of MOS transistor transmission gates in the said behavioral scaling model, said two groups of MOS transistor transmission gates are respectively that nmos pass transistor transmission gate by two substrates of floating is formed in parallel and are formed in parallel by the PMOS transistor transmission gate of two substrates of floating;
The input voltage of said two nmos pass transistor transmission gates is respectively negative voltage VNEG1 and the VNEG2 that is provided by spice power supply storehouse; The control signal of said two nmos pass transistor transmission gates gets through the conversion of first level shifting circuit respectively for the input control signal by charge pump circuit; Make the nmos pass transistor transmission gate of the substrate of floating of said two parallel connections be output as selection or floating sky, thereby realize the behavior of negative voltage charge pump input voltage VNEG1 and VNEG2;
Positive voltage VPOS1 and the VPOS2 of the input voltage of said two PMOS transistor transmission gates for providing by spice power supply storehouse; The control signal of said two PMOS transistor transmission gates gets through the conversion of second level shifting circuit respectively for the input control signal by charge pump circuit; Make the PMOS transistor transmission gate of the substrate of floating of said two parallel connections be output as selection or floating sky, from realizing the behavior of positive voltage charge pump to input voltage VPOS1 and VPOS2.
4. according to the modeling method of the described behavioral scaling model of claim 3, it is characterized in that: the input voltage that said spice power supply storehouse provides is according to wanting the designing requirement of the charge pump circuit of emulation to select.
5. according to the modeling method of the described behavioral scaling model of claim 3; It is characterized in that: like said input control signal is zero level, and said first level shifting circuit is used for converting this input control signal the control signal of a less value of the negative voltage that provided by said spice power supply storehouse as the nmos pass transistor transmission gate to; Like input control signal is high level, and said first level shifting circuit is used for directly exporting the control signal of this high level as the nmos pass transistor transmission gate.
6. according to the modeling method of the described behavioral scaling model of claim 3; It is characterized in that: like said input control signal is zero level, and said second level shifting circuit is used for converting this input control signal the control signal of a bigger value of the positive voltage that provided by said spice power supply storehouse as PMOS transistor transmission gate to; Like input control signal is high level, and said second level shifting circuit is used for directly exporting the control signal of zero level as PMOS transistor transmission gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810044105A CN101753011B (en) | 2008-12-16 | 2008-12-16 | Behavioral scaling model of charge pump circuit suitable for spice scaling emulation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810044105A CN101753011B (en) | 2008-12-16 | 2008-12-16 | Behavioral scaling model of charge pump circuit suitable for spice scaling emulation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101753011A CN101753011A (en) | 2010-06-23 |
| CN101753011B true CN101753011B (en) | 2012-10-03 |
Family
ID=42479528
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200810044105A Active CN101753011B (en) | 2008-12-16 | 2008-12-16 | Behavioral scaling model of charge pump circuit suitable for spice scaling emulation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101753011B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102081686B (en) * | 2010-12-21 | 2016-04-27 | 上海集成电路研发中心有限公司 | The modeling method of MOS transistor process corner SPICE model |
| CN102542090B (en) * | 2010-12-29 | 2014-07-16 | 联芯科技有限公司 | Average model applicable to charge pump circuit and method for constructing average model |
| CN103138566B (en) * | 2011-11-23 | 2015-10-14 | 上海华虹宏力半导体制造有限公司 | Single charge pump exports the control circuit of multiple high pressure |
| KR102284656B1 (en) | 2014-07-31 | 2021-08-02 | 삼성전자 주식회사 | Method for simulating electronic circuit comprising charge pump |
| CN108875192B (en) * | 2018-06-11 | 2022-10-25 | 北京航空航天大学 | Simulation method for extreme low-temperature characteristics of typical CMOS (complementary metal oxide semiconductor) device |
| CN109617395B (en) * | 2018-12-27 | 2020-10-13 | 西安紫光国芯半导体有限公司 | Method and circuit for improving conversion efficiency of charge pump and charge pump |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1399407A (en) * | 2001-07-26 | 2003-02-26 | 中国科学院微电子中心 | Bootstrap-complementary transmission gate charge-restoring low-power consumption circuit structure |
| CN1472746A (en) * | 2002-07-08 | 2004-02-04 | ���ǵ�����ʽ���� | Double port static memory unit and semiconductor device therewith |
| CN1779768A (en) * | 2004-11-17 | 2006-05-31 | 上海华园微电子技术有限公司 | LCOS pixel voltage generating circuit |
| CN101038617A (en) * | 2006-03-17 | 2007-09-19 | 上海华虹集成电路有限责任公司 | Clock recovery circuit used in non-contact IC card and radio frequency identification label |
-
2008
- 2008-12-16 CN CN200810044105A patent/CN101753011B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1399407A (en) * | 2001-07-26 | 2003-02-26 | 中国科学院微电子中心 | Bootstrap-complementary transmission gate charge-restoring low-power consumption circuit structure |
| CN1472746A (en) * | 2002-07-08 | 2004-02-04 | ���ǵ�����ʽ���� | Double port static memory unit and semiconductor device therewith |
| CN1779768A (en) * | 2004-11-17 | 2006-05-31 | 上海华园微电子技术有限公司 | LCOS pixel voltage generating circuit |
| CN101038617A (en) * | 2006-03-17 | 2007-09-19 | 上海华虹集成电路有限责任公司 | Clock recovery circuit used in non-contact IC card and radio frequency identification label |
Non-Patent Citations (1)
| Title |
|---|
| 方伟等.仿真在NMOS电路设计中的应用.《微处理机》.2005,(第2期),第21-22页. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101753011A (en) | 2010-06-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101753011B (en) | Behavioral scaling model of charge pump circuit suitable for spice scaling emulation | |
| CN104865518B (en) | A kind of CLB dynamic collocation methods of SRAM type FPGA | |
| CN103678745B (en) | Cross-platform multi-level integrated design system for FPGA | |
| CN103914580B (en) | A kind of method for the emulation of FPGA circuitry bit stream | |
| CN102129847A (en) | Gamma reference voltage output circuit of source driver | |
| Bryant | A switch-level simulation model for integrated logic circuits | |
| CN101499937A (en) | Software and hardware collaborative simulation verification system and method based on FPGA | |
| CN101539958A (en) | Method and device for designing standard cell library and integrated circuit | |
| CN102866349A (en) | Integrated circuit testing method | |
| CN105005015A (en) | Circuit fault simulation system based on hardware circuit fault injection | |
| CN105718644A (en) | Field-programmable gate array netlist generation method and device | |
| CN100535868C (en) | Real-time bit true simulation development system and method thereof | |
| CN201522707U (en) | Software and hardware cooperated simulation verification system based on FPGA | |
| CN105869601A (en) | Grid driving method and circuit and display device comprising grid driving circuit | |
| KR19980080808A (en) | Manufacturing Method of Integrated Circuit Device and Logic Inspection Method for Integrated Circuit Device | |
| CN101741374B (en) | Voltage level converter without phase distortion | |
| CN107517055B (en) | Design method of CMOS digital logic circuit | |
| CN105740579A (en) | Building method for connecting UVM verification platform | |
| CN103346780A (en) | Reusable logical gate of mixed structure of MOS transistor and single-electron transistor | |
| US8082139B1 (en) | Displaying signals of a design block emulated in hardware co-simulation | |
| CN103440391A (en) | Semiconductor process corner scanning and simulating method based on numerical value selection function | |
| CN103309781B (en) | The detection method of the single multiplying power Synchronous dynamic RAM based on DSP and FPGA | |
| CN107526585A (en) | FPGA development platforms and its debugging, method of testing based on Scala | |
| Alt et al. | Simulation of non-classical faults on the gate level-fault modeling | |
| CN107679282A (en) | The emulation mode and simulator of charge pump |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140108 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20140108 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |