CN101539958B - Method and device for designing standard cell library and integrated circuit - Google Patents
Method and device for designing standard cell library and integrated circuit Download PDFInfo
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- CN101539958B CN101539958B CN2008101021635A CN200810102163A CN101539958B CN 101539958 B CN101539958 B CN 101539958B CN 2008101021635 A CN2008101021635 A CN 2008101021635A CN 200810102163 A CN200810102163 A CN 200810102163A CN 101539958 B CN101539958 B CN 101539958B
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Abstract
The invention discloses a method and a device for designing a standard cell library. The method comprises a step of designing a common standard cell, and also comprises a step of designing a double-edge flip-flop cell, and the step of designing the double-edge flip-flop cell comprises: when determining the type of the standard cell, adding the double-edge flip-flop cell to the standard cell type; designing a schematic diagram of the double-edge flip-flop cell; and designing a diagram of the double-edge flip-flop cell. A mold of the double-edge flip-flop cell is established, and the method for establishing the mold comprises the following steps of: establishing a rising edge comprehensive library and a falling edge comprehensive library for the double-edge flip-flop; and establishing a double-edge flip-flop simulated library for the double-edge flip-flop. The invention also discloses a method and a device for designing an integrated circuit. Due to the method and the device, the rising edge and the falling edge for each jump of the clock signal can serve the logical function of a chip, so that the jumping frequency of the clock, needed to complete the same logical function, is reduced, and the dynamic energy consumption of the circuit is also lowered.
Description
Technical field
The present invention relates to the integrated circuit (IC) design field, relate in particular to the method for designing and the device of a kind of standard cell lib and integrated circuit.
Background technology
The design of CMOS (Complementary Metal-Oxide Semiconductor, CMOS) digital IC (Integrated Circuit, integrated circuit) can be divided into full Custom Design and semi-custom designs.Full Custom Design is a kind of method for designing based on transistor level, and all devices, interconnection and the domain of circuit all adopt direct design.Semi-custom designs is divided into again based on gate array with based on the design of standard cell lib.
Design based on standard cell lib is meant some basic logic units in the circuit design (as gate circuit, multi-way switch, trigger etc.), principle design according to optimal design, and deposit in the standard cell lib as standard block, when carrying out integrated circuit (IC) design, from standard cell lib, call required standard block according to circuit requirement, carry out AUTOMATIC LOGIC SYNTHESIS and automatic placement and routing, finish the design of circuit.
Based on the digital IC method for designing flow process of standard cell lib as shown in Figure 1, concrete steps are as follows:
(1) carries out the design of RTL (Register TransferLevel, register transfer level) level.
This stage utilizes HDL (Hardware Description Language, hardware description language) to describe the RTL behavior model, and verifies by emulation tool whether its function is correct.
(2) carry out ASIC (Application Specific Integrated Circuit, special IC) logic synthesis.
The ASIC logic synthesis is meant passes through mapping and optimizing process on the basis of technology library, the rtl description of design is converted to and the closely-related gate level netlist of technology.In ASIC logic synthesis process, the deviser can add various constraint conditions according to the needs of oneself, makes ASIC logic synthesis result satisfy designing requirement.
In order in time to find and debug, the gate level netlist that also needs logic synthesis is obtained carries out gate leve emulation, if find that in emulation the logic function mistake maybe can not satisfy the sequential requirement, then needing to return logic synthesis stage or HDL Code Design stage corrects a mistake, till simulation result meets the requirements.
(3) carry out the laying out pattern wiring.
Robotization placement-and-routing instrument can read in the gate level netlist that comprehensively generates, and cooperates with technology physical message storehouse and timing sequence library, carries out the placement-and-routing of entire chip.
In order to verify that whether domain exists logic function or sequential mistake, also needs to carry out post-simulation.
At last, also need domain is carried out DRC (Design Rule Checker, DRC) and LVS (Layout Versus Schematic, the domain logic function is checked) inspection, to guarantee that the domain function is correct and not have design rule and circuit mistake.
(4) layout data is carried out flow, obtain final chip.
Along with enlarging day by day of integrated circuit (IC) chip scale and improving constantly of integrated level, the low power design technique of seeking to reduce the chip power loss becomes a focus of current integrated circuit (IC) design.Present integrated circuit is mainly based on CMOS technology.The CMOS power consumption of integrated circuit is mainly derived from the dynamic power consumption in each node potential saltus step process in the chip, and this dynamic power consumption accounts for 70% to 90% of whole IC power consumption, therefore reduces the main direction that dynamic power consumption is the low power design technique development.
Design to synchronizing circuit has accounted for very most of in current integrated circuit (IC) design.So-called synchronizing circuit, promptly the data latching in the circuit is the circuit of being controlled by one or more clock signals that are distributed in the circuit.Comprise three kinds of primary structures in the synchronizing circuit: combinational logic, sequential logic and clock distributing network, the relation between three kinds of primary structures in the synchronizing circuit as shown in Figure 2.
Wherein, combinational logic is used for realizing that various logic calculates; Sequential logic is used for storing the logical value that is calculated by combinational logic as storage unit; Clock distributing network is used for providing correct clock signal to the sequential logic of entire circuit, to reach the purpose that makes the entire circuit true(-)running.As can be seen from Figure 2, the effect of clock distributing network in synchronizing circuit is extremely important, provides correct clock signal can avoid occurring race hazard and logic error in synchronizing circuit.The sequential of the clock signal of each sequential logic unit of only guaranteed arrival (comprising register, latch) is correct, could guarantee that the sequential logic unit latched in each clock period to obtain correct logical value, thereby guarantee the correct of entire circuit function.Current clock distributing network relatively more commonly used is a kind of tree structure, as shown in Figure 3.
In sequential logic system, the realization of logic function is that the upset that relies on time clock to trigger trigger realizes that the time clock in the sequential logic system is unique always at the signal of saltus step, is one of main source of system dynamics power consumption.
In traditional standard cell lib, what sequential logic unit, basis adopted is monolateral along trigger, its upset only relies on some edges (rising edge or negative edge) of clock to trigger, the saltus step at another one edge is not utilized, monolateral have only 50% along trigger to the utilization factor of clock, clock can not get sufficient utilization, therefore, has also caused the waste of dynamic power consumption.
Summary of the invention
In view of this, the purpose of the embodiment of the invention is to provide the method for designing and the device of a kind of standard cell lib and integrated circuit, make two edges of clock signal to be utilized, reduce the number of time clock for the identical logic function of realization, thereby effectively reduced the dynamic power consumption of circuit.
For achieving the above object, on the one hand, the embodiment of the invention provides a kind of method for designing of standard cell lib, comprises the step of design common standard unit, also comprises the step of design dual-edge trigger unit, and the step of described design dual-edge trigger unit comprises:
The unit kind time-like that settles the standard adds described dual-edge trigger unit in the standard block kind to;
Design the schematic diagram of described dual-edge trigger unit;
Design the domain of described dual-edge trigger unit;
To the unit modeling of described dual-edge trigger, the method for described modeling is:
For described dual-edge trigger is set up comprehensive storehouse of rising edge and the comprehensive storehouse of negative edge;
For described dual-edge trigger is set up the dual-edge trigger simulated library.
The described method of setting up comprehensive storehouse of rising edge and the comprehensive storehouse of negative edge for described dual-edge trigger is specially:
The logic function of described dual-edge trigger unit is designated as the rising edge flip-flop element, and uses modeling tool that it is carried out modeling, obtain the comprehensive storehouse of described rising edge;
The logic function of described dual-edge trigger unit is designated as the negative edge flip-flop element, and uses modeling tool that it is carried out modeling, obtain the comprehensive storehouse of described negative edge.
The described method of setting up the dual-edge trigger simulated library for described dual-edge trigger is specially:
The logic function of described dual-edge trigger unit is designated as the rising edge flip-flop element, and uses modeling tool that it is carried out modeling, obtain the rising edge simulated library;
The logic function of described dual-edge trigger unit is designated as the negative edge flip-flop element, and uses modeling tool that it is carried out modeling, obtain the negative edge simulated library;
The model file of described rising edge simulated library and described negative edge simulated library is merged, keep the non-functional description part, functional description partly is revised as the functional description of described dual-edge trigger unit, obtain described dual-edge trigger simulated library.
On the other hand, the embodiment of the invention also provides a kind of design apparatus of standard cell lib, comprises common standard unit design module, it is characterized in that, also comprises dual-edge trigger unit design module, and described dual-edge trigger unit design module further comprises:
Add submodule, be used for described dual-edge trigger unit being added in the standard block kind at the unit kind time-like that settles the standard;
The principle diagram design submodule is used to design the schematic diagram of described dual-edge trigger unit;
The layout design submodule is used to design the domain of described dual-edge trigger unit;
The modeling submodule is used for the unit modeling of described dual-edge trigger, and described modeling submodule also comprises:
Comprehensive storehouse modeling unit is used to described dual-edge trigger to set up comprehensive storehouse of rising edge and the comprehensive storehouse of negative edge;
The simulated library modeling unit is used to described dual-edge trigger to set up the dual-edge trigger simulated library.
Described comprehensive storehouse modeling unit also comprises:
The first modeling subelement is used for the logic function of described dual-edge trigger unit is designated as the rising edge flip-flop element, and uses modeling tool that it is carried out modeling, obtains the comprehensive storehouse of described rising edge;
The second modeling subelement is designated as the negative edge flip-flop element with the logic function of described dual-edge trigger unit, and uses modeling tool that it is carried out modeling, obtains the comprehensive storehouse of described negative edge.
Described simulated library modeling subelement also comprises:
The 3rd modeling subelement is used for the logic function of described dual-edge trigger unit is designated as the rising edge flip-flop element, and uses modeling tool that it is carried out modeling, obtains described rising edge simulated library;
The 4th modeling subelement is used for the logic function of described dual-edge trigger unit is designated as the negative edge flip-flop element, and uses modeling tool that it is carried out modeling, obtains described negative edge simulated library;
Merge subelement, be used for the model file of described rising edge simulated library and described negative edge simulated library is merged, keep the non-functional description part, functional description partly is revised as the functional description of described dual-edge trigger unit, obtain described dual-edge trigger simulated library.
Again on the one hand, the embodiment of the invention also provides a kind of method for designing of integrated circuit, comprise that carrying out register transfer level RTL designs, carries out the step that circuit logic is comprehensive, carry out the laying out pattern wiring and layout data is carried out flow, the described comprehensive step of circuit logic of carrying out is specially:
Use the comprehensive storehouse of rising edge and the comprehensive storehouse of negative edge of dual-edge trigger unit that rtl circuit net table is carried out comprehensively, obtain the second gate level circuit net table;
Carry out and judge and the iteration synthetic operation, satisfied the second gate level circuit net table that comprehensive storehouse of described rising edge and the comprehensive storehouse of described negative edge sequential require simultaneously.
Carry out comprehensively rtl circuit net table in the comprehensive storehouse of rising edge of described use dual-edge trigger unit and the comprehensive storehouse of negative edge, and the method that obtains the second gate level circuit net table is specially:
Use the comprehensive storehouse of described rising edge that described rtl circuit net table is carried out comprehensively, obtain the first gate level circuit net table after, use the comprehensive storehouse of described negative edge that the described first gate level circuit net table is carried out comprehensively, obtain the described second gate level circuit net table; Or
Use the comprehensive storehouse of described negative edge that described rtl circuit net table is carried out comprehensively, obtain the first gate level circuit net table after, use the comprehensive storehouse of described rising edge that the described first gate level circuit net table is carried out comprehensively, obtain the described second gate level circuit net table.
The method of described execution judgement and iteration synthetic operation is specially:
Judge whether the described second gate level circuit net table satisfies the sequential requirement in comprehensive storehouse of described rising edge and the comprehensive storehouse of described negative edge simultaneously;
When the described second gate level circuit net table satisfies comprehensive storehouse of described rising edge and the requirement of the comprehensive storehouse of described negative edge sequential simultaneously, the described second gate level circuit net table is carried out described step of carrying out the laying out pattern wiring;
When the sequential that does not satisfy the comprehensive storehouse of described rising edge when the described second gate level circuit net table requires, use the comprehensive storehouse of described rising edge that the described second gate level circuit net table is carried out comprehensively again, return determining step after comprehensively;
When the sequential that does not satisfy the comprehensive storehouse of described negative edge when the described second gate level circuit net table requires, use the comprehensive storehouse of described negative edge that the described second gate level circuit net table is carried out comprehensively again, return determining step after comprehensively.
Another aspect, the embodiment of the invention also provide a kind of design apparatus of integrated circuit, comprise RTL design module, logic synthesis module, laying out pattern interconnect module and flow module, and described logic synthesis module comprises:
Comprehensive submodule is used to use the comprehensive storehouse of rising edge of dual-edge trigger unit and the comprehensive storehouse of negative edge that rtl circuit net table is carried out comprehensively, obtains the second gate level circuit net table;
Processing sub is used for carrying out and judges and the iteration synthetic operation, is satisfied the second gate level circuit net table that comprehensive storehouse of described rising edge and the comprehensive storehouse of described negative edge sequential require simultaneously.
Described comprehensive submodule further comprises:
First comprehensive unit is used to use the comprehensive storehouse of described rising edge that the circuit meshwork list that receives is carried out comprehensively;
Second comprehensive unit is used to use the comprehensive storehouse of described negative edge that the circuit meshwork list that receives is carried out comprehensively.
Described processing sub further comprises:
Judging unit is used to judge whether the described second gate level circuit net table satisfies the sequential requirement in comprehensive storehouse of described rising edge and the comprehensive storehouse of described negative edge simultaneously;
Transmitting element is used for when the described second gate level circuit net table satisfies comprehensive storehouse of described rising edge and the requirement of the comprehensive storehouse of described negative edge sequential simultaneously the described second gate level circuit net table being sent to described laying out pattern interconnect module;
First performance element, be used for when the described second gate level circuit net table does not satisfy the sequential requirement in the comprehensive storehouse of described rising edge, the described second gate level circuit net table is sent to described first comprehensive unit carry out again comprehensively, and comprehensive result is sent to described judging unit;
Second performance element, be used for when the described second gate level circuit net table does not satisfy the sequential requirement in the comprehensive storehouse of described negative edge, the described second gate level circuit net table is sent to described second comprehensive unit carry out again comprehensively, and comprehensive result is sent to described judging unit.
Compared with prior art, embodiments of the invention have the following advantages:
By in standard cell lib, adding based on rising edge clock and the equal dual-edge trigger unit that can trigger of negative edge, and the standard cell lib that will use this kind dual-edge trigger unit applies in the Design of Digital Integrated Circuit flow process, can make full use of the saltus step of clock signal, improved the utilization factor of clock signal, make the front and rear side of each saltus step can both be the logic function service of realization chip along (rising edge and negative edge), finish the required clock transition times minimizing of identity logic function thereby make, reduce the clock activity, reduced the dynamic power consumption of entire circuit system on clock trees.
Description of drawings
Fig. 1 is based on the digital integrated circuit design method schematic flow sheet of standard cell lib in the prior art;
Fig. 2 is a synchronous circuit structure synoptic diagram in the prior art;
Fig. 3 is a kind of clock distributing network synoptic diagram of tree structure in the synchronizing circuit in the prior art;
Fig. 4 is the method for designing schematic flow sheet of the standard cell lib of the embodiment of the invention;
Fig. 5 is the design apparatus synoptic diagram of the standard cell lib of the embodiment of the invention;
Fig. 6 is the method for designing schematic flow sheet of the integrated circuit of the embodiment of the invention;
Fig. 7 is the design apparatus synoptic diagram of the integrated circuit of the embodiment of the invention.
Embodiment
The dynamic power consumption that reduces in the circuit can be considered from two aspects: first aspect, and each node is blocked it to the circuit internal penetration, thereby is suppressed its corresponding dynamic power consumption the inoperative clock saltus step of sequential logic function activity in the control chip of should trying one's best; Second aspect, should improve the utilization factor of each time clock saltus step activity as far as possible, make each saltus step, even the front and rear side of each saltus step can both be for realizing the logic function service of chip along (rising edge and negative edge), finish the required clock transition times minimizing of identity logic function thereby make, reduce the clock activity to reach, reduce the purpose of circuit dynamic power consumption.
The embodiment of the invention promptly is to consider from above-described second aspect, in order to reduce the circuit dynamic power consumption, under the prerequisite that does not influence sequential logic unit correct logic functions and normal memory function, in standard cell lib, added based on rising edge clock and the equal dual-edge trigger unit that can trigger of negative edge, and proposition is based on the method for designing of the integrated circuit of this standard cell lib, the integrated circuit that makes design has reduced dynamic power consumption effectively.
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.
The method for designing of the standard cell lib of the embodiment of the invention as shown in Figure 4, concrete steps are as follows:
When the design standards cell library, at first need application purpose according to cell library, determine suitable standard block kind and corresponding driving ability.
In order to make full use of the upset of clock, effectively reduce the dynamic power consumption of circuit, the embodiment of the invention is added in sequential logic unit kind based on rising edge clock and the equal dual-edge trigger unit that can trigger of negative edge at determining unit kind time-like.
The principle diagram design of dual-edge trigger unit is identical with the principle diagram design method of other common standard unit.When design concept figure, must guarantee that the logic function of standard block is correct, also should satisfy sequential, the power consumption performance requirement of cell library integral body simultaneously.
The layout design of dual-edge trigger unit is identical with the layout design method of other common standard unit.When the design standards cell layout, satisfy the unified structure of a whole set of cell library, in the utilization factor that guarantees also should improve as far as possible under the correct prerequisite of domain function chip area except needs.
Use cell library modeling eda tool, set up a series of storehouses model files such as placement-and-routing storehouse, symbolic library, comprehensive storehouse, simulated library for each standard block in the standard cell lib.
Because existing cell library modeling eda tool can't be discerned the logic function of dual-edge trigger unit, therefore when the dual-edge trigger unit is carried out modeling, have only placement-and-routing storehouse, symbolic library etc. and the irrelevant storehouse model of standard block logic function, can directly use existing eda tool modeling flow process to carry out modeling.And, need carry out some special processings for storehouse models relevant such as the comprehensive storehouse of dual-edge trigger unit, simulated library with the standard block logic function, so that use existing eda tool that it is carried out modeling.Concrete steps are as follows:
(1) sets up two comprehensive storehouses for the dual-edge trigger unit: comprehensive storehouse of rising edge and the comprehensive storehouse of negative edge.
At first the logic function with the dual-edge trigger unit is designated as the rising edge flip-flop element, and uses eda tool that it is carried out modeling, obtains a comprehensive storehouse of rising edge;
Logic function with the dual-edge trigger unit is designated as the negative edge flip-flop element then, and uses eda tool that it is carried out modeling, obtains a comprehensive storehouse of negative edge.
(2) set up simulated library for the dual-edge trigger unit.
At first the logic function with the dual-edge trigger unit is designated as the rising edge flip-flop element, and uses eda tool that it is carried out modeling, obtains a rising edge simulated library;
Logic function with the dual-edge trigger unit is designated as the negative edge flip-flop element then, and uses eda tool that it is carried out modeling, obtains a negative edge simulated library;
Model file with the rising edge simulated library that obtains and negative edge simulated library merges at last, the part of non-functional description in the document retaining, and the functional description in the file partly made amendment, obtain final dual-edge trigger simulated library.
The model file of standard block generally comprises two parts in the simulated library: functional description part and non-functional description part.Functional description partly is used to describe the logic function of this standard block, and non-functional description partly comprises port definition, signal delay information etc.
Functional description in the sequential logical circuit generally adopts UDP (User Defined Primitives, User Defined elementary cell) mode (being truth table) to realize.
The UDP describing mode of rising edge simulated library and negative edge simulated library is different, and all available eda tool of non-functional descriptions such as port definition, signal delay information part generates automatically.
When carrying out rising edge simulated library and negative edge simulated library synthetic,, therefore need the UDP in two simulated library of deletion to describe part because the UDP in two simulated library that obtain describes the performance that part can not reflect dual-edge trigger; Part to non-functional description in two simulated library model files keeps, and is merged into a file.
Because merging in the new library file that obtains does not have UDP to describe part, promptly there is not sequential logic functional description part, therefore need add UDP again and describe part (UDP describe part must by manually adding), realize the logic function of dual-edge trigger with truth table, together with the non-functional description part that merges, obtain final dual-edge trigger simulated library at last.
The method that the application of the invention embodiment provides for standard cell lib provides based on rising edge of clock signal and the equal dual-edge trigger unit that can trigger of negative edge, uses this dual-edge trigger can make full use of the saltus step of clock.
The design apparatus of the standard cell lib of the embodiment of the invention comprises as shown in Figure 5:
Common standard unit design module 10 is used for the common standard unit of design standards cell library.
Dual-edge trigger unit design module 20 is used to design the dual-edge trigger unit.
Dual-edge trigger unit design module 20 further comprises:
Add submodule 21, be used for the dual-edge trigger unit being added in the standard block kind at the unit kind time-like that settles the standard.
Principle diagram design submodule 22 is used to design the schematic diagram of dual-edge trigger unit.
Comprehensive storehouse modeling unit 241 is used to the dual-edge trigger unit to set up comprehensive storehouse of rising edge and the comprehensive storehouse of negative edge;
Simulated library modeling unit 242 is used to the dual-edge trigger unit to set up the dual-edge trigger simulated library.
Comprehensive storehouse modeling unit 241 also comprises:
The first modeling subelement 2411 is used for the logic function of dual-edge trigger unit is designated as the rising edge flip-flop element, and uses modeling tool that it is carried out modeling, obtains the comprehensive storehouse of rising edge.
The second modeling subelement 2412 is designated as the negative edge flip-flop element with the logic function of dual-edge trigger unit, and uses modeling tool that it is carried out modeling, obtains the comprehensive storehouse of negative edge.
Simulated library modeling unit 242 also comprises:
The 3rd modeling subelement 2421 is used for the logic function of dual-edge trigger unit is designated as the rising edge flip-flop element, and uses modeling tool that it is carried out modeling, obtains the rising edge simulated library.
The 4th modeling subelement 2422 is used for the logic function of dual-edge trigger unit is designated as the negative edge flip-flop element, and uses modeling tool that it is carried out modeling, obtains the negative edge simulated library.
Merge subelement 2423, be used for the model file of rising edge simulated library and negative edge simulated library is merged, keep the non-functional description part, functional description partly is revised as the functional description of dual-edge trigger unit, obtain the dual-edge trigger simulated library.
The device that the application of the invention embodiment provides for standard cell lib provides based on rising edge of clock signal and the equal dual-edge trigger unit that can trigger of negative edge, uses this dual-edge trigger can make full use of the saltus step of clock.
After the standard cell lib modelling of finishing based on dual-edge trigger, can utilize this standard cell lib to carry out the design of integrated circuit, therefore the circuit of described design can reach the purpose that reduces the circuit dynamic power consumption owing to the standard cell lib that has adopted based on dual-edge trigger.
The method for designing of the integrated circuit of the embodiment of the invention as described in Figure 6, concrete steps are as follows:
With hardware description language (as verilog) descriptive system behavioral scaling model, obtain rtl circuit net table, and verify by emulation tool whether its function is correct.
As previously mentioned, it is comprehensive to need to carry out circuit logic after finishing RTL design, and the circuit logic of the embodiment of the invention comprehensively is step 62～step 63.
In the step 62, can at first use the comprehensive storehouse of rising edge that rtl circuit net table is carried out comprehensively, be met the first gate level circuit net table that the comprehensive storehouse of rising edge sequential requires, use the comprehensive storehouse of negative edge that the first gate level circuit net table is carried out comprehensively then, be met the second gate level circuit net table that the comprehensive storehouse of negative edge sequential requires;
Perhaps, at first use the comprehensive storehouse of negative edge that rtl circuit net table is carried out comprehensively, be met the first gate level circuit net table that the comprehensive storehouse of negative edge sequential requires, use the comprehensive storehouse of rising edge that the first gate level circuit net table is carried out comprehensively then, be met the second gate level circuit net table that the comprehensive storehouse of rising edge sequential requires.
Circuit logic comprehensively is the process that generates the gate level netlist file of describing side circuit from the RTL code, language description soon is converted into circuit diagram and describes, with the function of the standard block in the standard cell lib (comprehensive storehouse) realization with (RTL level) circuit of hardware description language description.The comprehensive purpose of circuit logic is: decision-making circuit gate leve structure, seek sequential and area balance, seek the balance of power consumption and sequential, the testability of intensifier circuit.
Circuit logic comprehensively generally includes following steps:
(1) defines the comprehensive storehouse that to call.
At first need definition to call the path, call the path and be meant the HDL of RTL level is described the comprehensive storehouse of standard block required when being mapped to gate leve.
The comprehensive storehouse that needs in the embodiment of the invention to call is comprehensive storehouse of rising edge and the comprehensive storehouse of negative edge.
(2) synthesizer reads in RTL, analyzes the grammar mistake of design and carries out the HDL code conversion.
(3) the comprehensive environmental constraints of definition.
Environmental constraints mainly comprises technological parameter (as manufacturing process, temperature, voltage etc.), I/O port attribute (as load, driving force, fan-in fan-out etc.) of design etc.
(4) definition design constraint.
Design constraint comprises design rule constraints and optimizes constraint.Design rule constraints is by providing in the technology library, must be provided with according to the parameter (as maximum capacitor and maximum fan-out) that technology library provides in actual design, optimizing the constraint of confinement time (as clock and input and output time-delay) and area.
(5) analyze and solve design problem.
Information such as the area that can produce by comprehensive back, power consumption, sequential are analyzed and are optimized synthesis result.
(6) gate level netlist of comprehensive generation is verified.
Usually can use instruments such as emulation, static timing analysis and formal verification that the gate level netlist of comprehensive generation is verified.
Judge that whether the second gate level circuit net table satisfies the sequential requirement of rising edge and negative edge simultaneously, if satisfy the sequential requirement in comprehensive storehouse of rising edge and the comprehensive storehouse of negative edge simultaneously, then enters step 64;
If the second gate level circuit net table does not satisfy the sequential requirement in the comprehensive storehouse of rising edge, then use the comprehensive storehouse of rising edge that the second gate level circuit net table is carried out comprehensively again, return determining step after comprehensive;
If the sequential requirement in the discontented comprehensive storehouse of sufficient negative edge of the second gate level circuit net table then uses the comprehensive storehouse of negative edge that the second gate level circuit net table is carried out comprehensively again, return determining step after comprehensively;
Satisfied the second gate level circuit net table that comprehensive storehouse of rising edge and the comprehensive storehouse of negative edge sequential require until simultaneously.
Utilize the placement-and-routing storehouse of placement-and-routing's facility invokes standard cell lib, the second gate level circuit net table that comprehensively obtains is carried out automatic placement and routing, obtain the layout data of circuit.
After obtaining domain, need also to carry out verifying behind the domain whether the checking layout design can realize all functions and performance index.
On specific chip technology line, produce chip according to layout data, and the chip of making is tested, detect the defective and the problem that produce in producing.
The method that the application of the invention embodiment provides, to use the standard cell lib of dual-edge trigger unit to apply in the Design of Digital Integrated Circuit flow process, the digital circuit that obtains can make full use of the saltus step of clock signal, guaranteeing to have reduced the dynamic power consumption of entire circuit system on clock trees under the correct prerequisite of logic function.
The design apparatus of the integrated circuit of the embodiment of the invention comprises as shown in Figure 7:
Laying out pattern interconnect module 50 is used for the second gate level circuit net table that satisfies the requirement of comprehensive storehouse of rising edge and the comprehensive storehouse of negative edge sequential is carried out the laying out pattern wiring, obtains the layout data of circuit.
Processing sub 42 is used for the second gate level circuit net table that receives carried out and judges and iteration synthetic operation repeatedly, is satisfied the second gate level circuit net table that comprehensive storehouse of rising edge and the comprehensive storehouse of negative edge sequential require simultaneously.
First comprehensive unit 411 is used to use the comprehensive storehouse of rising edge that the circuit meshwork list that receives is carried out comprehensively.
Second comprehensive unit 412 is used to use the comprehensive storehouse of negative edge that the circuit meshwork list that receives is carried out comprehensively.
When receiving the rtl circuit net table of RTL design module 30 transmissions, can at first use 411 pairs of rtl circuit nets of first comprehensive unit table to carry out comprehensively, be met the first gate level circuit net table that the comprehensive storehouse of rising edge sequential requires, use 412 pairs first gate level circuit nets of second comprehensive unit table to carry out comprehensively then, be met the second gate level circuit net table that the comprehensive storehouse of negative edge sequential requires;
Perhaps, at first use 412 pairs of rtl circuit nets of second comprehensive unit table to carry out comprehensively, be met the first gate level circuit net table that the comprehensive storehouse of negative edge sequential requires, use 411 pairs first gate level circuit nets of first comprehensive unit table to carry out comprehensively then, be met the second gate level circuit net table that the comprehensive storehouse of rising edge sequential requires.
Processing sub 42 further comprises:
Judging unit 421 is used to judge whether the second gate level circuit net table satisfies the sequential requirement in comprehensive storehouse of rising edge and the comprehensive storehouse of negative edge simultaneously.
Transmitting element 422 is used for when the second gate level circuit net table satisfies comprehensive storehouse of rising edge and the requirement of the comprehensive storehouse of negative edge sequential simultaneously the second gate level circuit net table being sent to laying out pattern interconnect module 50.
The device that the application of the invention embodiment provides, to use the standard cell lib of dual-edge trigger unit to apply in the Design of Digital Integrated Circuit flow process, the digital circuit that obtains can make full use of the saltus step of clock signal, guaranteeing to have reduced the dynamic power consumption of entire circuit system on clock trees under the correct prerequisite of logic function.
By the description of above embodiment, those skilled in the art can be well understood to the present invention and can realize by the mode that software adds essential general hardware platform, can certainly pass through hardware, but the former is better embodiment under a lot of situation.Based on such understanding, the part that technical scheme of the present invention contributes to prior art in essence in other words can embody with the form of software product, this obtains the machine software product and is stored in the storage medium, comprises that some instructions are used so that a station terminal equipment is carried out the described method of each embodiment of the present invention.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (4)
1. the method for designing of a standard cell lib comprises the step that designs the common standard unit, it is characterized in that, also comprises the step of design dual-edge trigger unit, and the step of described design dual-edge trigger unit comprises:
The unit kind time-like that settles the standard adds described dual-edge trigger unit in the standard block kind to;
Design the schematic diagram of described dual-edge trigger unit;
Design the domain of described dual-edge trigger unit;
To the unit modeling of described dual-edge trigger, the method for described modeling is: for setting up comprehensive storehouse of rising edge and the comprehensive storehouse of negative edge in described dual-edge trigger unit; For setting up the dual-edge trigger simulated library in described dual-edge trigger unit;
The described method of setting up comprehensive storehouse of rising edge and the comprehensive storehouse of negative edge for described dual-edge trigger unit is specially: the logic function of described dual-edge trigger unit is designated as the rising edge flip-flop element, and use modeling tool that it is carried out modeling, obtain the comprehensive storehouse of described rising edge; The logic function of described dual-edge trigger unit is designated as the negative edge flip-flop element, and uses modeling tool that it is carried out modeling, obtain the comprehensive storehouse of described negative edge;
The described method of setting up the dual-edge trigger simulated library for described dual-edge trigger unit is specially: the logic function of described dual-edge trigger unit is designated as the rising edge flip-flop element, and use modeling tool that it is carried out modeling, obtain the rising edge simulated library; The logic function of described dual-edge trigger unit is designated as the negative edge flip-flop element, and uses modeling tool that it is carried out modeling, obtain the negative edge simulated library; The model file of described rising edge simulated library and described negative edge simulated library is merged, keep the non-functional description part, functional description partly is revised as the functional description of described dual-edge trigger unit, obtain described dual-edge trigger simulated library.
2. the design apparatus of a standard cell lib comprises common standard unit design module, it is characterized in that, also comprises dual-edge trigger unit design module, and described dual-edge trigger unit design module further comprises:
Add submodule, be used for described dual-edge trigger unit being added in the standard block kind at the unit kind time-like that settles the standard;
The principle diagram design submodule is used to design the schematic diagram of described dual-edge trigger unit;
The layout design submodule is used to design the domain of described dual-edge trigger unit;
The modeling submodule is used for the unit modeling of described dual-edge trigger, and described modeling submodule also comprises: comprehensive storehouse modeling unit is used to described dual-edge trigger unit to set up comprehensive storehouse of rising edge and the comprehensive storehouse of negative edge; The simulated library modeling unit is used to described dual-edge trigger unit to set up the dual-edge trigger simulated library;
Described comprehensive storehouse modeling unit also comprises: the first modeling subelement, and be used for the logic function of described dual-edge trigger unit is designated as the rising edge flip-flop element, and use modeling tool that it is carried out modeling, obtain the comprehensive storehouse of described rising edge; The second modeling subelement is used for the logic function of described dual-edge trigger unit is designated as the negative edge flip-flop element, and uses modeling tool that it is carried out modeling, obtains the comprehensive storehouse of described negative edge;
Described simulated library modeling subelement also comprises: the 3rd modeling subelement, and be used for the logic function of described dual-edge trigger unit is designated as the rising edge flip-flop element, and use modeling tool that it is carried out modeling, obtain described rising edge simulated library; The 4th modeling subelement is used for the logic function of described dual-edge trigger unit is designated as the negative edge flip-flop element, and uses modeling tool that it is carried out modeling, obtains described negative edge simulated library; Merge subelement, be used for the model file of described rising edge simulated library and described negative edge simulated library is merged, keep the non-functional description part, functional description partly is revised as the functional description of described dual-edge trigger unit, obtain described dual-edge trigger simulated library.
3. the method for designing of an integrated circuit, comprise that carrying out register transfer level RTL designs, carries out the step that circuit logic is comprehensive, carry out the laying out pattern wiring and layout data is carried out flow, it is characterized in that the described comprehensive step of circuit logic of carrying out is specially:
Use the comprehensive storehouse of rising edge and the comprehensive storehouse of negative edge of dual-edge trigger unit that rtl circuit net table is carried out comprehensively, obtain the second gate level circuit net table;
Carry out and judge and the iteration synthetic operation, satisfied the second gate level circuit net table that comprehensive storehouse of described rising edge and the comprehensive storehouse of described negative edge sequential require simultaneously;
Carry out comprehensively rtl circuit net table in the comprehensive storehouse of rising edge of described use dual-edge trigger unit and the comprehensive storehouse of negative edge, the method that obtains the second gate level circuit net table is specially: use the comprehensive storehouse of described rising edge that described rtl circuit net table is carried out comprehensively, after obtaining the first gate level circuit net table, use the comprehensive storehouse of described negative edge that the described first gate level circuit net table is carried out comprehensively, obtain the described second gate level circuit net table; Or use the comprehensive storehouse of described negative edge that described rtl circuit net table is carried out comprehensively, obtain the first gate level circuit net table after, use the comprehensive storehouse of described rising edge that the described first gate level circuit net table is carried out comprehensively, obtain the described second gate level circuit net table;
The method of described execution judgement and iteration synthetic operation is specially: judge whether the described second gate level circuit net table satisfies the sequential requirement in comprehensive storehouse of described rising edge and the comprehensive storehouse of described negative edge simultaneously; When the described second gate level circuit net table satisfies comprehensive storehouse of described rising edge and the requirement of the comprehensive storehouse of described negative edge sequential simultaneously, the described second gate level circuit net table is carried out described step of carrying out the laying out pattern wiring; When the sequential that does not satisfy the comprehensive storehouse of described rising edge when the described second gate level circuit net table requires, use the comprehensive storehouse of described rising edge that the described second gate level circuit net table is carried out comprehensively again, return determining step after comprehensively; When the sequential that does not satisfy the comprehensive storehouse of described negative edge when the described second gate level circuit net table requires, use the comprehensive storehouse of described negative edge that the described second gate level circuit net table is carried out comprehensively again, return determining step after comprehensively.
4. the design apparatus of an integrated circuit is characterized in that, comprises register transfer level RTL design module, logic synthesis module, laying out pattern interconnect module and flow module, it is characterized in that described logic synthesis module comprises:
Comprehensive submodule is used to use the comprehensive storehouse of rising edge of dual-edge trigger unit and the comprehensive storehouse of negative edge that rtl circuit net table is carried out comprehensively, obtains the second gate level circuit net table;
Processing sub is used for carrying out and judges and the iteration synthetic operation, is satisfied the second gate level circuit net table that comprehensive storehouse of described rising edge and the comprehensive storehouse of described negative edge sequential require simultaneously;
Described comprehensive submodule further comprises: first comprehensive unit is used to use the comprehensive storehouse of described rising edge that the circuit meshwork list that receives is carried out comprehensively; Second comprehensive unit is used to use the comprehensive storehouse of described negative edge that the circuit meshwork list that receives is carried out comprehensively;
Described processing sub further comprises: judging unit is used to judge whether the described second gate level circuit net table satisfies the sequential requirement in comprehensive storehouse of described rising edge and the comprehensive storehouse of described negative edge simultaneously; Transmitting element is used for when the described second gate level circuit net table satisfies comprehensive storehouse of described rising edge and the requirement of the comprehensive storehouse of described negative edge sequential simultaneously the described second gate level circuit net table being sent to described laying out pattern interconnect module; First performance element, be used for when the described second gate level circuit net table does not satisfy the sequential requirement in the comprehensive storehouse of described rising edge, the described second gate level circuit net table is sent to described first comprehensive unit carry out again comprehensively, and comprehensive result is sent to described judging unit; Second performance element, be used for when the described second gate level circuit net table does not satisfy the sequential requirement in the comprehensive storehouse of described negative edge, the described second gate level circuit net table is sent to described second comprehensive unit carry out again comprehensively, and comprehensive result is sent to described judging unit.
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| CN102831273B (en) * | 2012-08-30 | 2015-02-04 | 锐迪科科技有限公司 | Design method of digital integrated circuit comprising double-edge trigger |
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| CN105138769B (en) * | 2015-08-24 | 2018-11-23 | 深圳市紫光同创电子有限公司 | A kind of temporal model generation method and device for programmable circuit |
| CN106529043A (en) * | 2016-11-14 | 2017-03-22 | 无锡华润矽科微电子有限公司 | Method for carrying out sub-module comprehensive design on circuit on basis of computer software |
| CN108153961A (en) * | 2017-12-21 | 2018-06-12 | 盛科网络（苏州）有限公司 | A kind of register generation method device for chip checking |
| CN109657383B (en) * | 2018-12-26 | 2020-07-28 | 北京华大九天软件有限公司 | Spice simulation method of time sequence path |
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| WO2022021091A1 (en) * | 2020-07-28 | 2022-02-03 | 华为技术有限公司 | Clock tree architecture, and clock signal transmission method and device |
| CN112232006B (en) * | 2020-10-26 | 2021-07-02 | 海光信息技术股份有限公司 | Standard cell library verification method and device, electronic equipment and storage medium |
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