CN102831273B - Design method of digital integrated circuit comprising double-edge trigger - Google Patents
Design method of digital integrated circuit comprising double-edge trigger Download PDFInfo
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- CN102831273B CN102831273B CN201210315870.9A CN201210315870A CN102831273B CN 102831273 B CN102831273 B CN 102831273B CN 201210315870 A CN201210315870 A CN 201210315870A CN 102831273 B CN102831273 B CN 102831273B
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Abstract
The invention discloses a design method of a digital integrated circuit comprising a double-edge trigger, wherein the method updates steps such as design input, logic synthesis, gate-level and RTL (Resistor Transistor Logic) level formal verification, logic optimization, formal verification of the gate level after/before optimization, distributing, wiring, and the like, so that the double-edge trigger is really integrated to the design method of the digital integrated circuit. The method has an important significance for improving processing speed of the digital integrated circuit or reducing power consumption of the digital integrated circuit.
Description
Technical field
The application relates to a kind of digital integrated circuit design method,
Background technology
Fig. 1 is a rising edge d type flip flop, and its output signal Q only follows the tracks of input signal D at the rising edge of clock signal clk.
Fig. 2 is a negative edge d type flip flop, and it is just by the clock input inversion of rising edge d type flip flop, only follows the tracks of input signal D at the negative edge of clock signal clk to make output signal Q.
Fig. 3 is a Double-edge D trigger, comprises a rising edge d type flip flop 10, negative edge d type flip flop 20 and two path multiplexers 30.At the rising edge of clock signal clk, two path multiplexers 30 are using the output signal Q3 of the output signal Q1 of rising edge d type flip flop 10 as Double-edge D trigger.At the negative edge of clock signal clk, two path multiplexers 30 are using the output signal Q3 of the output signal Q2 of negative edge d type flip flop 20 as Double-edge D trigger.Therefore, the output signal Q3 of Double-edge D trigger is both at the rising edge of clock signal clk, also follow the tracks of input signal D at the negative edge of clock signal clk.
The above-mentioned dual-edge trigger for d type flip flop has been broken can only at a clock along the limitation of carrying out data processing in the clock period, and the rising edge within a clock period and negative edge all can carry out data processing.After adopting this dual-edge trigger, when input signal still maintains original frequency, the frequency of clock signal can be reduced to original half, and still can process data volume identical with single edge flip-flops under original clock signal frequency.Obviously, reduce half clock frequency and can reach the object significantly reducing power consumption, reduce heating.If still maintain original clock signal frequency, then the data processing amount of dual-edge trigger in same time section can reach original twice, thus significantly promotes processing speed.
Current, digital integrated circuit adopts method for designing top down usually.Refer to Fig. 4, this is a kind of typical digital integrated circuit design method, comprises the steps:
1st step, design input (design entry), namely describe behavior and/or the structure of circuit with text and/or graphics mode, form the circuit description document of RTL.Text mode such as adopts the hardware description languages (HDL, hardware description language) such as Veri log, VHDL.Graphics mode such as adopts schematic diagram, constitutional diagram etc.Circuit behavior refers to relation between the constrained input of circuit and sequential relationship thereof.Circuit structure refers to each functional block, module, unit, door and the annexation between them in circuit.
2nd step, RTL(Method at Register Transfer Level, register transfer level) level functional simulation, whether namely emulate rtl circuit description document, it is consistent with designing requirement to test its function.RTL functional simulation, also known as front emulation (pre-layout simulation), does not have time sequence information usually, or simply define time delay be the unit time, as 1ns.
3rd step, logic synthesis (logic synthesis), the circuit description document by RTL is converted to gate level netlist (netlist) file be made up of concrete logical block.Gate level netlist file can be EDIF file, VHDL file, Verilog file etc.Transfer process depends on constraint condition and cell library file.
Described constraint condition, comprises area-constrained, temporal constraint etc.Described temporal constraint comprises the frequency of requirement work clock, dutycycle, offset characteristic, the input time delay of input signal, the output time delay of output signal, the switching time etc. of each signal.
Described cell library file also claims technology library file, comprises the time sequence information (delayed data, driving force etc.) of some necessity of various combinatorial logic unit (Sheffer stroke gate, multiplexer, totalizer etc.) and sequential logic unit (trigger, latch etc.) and these unit.
According to circuit structure, 4th step, gate leve and RTL formal verification, namely judge whether gate level netlist file and rtl circuit description document be functionally consistent statically.Existing digital integrated circuit only adopts single edge flip-flops, and thus this step can be omitted.
5th step, comprehensive after gate leve functional simulation, whether namely emulate the gate level netlist file formed after logic synthesis, it is consistent with designing requirement to test its function.Now can select to add time sequence information in gate level netlist, to judge that whether its sequential is consistent with designing requirement.
6th step, logic optimization (logic optimization), namely according to Boolean equation equivalence principle, some unoptimizable boolean in gate level netlist file logic synthesis generated describe the boolean being converted to optimization and describe, to reduce scale, the simplification circuit structure of the logical block that circuit takies.Gate level netlist file after logic optimization also will carry out functional simulation.
Gate leve formal verification before and after 7th step, optimization, namely functionally whether consistent with the gate level netlist file before logic optimization according to the gate level netlist file after circuit structure decision logic optimization statically.
8th step, optimize after gate leve functional simulation, whether namely emulate the gate level netlist file formed after logic optimization, it is consistent with designing requirement to test its function.Now can select to add time sequence information in gate level netlist, to judge that whether its sequential is consistent with designing requirement.
9th step, placement-and-routing, namely carry out layout design according to gate level netlist file.This process generally includes:
(1) pre-layout (floor planning), namely determines the shape of chip, size etc.
(2) layout (placement), the block (blocks) that namely arrangement net is shown on chip, determines the position of unit in block (cells).
(3) clock tree synthesis (clock tree synthesis, CTS), this is, according to the physical layout of chip, clock signal is passed to each register clock pin in chip by clock source.Clock Tree is a kind of tree structure being used for analytical line time delay.Such as, using clock source as tree root, each lock unit is as leaf, and middle branch is exactly actual line.Ideally, each lock unit should receive clock signal simultaneously.Improvement can be optimized to the delay deviation of receive clock signal by each paths length analyzing Clock Tree.
(4) connect up (routing), namely in block and unit or between them, determine line.
10th step, domain level functional simulation, also post-simulation (post-layout simulation) is claimed, namely emulate to the net meter file after placement-and-routing or to the net meter file having extracted RC parameter (resistance capacitance parameter) after placement-and-routing, whether consistent with designing requirement with sequential to test its function.
11st step, layout verification, comprise DRC (DRC), the net table of domain export (NE), electricity rule checks (ERC), parasitic parameter extraction (PE), circuit diagram domain contrast (LVS) etc.
12nd step, generation domain GDSII data.
Due to EDA(electronic design automation) instrument universal, in each step of above-mentioned design cycle, there is eda tool to help to realize.In all the other steps except the 1st step, be rely on eda tool automatically to realize, errors excepted again by manual amendment substantially.
Existing digital integrated circuit design method is all based on single edge flip-flops.Also have no idea at present to carry out comprising the Design of Digital Integrated Circuit of dual-edge trigger, this is because the eda tools such as the logic synthesis tool in the 3rd step do not support dual-edge trigger, thus the circuit description document of RTL automatically cannot be converted to gate level netlist file.These work as all transferred to artificial treatment, are then unthinkable.
Summary of the invention
Technical problems to be solved in this application make the support of existing digital integrated circuit design method increase to dual-edge trigger.
For solving the problems of the technologies described above, the digital integrated circuit design method that the application comprises dual-edge trigger comprises the step of gate leve formal verification before and after design input, logic synthesis, gate leve and RTL formal verification, logic optimization, optimization, placement-and-routing; Wherein:
When designing input, in rtl circuit description document, only adopt single edge flip-flops;
After logic synthesis, partly or entirely into dual-edge trigger is changed to the single edge flip-flops in the comprehensive rear first gate level netlist file generated, generates the second gate level netlist file comprehensively; In gate leve cell library file, increase the door of dual-edge trigger simultaneously, in gate leve cell library description document, increase the description of dual-edge trigger;
When gate leve and RTL formal verification, formal verification is carried out to comprehensive rear first gate level netlist file and rtl circuit description document;
When logic optimization, logic optimization is carried out to comprehensive rear second gate level netlist file;
Before optimization before gate leve formal verification, first the description of the dual-edge trigger in gate leve cell library description document is changed into consistent with single edge flip-flops, again formal verification is carried out to gate leve net meter file after optimization and comprehensive rear second gate level netlist file, then the description of the dual-edge trigger in gate leve cell library description document is recovered former state;
Before placement-and-routing, in domain level cell library file, first increase territory unit structure and the ROW(row of dual-edge trigger) describe, then carry out placement-and-routing; When placement-and-routing, the Clock Tree generated includes the delay of wire delay within the territory unit structure of dual-edge trigger and two path multiplexers.
Method described in the application achieves the whole process of the Design of Digital Integrated Circuit comprising dual-edge trigger, and dual-edge trigger is really dissolved among the design of digital integrated circuit.This, for promoting the processing speed of digital integrated circuit or reducing the power consumption aspect of digital integrated circuit, is all significant.
Accompanying drawing explanation
Fig. 1 is the logical symbol of rising edge d type flip flop.
Fig. 2 is the logical symbol of negative edge d type flip flop.
Fig. 3 is the circuit diagram of Double-edge D trigger.
Fig. 4 is the process flow diagram of existing digital integrated circuit design method.
Fig. 5 is the process flow diagram of the digital integrated circuit design method of the application.
Description of reference numerals in figure:
10 is rising edge d type flip flop; 20 is negative edge d type flip flop; 30 is two path multiplexers.
Embodiment
The application comprises the digital integrated circuit design method of dual-edge trigger, also has gate leve formal verification before and after design input as shown in Figure 4, RTL functional simulation, logic synthesis, gate leve and RTL formal verification, comprehensively rear gate leve functional simulation, logic optimization, optimization, optimizes rear gate leve functional simulation, placement-and-routing, domain level functional simulation, layout verification, these 12 steps of generation domain GDSII data.Wherein revise part steps, concrete modification content is as follows:
One, when the 1st step design input, all triggers in rtl circuit description document all adopt traditional single edge flip-flops.
Its two, the gate level netlist file generated after the 3rd step logic synthesis be called comprehensive after the first gate level netlist file, trigger is wherein all single edge flip-flops.Then partly or entirely change the single edge flip-flops in comprehensive rear first gate level netlist file into dual-edge trigger according to designing requirement, be called comprehensive rear second gate level netlist file.This change can be realized by script file.
The advantage of single edge flip-flops is that chip area is little, the advantage of dual-edge trigger be when keeping the clock frequency the same with single edge flip-flops processing speed can double, when the processing speed that maintenance is the same with single edge flip-flops, clock frequency can reduce by half.Thus, common designing requirement only in the nucleus module needing high speed processing, adopts dual-edge trigger, in all the other modules, still adopt single edge flip-flops; The same clock frequency is adopted, to make the processing speed of nucleus module double to all triggers.
After formation is comprehensive while second gate level netlist file, in gate leve cell library file (.lib file), increase the door of dual-edge trigger; Also increase the description of dual-edge trigger in the gate leve cell library description document (.v or .vhd file), namely dual-edge trigger all works at the rising edge of clock signal and negative edge.Although gate level netlist file is identical with gate leve cell library description document suffix name, but the former is used for describing circuit connecting relation, input/output relation, the sequential relationship between each logical block (combinatorial logic unit, sequential logic unit), and the latter is used for describing the response process etc. of each logical block to clock signal.
Its three, when the 4th step gate leve and RTL formal verification, formal verification is carried out to the first gate level netlist file after comprehensive and rtl circuit description document.
Its four, after the 5th step is comprehensive during gate leve functional simulation, carry out functional simulation to the first gate level netlist file after comprehensive, this step can be omitted.
Its five, when the 6th step logic optimization, logic optimization is carried out to the second gate level netlist file after comprehensive.
They are six years old, before and after the 7th step is optimized before gate leve formal verification, first change into consistent with single edge flip-flops by the description of the dual-edge trigger in gate leve cell library description document (.v or .vhd file), namely dual-edge trigger is only in rising edge or the negative edge work of clock signal.Then formal verification is carried out to gate leve net meter file after optimization and comprehensive rear second gate level netlist file.Last again the description of the dual-edge trigger in gate leve cell library description document is recovered former state, namely dual-edge trigger all works at the rising edge of clock signal and negative edge.
Its seven, before the 9th step placement-and-routing, in domain level cell library file (techfile), first increase territory unit structure and the ROW(row of dual-edge trigger) describe, namely record its height.Carry out placement-and-routing more afterwards.When placement-and-routing, the Clock Tree generated includes the deferred message of wire delay within the territory unit structure of dual-edge trigger, two path multiplexers.
By carrying out above-mentioned change to existing digital integrated circuit design method, the method is made to be able to compatible dual-edge trigger.
Refer to Fig. 5, this is the specific embodiment that the application comprises the digital integrated circuit design method of dual-edge trigger, comprises the steps: (part identical with the content in background technology in each step repeats no more)
1st step, design input, to form rtl circuit description document, now do not adopt dual-edge trigger.Run into the situation needing to use trigger, all adopt single edge flip-flops.Common design input tool software has Verilog, VHDL etc., and the suffix name of the rtl circuit description document that they are formed is respectively .v .vhd.
In fact, these two kinds of hardware description languages of Verilog and VDHL can be used for describing dual-edge trigger, but do not support dual-edge trigger due to follow-up logic synthesis tool, thus there is no need when designing input to adopt dual-edge trigger.
2nd step, functional simulation is carried out to rtl circuit description document.Common functional simulation instrument has VCS(verilog compiled simulator), NCVerilog etc., they all support that all functions of the 2nd step, the 5th step, the 8th step, the 10th step emulate.
In fact, dual-edge trigger supported by functional simulation instrument.But owing to not comprising dual-edge trigger in rtl circuit description document before, in the functional simulation of thus this step, also functional test is not carried out to dual-edge trigger.
3rd step, logic synthesis is carried out to rtl circuit description document, form gate level netlist file.
Common logic synthesis tool is DC(design compiler), it does not support dual-edge trigger.If comprise dual-edge trigger in rtl circuit description document, then DC cannot be converted into gate level netlist file.Therefore, the trigger in the rtl circuit description document that the application is formed is all single edge flip-flops, facilitates the use DC and carries out logic synthesis.There is no dual-edge trigger in the gate level netlist file formed after comprehensive, be called comprehensive rear first gate level netlist file yet.
Then partly or entirely change the single edge flip-flops in comprehensive rear first gate level netlist file into dual-edge trigger according to designing requirement, be called comprehensive rear second gate level netlist file.After formation is comprehensive while second gate level netlist file, in gate leve cell library file (.lib file), increase the door of dual-edge trigger; In gate leve cell library description document (.v or .vhd file), also increase the description of dual-edge trigger.
The input of logic synthesis tool has three classes, and the first kind is rtl circuit description document (.v or .vhd file), and Equations of The Second Kind is gate leve cell library file (.lib file), and the 3rd class is unbound document (such as time constraints file is .sdc file); The suffix name of the gate level netlist file that Verilog, VHDL of exporting are formed still is respectively .v .vhd, consistent with the suffix name of rtl circuit description document.
If the processing speed in order to promote dual-edge trigger place module, so the clock frequency of dual-edge trigger will be consistent with single edge flip-flops.In time constraints file (.sdc file) used by logic synthesis, can the clock frequency of dual-edge trigger be set to consistent with single edge flip-flops.
If in order to reduce dual-edge trigger place module power consumption, heat radiation, and maintain and the same processing speed during employing single edge flip-flops, so the clock frequency of dual-edge trigger will become the half of single edge flip-flops.Now can modify to time constraints file (.sdc file), the clock frequency of dual-edge trigger is set to the half of the clock frequency of single edge flip-flops.
4th step, formal verification is carried out to the first gate level netlist file after comprehensive and rtl circuit description document.Common formal verification tool has conformal, formality etc., and they all support that the form of ownership of the 4th step, the 7th step is verified.
5th step, carry out functional simulation to the first gate level netlist file after comprehensive, this step can be omitted.
6th step, carry out logic optimization to the second gate level netlist file after comprehensive, logic optimization instrument is exactly logic synthesis tool DC, and after optimizing, the suffix name of gate leve net meter file is still .v or .vhd file, wherein comprises dual-edge trigger.
Although DC does not support the rtl circuit description document comprising dual-edge trigger to be converted to gate level netlist file, support to carry out logic optimization to the gate level netlist file comprising dual-edge trigger.
7th step, first change into consistent with single edge flip-flops by the description of the dual-edge trigger in gate leve cell library description document (.v or .vhd file), namely dual-edge trigger is only in rising edge or the negative edge work of clock signal.Then formal verification is carried out to gate leve net meter file after optimization and comprehensive rear second gate level netlist file.Last again the description of the dual-edge trigger in gate leve cell library description document is recovered former state, namely dual-edge trigger all works at the rising edge of clock signal and negative edge.
8th step, to optimization after gate leve net meter file carry out functional simulation.
9th step, according to optimization after gate leve net meter file carry out placement-and-routing.Common placement-and-routing's instrument has SoC Encounter, IC Compiler etc.Owing to there is no the territory unit structure of dual-edge trigger in existing domain level cell library file (techfile), after also needing to increase the territory unit structure of dual-edge trigger wherein, carry out placement-and-routing again.Comparison diagram 1 ~ Fig. 3 is known, the area of dual-edge trigger, be highly all roughly the twice of single edge flip-flops, thus the ROW(row increasing dual-edge trigger in domain level cell library file is also needed) describe, namely record its height, carry out placement-and-routing more afterwards.
Can generated clock tree in placement-and-routing's process.When only adopting single edge flip-flops, Clock Tree only needs to consider the deferred messages such as the wire delay outside the territory unit structure of single edge flip-flops.After have employed dual-edge trigger, Clock Tree also need consider dual-edge trigger territory unit structure within wire delay, two path multiplexers deferred message.This is due to as shown in Figure 3, and dual-edge trigger can be considered the combination of two single edge flip-flops and two path multiplexers.
Placement-and-routing's instrument reads gate level netlist file (.v or .vhd file), gate leve cell library file (.lib file), various unbound document (time constraints file .sdc file, power constraints file etc.), domain level cell library file (.lef) after optimizing, then carries out layout design.
10th step, carry out domain level functional simulation according to the net meter file after placement-and-routing or to the net meter file having extracted RC parameter (resistance capacitance parameter) after placement-and-routing.
11st step, layout verification (physical verification) is carried out to the net meter file after placement-and-routing.Layout verification tool can adopt placement-and-routing's instrument, also can adopt third party's instrument, the Calibre groupware of such as Mentor company or the Hercules groupware of Synopsys company.
12nd step, generation domain GDSII data, still adopt placement-and-routing's instrument.
The application's digital integrated circuit design method achieves the complete compatibility to dual-edge trigger, is conducive to promoting the processing speed of digital integrated circuit or reducing power consumption and the heat radiation of digital integrated circuit.
These are only the preferred embodiment of the application, and be not used in restriction the application.For a person skilled in the art, the application can have various modifications and variations.Within all spirit in the application and principle, any amendment done, equivalent replacement, improvement etc., within the protection domain that all should be included in the application.
Claims (4)
1. comprise a digital integrated circuit design method for dual-edge trigger, comprise the step of gate leve formal verification before and after design input, logic synthesis, gate leve and RTL formal verification, logic optimization, optimization, placement-and-routing; It is characterized in that:
When designing input, in rtl circuit description document, only adopt single edge flip-flops;
After logic synthesis, partly or entirely into dual-edge trigger is changed to the single edge flip-flops in the comprehensive rear first gate level netlist file generated, generates the second gate level netlist file comprehensively; In gate leve cell library file, increase the door of dual-edge trigger simultaneously, in gate leve cell library description document, increase the description of dual-edge trigger;
When gate leve and RTL formal verification, formal verification is carried out to comprehensive rear first gate level netlist file and rtl circuit description document;
When logic optimization, logic optimization is carried out to comprehensive rear second gate level netlist file;
Before optimization before gate leve formal verification, first the description of the dual-edge trigger in gate leve cell library description document is changed into consistent with single edge flip-flops, again formal verification is carried out to gate leve net meter file after optimization and comprehensive rear second gate level netlist file, then the description of the dual-edge trigger in gate leve cell library description document is recovered former state;
Before placement-and-routing, in domain level cell library file, first increase territory unit structure and the ROW(row of dual-edge trigger) describe, then carry out placement-and-routing; When placement-and-routing, the Clock Tree generated includes the delay of wire delay within the territory unit structure of dual-edge trigger and two path multiplexers.
2. the digital integrated circuit design method comprising dual-edge trigger according to claim 1, also comprise between the step of gate leve and RTL formal verification, logic optimization comprehensive after the step of gate leve functional simulation, it is characterized in that, when comprehensive rear gate leve functional simulation, functional simulation is carried out to comprehensive rear first gate level netlist file.
3. the digital integrated circuit design method comprising dual-edge trigger according to claim 1, it is characterized in that, before logic synthesis, in time constraints file, the clock frequency of dual-edge trigger is set to consistent with single edge flip-flops, to obtain the double processing speed of dual-edge trigger place module.
4. the digital integrated circuit design method comprising dual-edge trigger according to claim 1, it is characterized in that, before logic synthesis, the clock frequency of dual-edge trigger is set to the half of the clock frequency of single edge flip-flops in time constraints file, with reduce dual-edge trigger place module power consumption and heat radiation.
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| CN105574219B (en) * | 2014-10-10 | 2018-08-21 | 上海华虹宏力半导体制造有限公司 | The method of non-standard cell library logic unit automatic placement and routing |
| CN106529043A (en) * | 2016-11-14 | 2017-03-22 | 无锡华润矽科微电子有限公司 | Method for carrying out sub-module comprehensive design on circuit on basis of computer software |
| CN107122565B (en) * | 2017-05-12 | 2019-08-30 | 山东大学 | FPGA BRAM framework and design method based on nonvolatile memory |
| CN108829903B (en) * | 2017-11-09 | 2021-11-05 | 北京广利核系统工程有限公司 | Method and system for judging consistency of codes of FPGA redundant design and integrated circuit |
| CN108052838B (en) * | 2017-11-23 | 2021-12-07 | 北京智芯微电子科技有限公司 | Leakage positioning system and method for chip encryption design |
| CN110032792B (en) * | 2019-04-09 | 2022-11-11 | 中国科学院上海微系统与信息技术研究所 | Superconducting digital circuit design method |
| CN110765710B (en) * | 2019-10-22 | 2021-11-30 | 清华大学 | Universal logic synthesis method and device based on nonvolatile device |
| CN111027267B (en) * | 2019-11-13 | 2021-01-19 | 广东高云半导体科技股份有限公司 | Method, device and system for realizing optimization of adder in FPGA (field programmable Gate array) logic synthesis |
| WO2022021091A1 (en) * | 2020-07-28 | 2022-02-03 | 华为技术有限公司 | Clock tree architecture, and clock signal transmission method and device |
| CN116108797B (en) * | 2023-04-06 | 2023-06-16 | 中国人民解放军国防科技大学 | Trigger replacement method and device based on trigger fanout number and storage medium |
| CN116595918B (en) * | 2023-07-18 | 2023-12-08 | 奇捷科技(深圳)有限公司 | Method, device, equipment and storage medium for verifying quick logical equivalence |
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| CN101539958B (en) * | 2008-03-18 | 2011-05-25 | 北京芯慧同用微电子技术有限责任公司 | Method and device for designing standard cell library and integrated circuit |
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