CN109617395B - Method and circuit for improving conversion efficiency of charge pump and charge pump - Google Patents
Method and circuit for improving conversion efficiency of charge pump and charge pump Download PDFInfo
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- CN109617395B CN109617395B CN201811616230.5A CN201811616230A CN109617395B CN 109617395 B CN109617395 B CN 109617395B CN 201811616230 A CN201811616230 A CN 201811616230A CN 109617395 B CN109617395 B CN 109617395B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
Abstract
In order to improve the actual conversion efficiency of the charge pump, the invention provides a method and a circuit for improving the conversion efficiency of the charge pump and the charge pump. The method for improving the conversion efficiency of the charge pump comprises the following steps: through simulation and test, the one-to-one correspondence relationship between the highest conversion efficiency, the clock signal frequency and the output voltage of the charge pump and the switch size and/or the capacitance value is obtained, and the corresponding switch size and/or the capacitance value is configured for the current clock signal frequency and/or the output voltage based on the one-to-one correspondence relationship. The invention can keep the optimum corresponding relation determined by simulation and test, thereby ensuring the high conversion efficiency of the charge pump under various conditions.
Description
Technical Field
The invention relates to a method and a circuit for improving conversion efficiency of a charge pump, and the charge pump comprising the circuit.
Background
When the charge pump is designed, different output voltages and clock signal frequencies have optimal switch sizes (switch conduction resistance values) and capacitance values corresponding to the output voltages and the clock signal frequencies, and when the corresponding relationships are optimal, the charge pump can achieve the highest current conversion efficiency. However, in practical applications, the clock signal frequency and/or the output voltage may be adjusted according to the situation, so that the switch size and the capacitance value are no longer in an optimal corresponding relationship, and the actual conversion efficiency of the charge pump is reduced. For example, in the charge pump structure shown in fig. 1, Vout is the output of the charge pump, Vin is the input of the charge pump, the clocks clk and clk _ n control the on and off of the switches (MOS transistors Mn1, Mn2, Mp1, Mp2), and by using the characteristic that the voltage difference between two ends of the capacitor cannot change instantaneously, the capacitor C1 is continuously charged and discharged, so that when the voltage at the V3 point is high, the voltage at the V1 point rises, and finally the voltage is output through the switch Mp 1; symmetrically, when the capacitor C2 is charged and discharged so that the voltage at the point V4 becomes high, the voltage at the point V2 rises, and finally the voltage is output through the switch Mp 2. In the prior art, according to the needs of practical applications, the control signals cfg _ f 0-cfg _ fx are used to adjust the clock signal clk frequency of the charge pump, or the control signals cfg _ v 0-cfg _ vx are used to adjust the output voltage, when the clock signal frequency or the output voltage changes, all devices lose the optimal corresponding relationship determined in the design, including the capacitors and the switches, so the conversion efficiency of the charge pump is not the optimal condition.
Disclosure of Invention
In order to improve the actual conversion efficiency of the charge pump, the invention provides a method and a circuit for improving the conversion efficiency of the charge pump and the charge pump.
The technical scheme of the invention is as follows:
a method for improving the conversion efficiency of a charge pump is characterized in that:
through simulation and test, the one-to-one correspondence relationship between the highest conversion efficiency, the clock signal frequency and the output voltage of the charge pump and the switch size and/or the capacitance value is obtained, and the corresponding switch size and/or the capacitance value is configured for the current clock signal frequency and/or the output voltage based on the one-to-one correspondence relationship.
Further, the method for improving the conversion efficiency of the charge pump specifically has the following three implementation modes:
the first implementation comprises the steps of:
1) keeping the input and output voltages and the capacitance value constant;
2) adjusting the frequency of the clock signal to be A, and adjusting the switch size by using x +1 control signals cfg _ f 0-cfg _ fx for adjusting the frequency of the clock signal through simulation to obtain the switch size SA with the highest conversion efficiency of the charge pump and corresponding cfg _ f 0-cfg _ fx codes;
3) adjusting the frequency of the clock signal to be B, and adjusting the switch size by using x +1 control signals cfg _ f 0-cfg _ fx for adjusting the frequency of the clock signal through simulation to obtain a switch size SB with the highest conversion efficiency of the charge pump and corresponding cfg _ f 0-cfg _ fx codes;
4) respectively obtaining the switch size with the highest charge pump conversion efficiency and the corresponding cfg _ f 0-cfg _ fx codes when the clock signal frequency is different values by using the methods of the steps 2) -3);
5) keeping the frequency of the clock signal and the capacitance value constant;
6) adjusting the output voltage to be V1, and adjusting the switch size by using x +1 control signals cfg _ V0-cfg _ vx for adjusting the output voltage through simulation to obtain the switch size S1 with the highest conversion efficiency of the charge pump and the corresponding cfg _ V0-cfg _ vx codes;
7) adjusting the output voltage to be V2, and adjusting the switch size by using x +1 control signals cfg _ V0-cfg _ vx for adjusting the output voltage through simulation to obtain the switch size S2 with the highest conversion efficiency of the charge pump and the corresponding cfg _ V0-cfg _ vx codes;
8) by using the methods of the steps 6) -7), respectively obtaining the switch size with the highest charge pump conversion efficiency and the corresponding cfg _ v 0-cfg _ vx codes when the output voltage is different values;
9) adding the cfg _ f 0-cfg _ fx codes obtained in the steps 4) and 8) and the cfg _ v 0-cfg _ vx codes bit by bit to finally obtain signals cfg 0-cfgx for controlling the switch size, and when the frequency of the clock signal and/or the output voltage change, adjusting the switch size according to the signals cfg 0-cfgx, so that the conversion efficiency of the charge pump can be kept to be the highest.
The second implementation comprises the steps of:
1) keeping the input and output voltages and the switch size constant.
2) Adjusting the frequency of the clock signal to be A, and adjusting the size of a capacitance value by using x +1 control signals cfg _ f 0-cfg _ fx for adjusting the frequency of the clock signal through simulation to obtain the capacitance value CA which enables the conversion efficiency of the charge pump to be highest and corresponding cfg _ f 0-cfg _ fx codes;
3) adjusting the frequency of the clock signal to be B, and adjusting the size of a capacitance value by using x +1 control signals cfg _ f 0-cfg _ fx for adjusting the frequency of the clock signal through simulation to obtain the capacitance value CB with the highest conversion efficiency of the charge pump and corresponding cfg _ f 0-cfg _ fx codes;
4) respectively obtaining the capacitance value with the highest charge pump conversion efficiency and the corresponding cfg _ f 0-cfg _ fx codes when the clock signal frequency is different by using the methods of the steps 2) -3);
5) keeping the frequency of the clock signal and the size of the switch constant;
6) adjusting the output voltage to be V1, and adjusting the capacitance value by using x +1 control signals cfg _ V0-cfg _ vx for adjusting the output voltage through simulation to obtain a capacitance value C1 with the highest charge pump conversion efficiency and corresponding cfg _ V0-cfg _ vx codes;
7) adjusting the output voltage to be V2, and adjusting the capacitance value by using x +1 control signals cfg _ V0-cfg _ vx for adjusting the output voltage through simulation to obtain a capacitance value C2 with the highest charge pump conversion efficiency and corresponding cfg _ V0-cfg _ vx codes;
8) respectively obtaining a capacitance value with the highest charge pump conversion efficiency and corresponding cfg _ v 0-cfg _ vx codes when the output voltage is different by using the methods of the steps 6) -7);
9) adding the cfg _ f 0-cfg _ fx codes obtained in the steps 4) and 8) and the cfg _ v 0-cfg _ vx codes bit by bit to finally obtain signals cfg 0-cfgx of the control capacitance value, and adjusting the capacitance value according to the signals cfg 0-cfgx when the frequency of the clock signal and/or the output voltage changes, so that the conversion efficiency of the charge pump can be kept highest.
The third implementation comprises the steps of:
1) keeping the input and output voltages constant.
2) Adjusting the frequency of the clock signal to be A, and obtaining a switch size SA and a capacitance value CA which enable the conversion efficiency of the charge pump to be the highest and corresponding cfg _ f 0-cfg _ fx codes by utilizing x +1 control signals cfg _ f 0-cfg _ fx for adjusting the frequency of the clock signal and simultaneously adjusting the switch size and the capacitance value through simulation;
3) adjusting the frequency of the clock signal to be B, and obtaining a switch size SB and a capacitor size CB which enable the conversion efficiency of the charge pump to be the highest and corresponding cfg _ f 0-cfg _ fx codes by utilizing x +1 control signals cfg _ f 0-cfg _ fx for adjusting the frequency of the clock signal and simultaneously adjusting the switch size and the capacitance value through simulation;
4) respectively obtaining the switch size and the capacitance value with the highest conversion efficiency of the charge pump when the clock signal frequency is different values and the corresponding cfg _ f 0-cfg _ fx codes by using the methods in the steps 2) -3);
5) keeping the frequency of the clock signal constant;
6) adjusting the output voltage to be V1, and obtaining a switch size SA and a capacitance value CA which enable the charge pump to have the highest conversion efficiency and corresponding cfg _ V0-cfg _ vx codes by utilizing x +1 control signals cfg _ V0-cfg _ vx for adjusting the output voltage and simultaneously adjusting the switch size and the capacitance value through simulation;
7) adjusting the frequency of a clock signal to be V2, and obtaining a switch size SB and a capacitance value CB which enable the conversion efficiency of the charge pump to be the highest and corresponding cfg _ V0-cfg _ vx codes by utilizing x +1 control signals cfg _ V0-cfg _ vx for adjusting the output voltage and simultaneously adjusting the switch size and the capacitance value through simulation;
8) by using the methods of the steps 6) -7), the switch size and the capacitance value with the highest conversion efficiency of the charge pump and the corresponding cfg _ v 0-cfg _ vx codes are obtained when the output voltage is different;
9) adding the cfg _ f 0-cfg _ fx codes obtained in the steps 4) and 8) and the cfg _ v 0-cfg _ vx codes bit by bit to finally obtain signals cfg 0-cfgx for synchronously controlling the size and the capacitance of the switch, and simultaneously adjusting the size and the capacitance of the switch according to the signals cfg 0-cfgx when the frequency and/or the output voltage of the clock signal change, so that the conversion efficiency of the charge pump can be kept highest.
The invention also provides a circuit for improving the conversion efficiency of the charge pump, wherein the charge pump comprises PMOS tubes Mp1 and Mp2, and NMOS tubes Mn1 and Mn 2; the output of the charge pump is Vout; it is characterized in that:
the circuit comprises switches Sp10, Sp11 … … Sp1x, switches Sp20, Sp21 … … Sp2x, switches Sn10, Sn11 … … Sn1x, switches Sn20, Sn21 … … Sn2x, a PMOS tube Mp11 … … M p1x, a PMOS tube Mp21 … … M p2x, an NMOS tube Mn11 … … M n1x and an NMOS tube Mn21 … … M n2 x;
the switch Sp10 is arranged between the PMOS tube Mp1 and Vout;
the grid ends of the PMOS tubes Mp11 … … M p1x are all connected and are all connected with the grid end of the PMOS tube Mp 1; the drain ends of the PMOS tubes Mp11 … … M p1x are connected and are connected with the drain end of Mp 1; the source ends of the PMOS tubes Mp11 … … M p1x are respectively connected with Vout through the switches Sp11 … … Sp1 x;
the switch Sp20 is arranged between the PMOS tube Mp2 and Vout;
the grid ends of the PMOS tubes Mp21 … … M p2x are all connected and are all connected with the grid end of the PMOS tube Mp 2; the drain ends of the PMOS tubes Mp21 … … M p2x are connected and are connected with the drain end of Mp 2; the source ends of the PMOS tubes Mp21 … … M p2x are respectively connected with Vout through the switches Sp21 … … Sp2 x;
the switch Sn10 is arranged between the NMOS tube Mn1 and Vout;
the grid ends of the NMOS tubes Mn11 … … M n1x are connected and are connected with the grid end of the NMOS tube Mn 1; drain ends of the NMOS tubes Mn11 … … M n1x are connected and are connected with a drain end of Mn 1; the source ends of the NMOS tubes Mn11 … … M n1x are respectively connected with Vout through the switches Sn11 … … Sn1 x;
the switch Sn20 is arranged between the NMOS tube Mn2 and Vout;
the grid ends of the NMOS tubes Mn21 … … M n2x are connected and are connected with the grid end of the NMOS tube Mn 2; drain ends of the NMOS tubes Mn21 … … M n2x are connected and are connected with a drain end of Mn 2; the source ends of the NMOS transistors Mn21 … … M n2x are respectively connected with Vout through the switches Sn21 … … Sn2 x.
The invention also provides another circuit for improving the conversion efficiency of the charge pump, wherein the charge pump comprises PMOS tubes Mp1 and Mp2, NMOS tubes Mn1 and Mn2, capacitors C1 and C2; the output of the charge pump is Vout; the output of the charge pump is Vout; it is characterized in that:
the circuit comprises switches S10, S11 … … S1x, switches S20, S21 … … S2x, a capacitor C11 … … C1x, a capacitor C21 … … C2x, a two-input NAND gate nand10, nand11 … … nand1x, and a two-input NAND gate nand20, nand21 … … nand2 x;
the switch S10 is disposed between the capacitor C1 and the drain of the PMOS transistor Mp1, the other end of the capacitor C1 is connected to the output end of the two-input nand gate nand10, and one input of the two-input nand gate nand10 is connected to the clock signal clk;
a capacitor C11 … … C1x is connected in parallel with the capacitor C1, one end of the capacitor C11 … … C1x is connected with the drain of the PMOS tube Mp1 through a switch S11 … … S1x, the other end of the capacitor C11 … … C1x is connected with the output end of a two-input NAND gate nand11 … … nand1x, and one input end of the two-input NAND gate nand11 … … nand1x is connected with a clock signal clk;
the switch S20 is disposed between the capacitor C2 and the drain of the PMOS transistor Mp2, the other end of the capacitor C2 is connected to the output end of the two-input nand gate nand20, and one input of the two-input nand gate nand20 is connected to the clock signal clk _ n;
the capacitor C21 … … C2x is connected in parallel with the capacitor C2, one end of the capacitor C21 … … C2x is connected to the drain of the PMOS transistor Mp2 through the switch S21 … … S2x, the other end of the capacitor C21 … … C2x is connected to the output end of the two-input nand gate nand21 … … nand2x, and one input end of the two-input nand gate nand21 … … nand2x is connected to the clock signal clk _ n.
The invention also provides a third circuit for improving the conversion efficiency of the charge pump, wherein the charge pump comprises PMOS tubes Mp1 and Mp2, and capacitors C1 and C2; the output of the charge pump is Vout; it is characterized in that:
the circuit comprises switches Sp10, Sp11 … … Sp1x, switches Sp20, Sp21 … … Sp2x, switches Sn10, Sn11 … … Sn1x, switches Sn20, Sn21 … … Sn2x, a PMOS tube Mp11 … … M p1x, a PMOS tube Mp21 … … M p2x, an NMOS tube Mn11 … … M n1x and an NMOS tube Mn21 … … M n2 x;
the switch Sp10 is arranged between the PMOS tube Mp1 and Vout;
the grid ends of the PMOS tubes Mp11 … … M p1x are all connected and are all connected with the grid end of the PMOS tube Mp 1; the drain ends of the PMOS tubes Mp11 … … M p1x are connected and are connected with the drain end of Mp 1; the source ends of the PMOS tubes Mp11 … … M p1x are respectively connected with Vout through the switches Sp11 … … Sp1 x;
the switch Sp20 is arranged between the PMOS tube Mp2 and Vout;
the grid ends of the PMOS tubes Mp21 … … M p2x are all connected and are all connected with the grid end of the PMOS tube Mp 2; the drain ends of the PMOS tubes Mp21 … … M p2x are connected and are connected with the drain end of Mp 2; the source ends of the PMOS tubes Mp21 … … M p2x are respectively connected with Vout through the switches Sp21 … … Sp2 x;
the switch Sn10 is arranged between the NMOS tube Mn1 and Vout;
the grid ends of the NMOS tubes Mn11 … … M n1x are connected and are connected with the grid end of the NMOS tube Mn 1; drain ends of the NMOS tubes Mn11 … … M n1x are connected and are connected with a drain end of Mn 1; the source ends of the NMOS tubes Mn11 … … M n1x are respectively connected with Vout through the switches Sn11 … … Sn1 x;
the switch Sn20 is arranged between the NMOS tube Mn2 and Vout;
the grid ends of the NMOS tubes Mn21 … … M n2x are connected and are connected with the grid end of the NMOS tube Mn 2; drain ends of the NMOS tubes Mn21 … … M n2x are connected and are connected with a drain end of Mn 2; the source ends of the NMOS tubes Mn21 … … M n2x are respectively connected with Vout through the switches Sn21 … … Sn2 x;
the circuit further comprises switches S10, S11 … … S1x, switches S20, S21 … … S2x, a capacitor C11 … … C1x, a capacitor C21 … … C2x, a two-input NAND gate nand10, nand11 … … nand1x, and a two-input NAND gate nand20, nand21 … … nand2 x;
the switch S10 is disposed between the capacitor C1 and the drain of the PMOS transistor Mp1, the other end of the capacitor C1 is connected to the output end of the two-input nand gate nand10, and one input of the two-input nand gate nand10 is connected to the clock signal clk;
a capacitor C11 … … C1x is connected in parallel with the capacitor C1, one end of the capacitor C11 … … C1x is connected with the drain of the PMOS tube Mp1 through a switch S11 … … S1x, the other end of the capacitor C11 … … C1x is connected with the output end of a two-input NAND gate nand11 … … nand1x, and one input end of the two-input NAND gate nand11 … … nand1x is connected with a clock signal clk;
the switch S20 is disposed between the capacitor C2 and the drain of the PMOS transistor Mp2, the other end of the capacitor C2 is connected to the output end of the two-input nand gate nand20, and one input of the two-input nand gate nand20 is connected to the clock signal clk _ n;
the capacitor C21 … … C2x is connected in parallel with the capacitor C2, one end of the capacitor C21 … … C2x is connected to the drain of the PMOS transistor Mp2 through the switch S21 … … S2x, the other end of the capacitor C21 … … C2x is connected to the output end of the two-input nand gate nand21 … … nand2x, and one input end of the two-input nand gate nand21 … … nand2x is connected to the clock signal clk _ n.
The invention also provides a charge pump, which is characterized in that: a circuit for improving the conversion efficiency of a charge pump as described in any of the above.
The invention has the advantages that:
the invention can keep the optimum corresponding relation determined by simulation and test, thereby ensuring the high conversion efficiency of the charge pump under various conditions.
Drawings
Fig. 1 is a structural diagram of a conventional charge pump.
Fig. 2 is a schematic diagram of a first embodiment of the present invention.
Fig. 3 is a schematic diagram of a second embodiment of the present invention.
Fig. 4 is a schematic diagram of a third embodiment of the present invention.
Fig. 5 is a schematic structural diagram of a control part according to a third embodiment of the present invention.
Detailed Description
The invention is further illustrated by the following figures and examples.
Example 1:
when the frequency of the clock signal and/or the output voltage changes, the size of the switch is adjusted to achieve the purpose of improving the conversion efficiency of the charge pump, and the specific implementation method comprises the following steps:
1. keeping the input and output voltages and the capacitance values constant.
2. Adjusting the frequency of the clock signal to be A, and adjusting the switch size by using x +1 control signals cfg _ f 0-cfg _ fx for adjusting the frequency of the clock signal through simulation to obtain the switch size SA with the highest conversion efficiency of the charge pump and the corresponding cfg _ f 0-cfg _ fx codes.
3. And adjusting the frequency of the clock signal to be B, and adjusting the switch size by using x +1 control signals cfg _ f 0-cfg _ fx for adjusting the frequency of the clock signal through simulation to obtain the switch size SB with the highest conversion efficiency of the charge pump and the corresponding cfg _ f 0-cfg _ fx codes.
4. By using the method in the above step 2-3, when the clock signal frequency is different values, the switch size with the highest conversion efficiency of the charge pump and the corresponding cfg _ f 0-cfg _ fx codes are obtained, so as to obtain the optimal one-to-one correspondence relationship between the clock signal frequency and the switch size, and according to the optimal one-to-one correspondence relationship, the corresponding switch size is selected according to the current clock signal frequency in the actual use, so that the conversion efficiency of the charge pump can be kept highest.
5. The clock signal frequency and the capacitance value are kept constant.
6. The output voltage is adjusted to be V1, and the switch size is adjusted by using x +1 control signals cfg _ V0-cfg _ vx for adjusting the output voltage through simulation, so that the switch size S1 with the highest conversion efficiency of the charge pump and the corresponding cfg _ V0-cfg _ vx codes are obtained.
7. The output voltage is adjusted to be V2, and the switch size is adjusted by using x +1 control signals cfg _ V0-cfg _ vx for adjusting the output voltage through simulation to obtain the switch size S2 with the highest conversion efficiency of the charge pump and the corresponding cfg _ V0-cfg _ vx codes.
8. And 6-7, when the output voltages are different values, respectively obtaining the switch size with the highest conversion efficiency of the charge pump and the corresponding cfg _ v 0-cfg _ vx codes, so as to obtain the optimal one-to-one correspondence relationship between the output voltages and the switch sizes, and selecting the corresponding switch size according to the current output voltage in actual use according to the optimal one-to-one correspondence relationship, so that the conversion efficiency of the charge pump can be kept to be the highest.
9. And (3) performing bit-by-bit addition operation on the cfg _ f 0-cfg _ fx codes obtained in the step (4) and the step (8) and the cfg _ v 0-cfg _ vx codes, such as logic OR, to finally obtain signals cfg 0-cfgx for controlling the switch size, and when the frequency of the clock signal and/or the output voltage change, adjusting the switch size according to the signals cfg 0-cfgx, so that the conversion efficiency of the charge pump can be kept highest.
Fig. 2 shows a circuit implementation of this embodiment, which is an improvement on the conventional charge pump structure shown in fig. 1 as follows:
(1) a switch Sp10 is additionally arranged between a PMOS tube Mp1 and Vout, the gate end of Mp1 is connected with a PMOS tube Mp11 … … Mp1x, the gate ends of Mp11 … … M p1x are connected with each other and connected with the gate end of Mp1, the drain ends of Mp11 … … M p1x are connected with each other and connected with the drain end of Mp1, and the source ends of Mp11 … … M p1x are respectively connected with Vout through a switch Sp11 … … Sp1 x;
(2) a switch Sp20 is additionally arranged between a PMOS tube Mp2 and Vout, the gate end of Mp2 is connected with a PMOS tube Mp21 … … Mp2x, the gate ends of Mp21 … … M p2x are connected with each other and connected with the gate end of Mp2, the drain ends of Mp21 … … M p2x are connected with each other and connected with the drain end of Mp2, and the source ends of Mp21 … … M p2x are respectively connected with Vout through a switch Sp21 … … Sp2 x;
(3) a switch Sn10 is additionally arranged between an NMOS tube Mn1 and Vout, the gate end of Mn1 is connected with an NMOS tube Mn11 … … Mn1x, the gate ends of Mn11 … … M n1x are connected and connected with the gate end of Mn1, the drain ends of Mn11 … … M n1x are connected and connected with the drain end of Mn1, and the source ends of Mn11 … … Mn1x are respectively connected with Vout through a switch Sn11 … … Sn1 x;
(4) a switch Sn20 is additionally arranged between an NMOS tube Mn2 and Vout, the gate end of Mn2 is connected with an NMOS tube Mn21 … … Mn2x, the gate ends of Mn21 … … M n2x are connected and connected with the gate end of Mn2, the drain ends of Mn21 … … M n2x are connected and connected with the drain end of Mn2, and the source end of Mn21 … … Mn2x is connected with Vout through a switch Sn21 … … Sn2 x.
(5) The switches Sp10 and Sp11 … … Sp1x are respectively controlled by cfg0 and cfg1 … … cfgx; the switches Sp20 and Sp21 … … Sp2x are respectively controlled by cfg0 and cfg1 … … cfgx; the switches Sn20 and Sn21 … … Sn2x are respectively controlled by cfg0 and cfg1 … … cfgx.
Example 2:
when the frequency of the clock signal and/or the output voltage changes, the capacitance value is adjusted to achieve the purpose of improving the conversion efficiency of the charge pump, and the specific implementation method comprises the following steps:
1. keeping the input and output voltages and the switch size constant.
2. The clock signal frequency is adjusted to be A, and the capacitance value is adjusted by using x +1 control signals cfg _ f 0-cfg _ fx for adjusting the clock signal frequency through simulation, so that the capacitance value CA which enables the charge pump to have the highest conversion efficiency and the corresponding cfg _ f 0-cfg _ fx codes are obtained.
3. And adjusting the frequency of the clock signal to be B, and adjusting the capacitance value by using x +1 control signals cfg _ f 0-cfg _ fx for adjusting the frequency of the clock signal through simulation to obtain the capacitance value CB with the highest conversion efficiency of the charge pump and corresponding cfg _ f 0-cfg _ fx codes.
4. And 2-3, respectively obtaining the capacitance value with the highest charge pump conversion efficiency and the corresponding cfg _ f 0-cfg _ fx codes when the clock signal frequency is different values, so as to obtain the optimal one-to-one correspondence relationship between the clock signal frequency and the capacitance value, and selecting the corresponding capacitance value according to the current clock signal frequency in actual use according to the optimal one-to-one correspondence relationship, so that the charge pump conversion efficiency can be kept to be the highest.
5. Keeping the clock signal frequency and the switch size constant.
6. The output voltage is adjusted to be V1, and the capacitance value is adjusted by using x +1 control signals cfg _ V0-cfg _ vx for adjusting the output voltage through simulation, so that the capacitance value C1 with the highest charge pump conversion efficiency and the corresponding cfg _ V0-cfg _ vx codes are obtained.
7. The output voltage is adjusted to be V2, and the capacitance value is adjusted by using x +1 control signals cfg _ V0-cfg _ vx for adjusting the output voltage through simulation, so that the capacitance value C2 with the highest charge pump conversion efficiency and the corresponding cfg _ V0-cfg _ vx codes are obtained.
8. And 6-7, respectively obtaining the capacitance value with the highest charge pump conversion efficiency and the corresponding cfg _ v 0-cfg _ vx codes when the output voltages are different values, so as to obtain the optimal one-to-one correspondence relationship between the output voltages and the capacitance values, and selecting the corresponding capacitance value according to the current output voltage in actual use according to the optimal one-to-one correspondence relationship, so that the charge pump conversion efficiency can be kept highest.
9. And (3) performing bit-by-bit addition operation on the cfg _ f 0-cfg _ fx codes obtained in the step (4) and the step (8) and the cfg _ v 0-cfg _ vx codes, such as logic OR, to finally obtain signals cfg 0-cfgx for controlling the capacitance value, and adjusting the capacitance value according to the signals cfg 0-cfgx when the frequency of the clock signal and/or the output voltage change, so that the conversion efficiency of the charge pump can be kept highest.
Fig. 3 shows a circuit implementation of this embodiment, which is an improvement on the conventional charge pump structure shown in fig. 1 as follows:
(1) a switch S10 is additionally arranged between the capacitor C1 and the drain electrode of the PMOS tube Mp1, the inverter Inv1 connected to the other end of the capacitor C1 in the figure 1 is replaced by a two-input NAND gate nand10, and one input end of the two-input NAND gate nand10 is connected with a clock signal clk;
(2) a capacitor C11 … … C1x connected with the capacitor C1 in parallel is additionally arranged, one end of the capacitor C11 … … C1x is connected with the drain of a PMOS (P-channel metal oxide semiconductor) tube Mp1 through a switch S11 … … S1x, the other end of the capacitor C11 … … C1x is connected with the output end of a two-input NAND gate nand11 … … nand1x, and one input end of the two-input NAND gate nand11 … … nand1x is connected with a clock signal clk;
(3) a switch S20 is additionally arranged between the capacitor C2 and the drain electrode of the PMOS tube Mp2, the inverter Inv2 connected to the other end of the capacitor C2 in the figure 1 is replaced by a two-input NAND gate nand20, and one input end of the two-input NAND gate nand20 is connected with a clock signal clk _ n;
(4) a capacitor C21 … … C2x connected with a capacitor C2 in parallel is additionally arranged, one end of the capacitor C21 … … C2x is connected with the drain of a PMOS tube Mp2 through a switch S21 … … S2x, the other end of the capacitor C21 … … C2x is connected with the output end of a two-input NAND gate nand21 … … nand2x, and one input end of the two-input NAND gate nand21 … … nand2x is connected with a clock signal clk _ n.
(5) Switches S10 and S11 … … S1x are controlled by cfg0 and cfg1 … … cfgx respectively; switches S20, S21 … … S2x are controlled by cfg0, cfg1 … … cfgx, respectively.
Example 3:
when the frequency of a clock signal and/or the output voltage changes, the capacitance value and the switch size are synchronously adjusted to achieve the purpose of improving the conversion efficiency of the charge pump, and the specific implementation method comprises the following steps:
1. keeping the input and output voltages constant.
2. Adjusting the frequency of the clock signal to be A, and obtaining the switch size SA and the capacitance value CA which enable the charge pump to have the highest conversion efficiency and the corresponding cfg _ f 0-cfg _ fx codes by utilizing x +1 control signals cfg _ f 0-cfg _ fx for adjusting the frequency of the clock signal and simultaneously adjusting the switch size and the capacitance value through simulation.
3. And adjusting the frequency of the clock signal to be B, and simultaneously adjusting the switch size and the capacitance value by using x +1 control signals cfg _ f 0-cfg _ fx for adjusting the frequency of the clock signal and by simulation to obtain the switch size SB and the capacitance size CB which enable the charge pump to have the highest conversion efficiency and the corresponding cfg _ f 0-cfg _ fx codes.
4. And 2-3, respectively obtaining the switch size and the capacitance value with the highest charge pump conversion efficiency when the clock signal frequency is different values, and the corresponding cfg _ f 0-cfg _ fx codes, so as to obtain the optimal one-to-one correspondence relationship between the clock signal frequency and the switch size and the capacitance value, and selecting the corresponding switch size and capacitance value according to the current clock signal frequency in actual use, so that the charge pump conversion efficiency can be kept to be the highest.
5. The clock signal frequency is kept constant.
6. Adjusting the output voltage to be V1, and obtaining the switch size SA and the capacitance value CA which enable the charge pump to have the highest conversion efficiency and the corresponding cfg _ V0-cfg _ vx codes by utilizing x +1 control signals cfg _ V0-cfg _ vx for adjusting the output voltage and simultaneously adjusting the switch size and the capacitance value through simulation.
7. The clock signal frequency is adjusted to be V2, and through simulation, the switch size and the capacitance value CB which enable the charge pump to have the highest conversion efficiency are obtained by utilizing x +1 control signals cfg _ V0-cfg _ vx for adjusting the output voltage and simultaneously adjusting the switch size and the capacitance value, and the corresponding cfg _ V0-cfg _ vx codes.
8. By using the methods in the steps 6 to 7, the switch size and the capacitance value with the highest conversion efficiency of the charge pump and the corresponding cfg _ v 0-cfg _ vx codes are obtained when the output voltages are different values, so that the optimal one-to-one correspondence relationship between the output voltages and the switch size and the capacitance value is obtained, and the conversion efficiency of the charge pump can be kept to be the highest by selecting the corresponding switch size and capacitance value according to the current output voltage in actual use according to the optimal one-to-one correspondence relationship.
9. And (3) performing bit-by-bit addition operation on the cfg _ f 0-cfg _ fx codes obtained in the step (4) and the step (8) and the cfg _ v 0-cfg _ vx codes, such as logic OR, to finally obtain signals cfg 0-cfgx for synchronously controlling the switch size and the capacitance value, and simultaneously adjusting the switch size and the capacitance value according to the signals cfg 0-cfgx when the clock signal frequency and/or the output voltage change, so that the conversion efficiency of the charge pump can be kept highest.
Fig. 4 shows a circuit implementation of this embodiment, which is a solution combining the circuit implementations shown in fig. 2 and 3, and specifically, the following modifications are made on the basis of the existing charge pump structure shown in fig. 1:
(1) a switch Sp10 is additionally arranged between a PMOS tube Mp1 and Vout, the gate end of Mp1 is connected with a PMOS tube Mp11 … … Mp1x, the gate ends of Mp11 … … M p1x are connected with each other and connected with the gate end of Mp1, the drain ends of Mp11 … … M p1x are connected with each other and connected with the drain end of Mp1, and the source ends of Mp11 … … M p1x are respectively connected with Vout through a switch Sp11 … … Sp1 x;
(2) a switch Sp20 is additionally arranged between a PMOS tube Mp2 and Vout, the gate end of Mp2 is connected with a PMOS tube Mp21 … … Mp2x, the gate ends of Mp21 … … M p2x are connected with each other and connected with the gate end of Mp2, the drain ends of Mp21 … … M p2x are connected with each other and connected with the drain end of Mp2, and the source ends of Mp21 … … M p2x are respectively connected with Vout through a switch Sp21 … … Sp2 x;
(3) a switch Sn10 is additionally arranged between an NMOS tube Mn1 and Vout, the gate end of Mn1 is connected with an NMOS tube Mn11 … … Mn1x, the gate ends of Mn11 … … M n1x are connected and connected with the gate end of Mn1, the drain ends of Mn11 … … M n1x are connected and connected with the drain end of Mn1, and the source ends of Mn11 … … Mn1x are respectively connected with Vout through a switch Sn11 … … Sn1 x;
(4) a switch Sn20 is additionally arranged between an NMOS tube Mn2 and Vout, the gate end of Mn2 is connected with an NMOS tube Mn21 … … Mn2x, the gate ends of Mn21 … … M n2x are connected and connected with the gate end of Mn2, the drain ends of Mn21 … … M n2x are connected and connected with the drain end of Mn2, and the source end of Mn21 … … Mn2x is connected with Vout through a switch Sn21 … … Sn2 x.
(5) The switches Sp10 and Sp11 … … Sp1x are respectively controlled by cfg0 and cfg1 … … cfgx; the switches Sp20 and Sp21 … … Sp2x are respectively controlled by cfg0 and cfg1 … … cfgx; the switches Sn20 and Sn21 … … Sn2x are respectively controlled by cfg0 and cfg1 … … cfgx.
(6) A switch S10 is additionally arranged between the capacitor C1 and the drain electrode of the PMOS tube Mp1, the inverter Inv1 connected to the other end of the capacitor C1 in the figure 1 is replaced by a two-input NAND gate nand10, and one input end of the two-input NAND gate nand10 is connected with a clock signal clk;
(7) a capacitor C11 … … C1x connected with the capacitor C1 in parallel is additionally arranged, one end of the capacitor C11 … … C1x is connected with the drain of a PMOS (P-channel metal oxide semiconductor) tube Mp1 through a switch S11 … … S1x, the other end of the capacitor C11 … … C1x is connected with the output end of a two-input NAND gate nand11 … … nand1x, and one input end of the two-input NAND gate nand11 … … nand1x is connected with a clock signal clk;
(8) a switch S20 is additionally arranged between the capacitor C2 and the drain electrode of the PMOS tube Mp2, the inverter Inv2 connected to the other end of the capacitor C2 in the figure 1 is replaced by a two-input NAND gate nand20, and one input end of the two-input NAND gate nand20 is connected with a clock signal clk _ n;
(9) a capacitor C21 … … C2x connected with a capacitor C2 in parallel is additionally arranged, one end of the capacitor C21 … … C2x is connected with the drain of a PMOS tube Mp2 through a switch S21 … … S2x, the other end of the capacitor C21 … … C2x is connected with the output end of a two-input NAND gate nand21 … … nand2x, and one input end of the two-input NAND gate nand21 … … nand2x is connected with a clock signal clk _ n.
(10) Switches S10 and S11 … … S1x are controlled by cfg0 and cfg1 … … cfgx respectively; switches S20, S21 … … S2x are controlled by cfg0, cfg1 … … cfgx, respectively.
Fig. 5 shows the structure of the control part of embodiment 3, in which cfg _ f 0-cfg _ fx codes and cfg _ v 0-cfg _ vx codes are added bit by bit (for example, "logical or" operation) to obtain code values of cfg 0-cfgx.
Claims (5)
1. A method for improving the conversion efficiency of a charge pump is characterized in that:
through simulation and test, the one-to-one correspondence relationship between the highest conversion efficiency, the clock signal frequency and the output voltage of the charge pump and the switch size and/or the capacitance value is obtained, and the corresponding switch size and/or the capacitance value is configured for the current clock signal frequency and/or the output voltage based on the one-to-one correspondence relationship, and the method comprises the following three methods:
a first method, comprising the steps of:
1) keeping the input and output voltages and the capacitance value constant;
2) adjusting the frequency of the clock signal to be A, and adjusting the switch size by using x +1 control signals cfg _ f 0-cfg _ fx for adjusting the frequency of the clock signal through simulation to obtain the switch size SA with the highest conversion efficiency of the charge pump and corresponding cfg _ f 0-cfg _ fx codes;
3) adjusting the frequency of the clock signal to be B, and adjusting the switch size by using x +1 control signals cfg _ f 0-cfg _ fx for adjusting the frequency of the clock signal through simulation to obtain a switch size SB with the highest conversion efficiency of the charge pump and corresponding cfg _ f 0-cfg _ fx codes;
4) respectively obtaining the switch size with the highest charge pump conversion efficiency and the corresponding cfg _ f 0-cfg _ fx codes when the clock signal frequency is different values by using the methods of the steps 2) -3);
5) keeping the frequency of the clock signal and the capacitance value constant;
6) adjusting the output voltage to be V1, and adjusting the switch size by using x +1 control signals cfg _ V0-cfg _ vx for adjusting the output voltage through simulation to obtain the switch size S1 with the highest conversion efficiency of the charge pump and the corresponding cfg _ V0-cfg _ vx codes;
7) adjusting the output voltage to be V2, and adjusting the switch size by using x +1 control signals cfg _ V0-cfg _ vx for adjusting the output voltage through simulation to obtain the switch size S2 with the highest conversion efficiency of the charge pump and the corresponding cfg _ V0-cfg _ vx codes;
8) by using the methods of the steps 6) -7), respectively obtaining the switch size with the highest charge pump conversion efficiency and the corresponding cfg _ v 0-cfg _ vx codes when the output voltage is different values;
9) adding the cfg _ f 0-cfg _ fx codes obtained in the steps 4) and 8) and the cfg _ v 0-cfg _ vx codes bit by bit to finally obtain signals cfg 0-cfgx for controlling the switch size, and when the frequency of the clock signal and/or the output voltage change, adjusting the switch size according to the signals cfg 0-cfgx to keep the highest conversion efficiency of the charge pump;
a second method, comprising the steps of:
1) keeping the input and output voltages and the switch size constant;
2) adjusting the frequency of the clock signal to be A, and adjusting the size of a capacitance value by using x +1 control signals cfg _ f 0-cfg _ fx for adjusting the frequency of the clock signal through simulation to obtain the capacitance value CA which enables the conversion efficiency of the charge pump to be highest and corresponding cfg _ f 0-cfg _ fx codes;
3) adjusting the frequency of the clock signal to be B, and adjusting the size of a capacitance value by using x +1 control signals cfg _ f 0-cfg _ fx for adjusting the frequency of the clock signal through simulation to obtain the capacitance value CB with the highest conversion efficiency of the charge pump and corresponding cfg _ f 0-cfg _ fx codes;
4) respectively obtaining the capacitance value with the highest charge pump conversion efficiency and the corresponding cfg _ f 0-cfg _ fx codes when the clock signal frequency is different by using the methods of the steps 2) -3);
5) keeping the frequency of the clock signal and the size of the switch constant;
6) adjusting the output voltage to be V1, and adjusting the capacitance value by using x +1 control signals cfg _ V0-cfg _ vx for adjusting the output voltage through simulation to obtain a capacitance value C1 with the highest charge pump conversion efficiency and corresponding cfg _ V0-cfg _ vx codes;
7) adjusting the output voltage to be V2, and adjusting the capacitance value by using x +1 control signals cfg _ V0-cfg _ vx for adjusting the output voltage through simulation to obtain a capacitance value C2 with the highest charge pump conversion efficiency and corresponding cfg _ V0-cfg _ vx codes;
8) respectively obtaining a capacitance value with the highest charge pump conversion efficiency and corresponding cfg _ v 0-cfg _ vx codes when the output voltage is different by using the methods of the steps 6) -7);
9) adding the cfg _ f 0-cfg _ fx codes obtained in the steps 4) and 8) and the cfg _ v 0-cfg _ vx codes bit by bit to finally obtain signals cfg 0-cfgx of the control capacitance value, and adjusting the capacitance value according to the signals cfg 0-cfgx when the frequency of the clock signal and/or the output voltage changes, so that the conversion efficiency of the charge pump can be kept highest;
a third method, comprising the steps of:
1) keeping the input and output voltages constant;
2) adjusting the frequency of the clock signal to be A, and obtaining a switch size SA and a capacitance value CA which enable the conversion efficiency of the charge pump to be the highest and corresponding cfg _ f 0-cfg _ fx codes by utilizing x +1 control signals cfg _ f 0-cfg _ fx for adjusting the frequency of the clock signal and simultaneously adjusting the switch size and the capacitance value through simulation;
3) adjusting the frequency of the clock signal to be B, and obtaining a switch size SB and a capacitor size CB which enable the conversion efficiency of the charge pump to be the highest and corresponding cfg _ f 0-cfg _ fx codes by utilizing x +1 control signals cfg _ f 0-cfg _ fx for adjusting the frequency of the clock signal and simultaneously adjusting the switch size and the capacitance value through simulation;
4) respectively obtaining the switch size and the capacitance value with the highest conversion efficiency of the charge pump when the clock signal frequency is different values and the corresponding cfg _ f 0-cfg _ fx codes by using the methods in the steps 2) -3);
5) keeping the frequency of the clock signal constant;
6) adjusting the output voltage to be V1, and obtaining a switch size SA and a capacitance value CA which enable the charge pump to have the highest conversion efficiency and corresponding cfg _ V0-cfg _ vx codes by utilizing x +1 control signals cfg _ V0-cfg _ vx for adjusting the output voltage and simultaneously adjusting the switch size and the capacitance value through simulation;
7) adjusting the frequency of a clock signal to be V2, and obtaining a switch size SB and a capacitance value CB which enable the conversion efficiency of the charge pump to be the highest and corresponding cfg _ V0-cfg _ vx codes by utilizing x +1 control signals cfg _ V0-cfg _ vx for adjusting the output voltage and simultaneously adjusting the switch size and the capacitance value through simulation;
8) by using the methods of the steps 6) -7), the switch size and the capacitance value with the highest conversion efficiency of the charge pump and the corresponding cfg _ v 0-cfg _ vx codes are obtained when the output voltage is different;
9) adding the cfg _ f 0-cfg _ fx codes obtained in the steps 4) and 8) and the cfg _ v 0-cfg _ vx codes bit by bit to finally obtain signals cfg 0-cfgx for synchronously controlling the size and the capacitance of the switch, and simultaneously adjusting the size and the capacitance of the switch according to the signals cfg 0-cfgx when the frequency and/or the output voltage of the clock signal change, so that the conversion efficiency of the charge pump can be kept highest.
2. A circuit for improving the conversion efficiency of a charge pump comprises PMOS tubes Mp1 and Mp2, NMOS tubes Mn1 and Mn 2; the output of the charge pump is Vout; the method is characterized in that:
the circuit comprises switches Sp10, Sp11 … … Sp1x, switches Sp20, Sp21 … … Sp2x, switches Sn10, Sn11 … … Sn1x, switches Sn20, Sn21 … … Sn2x, a PMOS tube Mp11 … … M p1x, a PMOS tube Mp21 … … M p2x, an NMOS tube Mn11 … … Mn1x and an NMOS tube Mn21 … … Mn2 x;
the switch Sp10 is arranged between the PMOS tube Mp1 and Vout;
the grid ends of the PMOS tubes Mp11 … … M p1x are all connected and are all connected with the grid end of the PMOS tube Mp 1; the drain ends of the PMOS tubes Mp11 … … M p1x are connected and are connected with the drain end of Mp 1; the source ends of the PMOS tubes Mp11 … … M p1x are respectively connected with Vout through the switches Sp11 … … Sp1 x;
the switch Sp20 is arranged between the PMOS tube Mp2 and Vout;
the grid ends of the PMOS tubes Mp21 … … M p2x are all connected and are all connected with the grid end of the PMOS tube Mp 2; the drain ends of the PMOS tubes Mp21 … … M p2x are connected and are connected with the drain end of Mp 2; the source ends of the PMOS tubes Mp21 … … M p2x are respectively connected with Vout through the switches Sp21 … … Sp2 x;
the switch Sn10 is arranged between the NMOS tube Mn1 and Vout;
the grid ends of the NMOS tubes Mn11 … … Mn1x are connected and are connected with the grid end of the NMOS tube Mn 1; drain ends of the NMOS tubes Mn11 … … Mn1x are connected and are connected with a drain end of Mn 1; the source ends of the NMOS tubes Mn11 … … Mn1x are respectively connected with Vout through the switches Sn11 … … Sn1 x;
the switch Sn20 is arranged between the NMOS tube Mn2 and Vout;
the grid ends of the NMOS tubes Mn21 … … Mn2x are connected and are connected with the grid end of the NMOS tube Mn 2; drain ends of the NMOS tubes Mn21 … … Mn2x are connected and are connected with a drain end of Mn 2; the source ends of the NMOS tubes Mn21 … … Mn2x are respectively connected with Vout through the switches Sn21 … … Sn2 x.
3. A circuit for improving the conversion efficiency of a charge pump comprises PMOS tubes Mp1 and Mp2, NMOS tubes Mn1 and Mn2, capacitors C1 and C2; the output of the charge pump is Vout; the output of the charge pump is Vout; the method is characterized in that:
the circuit comprises switches S10, S11 … … S1x, switches S20, S21 … … S2x, a capacitor C11 … … C1x, a capacitor C21 … … C2x, a two-input NAND gate nand10, nand11 … … nand1x, and a two-input NAND gate nand20, nand21 … … nand2 x;
the switch S10 is disposed between the capacitor C1 and the drain of the PMOS transistor Mp1, the other end of the capacitor C1 is connected to the output end of the two-input nand gate nand10, and one input of the two-input nand gate nand10 is connected to the clock signal clk;
a capacitor C11 … … C1x is connected in parallel with the capacitor C1, one end of the capacitor C11 … … C1x is connected with the drain of the PMOS tube Mp1 through a switch S11 … … S1x, the other end of the capacitor C11 … … C1x is connected with the output end of a two-input NAND gate nand11 … … nand1x, and one input end of the two-input NAND gate nand11 … … nand1x is connected with a clock signal clk;
the switch S20 is disposed between the capacitor C2 and the drain of the PMOS transistor Mp2, the other end of the capacitor C2 is connected to the output end of the two-input nand gate nand20, and one input of the two-input nand gate nand20 is connected to the clock signal clk _ n;
the capacitor C21 … … C2x is connected in parallel with the capacitor C2, one end of the capacitor C21 … … C2x is connected to the drain of the PMOS transistor Mp2 through the switch S21 … … S2x, the other end of the capacitor C21 … … C2x is connected to the output end of the two-input nand gate nand21 … … nand2x, and one input end of the two-input nand gate nand21 … … nand2x is connected to the clock signal clk _ n.
4. A circuit for improving the conversion efficiency of a charge pump comprises PMOS tubes Mp1 and Mp2, capacitors C1 and C2; the output of the charge pump is Vout; the method is characterized in that:
the circuit comprises switches Sp10, Sp11 … … Sp1x, switches Sp20, Sp21 … … Sp2x, switches Sn10, Sn11 … … Sn1x, switches Sn20, Sn21 … … Sn2x, a PMOS tube Mp11 … … M p1x, a PMOS tube Mp21 … … M p2x, an NMOS tube Mn11 … … Mn1x and an NMOS tube Mn21 … … Mn2 x;
the switch Sp10 is arranged between the PMOS tube Mp1 and Vout;
the grid ends of the PMOS tubes Mp11 … … M p1x are all connected and are all connected with the grid end of the PMOS tube Mp 1; the drain ends of the PMOS tubes Mp11 … … M p1x are connected and are connected with the drain end of Mp 1; the source ends of the PMOS tubes Mp11 … … M p1x are respectively connected with Vout through the switches Sp11 … … Sp1 x;
the switch Sp20 is arranged between the PMOS tube Mp2 and Vout;
the grid ends of the PMOS tubes Mp21 … … M p2x are all connected and are all connected with the grid end of the PMOS tube Mp 2; the drain ends of the PMOS tubes Mp21 … … M p2x are connected and are connected with the drain end of Mp 2; the source ends of the PMOS tubes Mp21 … … M p2x are respectively connected with Vout through the switches Sp21 … … Sp2 x;
the switch Sn10 is arranged between the NMOS tube Mn1 and Vout;
the grid ends of the NMOS tubes Mn11 … … Mn1x are connected and are connected with the grid end of the NMOS tube Mn 1; drain ends of the NMOS tubes Mn11 … … Mn1x are connected and are connected with a drain end of Mn 1; the source ends of the NMOS tubes Mn11 … … Mn1x are respectively connected with Vout through the switches Sn11 … … Sn1 x;
the switch Sn20 is arranged between the NMOS tube Mn2 and Vout;
the grid ends of the NMOS tubes Mn21 … … Mn2x are connected and are connected with the grid end of the NMOS tube Mn 2; drain ends of the NMOS tubes Mn21 … … Mn2x are connected and are connected with a drain end of Mn 2; the source ends of the NMOS tubes Mn21 … … Mn2x are respectively connected with Vout through the switches Sn21 … … Sn2 x;
the circuit further comprises switches S10, S11 … … S1x, switches S20, S21 … … S2x, a capacitor C11 … … C1x, a capacitor C21 … … C2x, a two-input NAND gate nand10, nand11 … … nand1x, and a two-input NAND gate nand20, nand21 … … nand2 x;
the switch S10 is disposed between the capacitor C1 and the drain of the PMOS transistor Mp1, the other end of the capacitor C1 is connected to the output end of the two-input nand gate nand10, and one input of the two-input nand gate nand10 is connected to the clock signal clk;
a capacitor C11 … … C1x is connected in parallel with the capacitor C1, one end of the capacitor C11 … … C1x is connected with the drain of the PMOS tube Mp1 through a switch S11 … … S1x, the other end of the capacitor C11 … … C1x is connected with the output end of a two-input NAND gate nand11 … … nand1x, and one input end of the two-input NAND gate nand11 … … nand1x is connected with a clock signal clk;
the switch S20 is disposed between the capacitor C2 and the drain of the PMOS transistor Mp2, the other end of the capacitor C2 is connected to the output end of the two-input nand gate nand20, and one input of the two-input nand gate nand20 is connected to the clock signal clk _ n;
the capacitor C21 … … C2x is connected in parallel with the capacitor C2, one end of the capacitor C21 … … C2x is connected to the drain of the PMOS transistor Mp2 through the switch S21 … … S2x, the other end of the capacitor C21 … … C2x is connected to the output end of the two-input nand gate nand21 … … nand2x, and one input end of the two-input nand gate nand21 … … nand2x is connected to the clock signal clk _ n.
5. A charge pump, comprising: a circuit for improving the conversion efficiency of a charge pump comprising a circuit as claimed in any one of claims 2 to 4.
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| US20090072891A1 (en) * | 2007-09-14 | 2009-03-19 | Srinivas Perisetty | Varactor-based charge pump |
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