CN107579725B

CN107579725B - Half-cycle delay circuit

Info

Publication number: CN107579725B
Application number: CN201710859649.2A
Authority: CN
Inventors: 何力
Original assignee: IPGoal Microelectronics Sichuan Co Ltd
Current assignee: IPGoal Microelectronics Sichuan Co Ltd
Priority date: 2017-09-21
Filing date: 2017-09-21
Publication date: 2020-08-11
Anticipated expiration: 2037-09-21
Also published as: CN107579725A

Abstract

The invention discloses a half-cycle delay circuit, which carries out N half-cycle delay on an input digital signal and comprises a phase inverter and N shift units, wherein each shift unit is provided with two differential signal input ends and two differential signal output ends, each shift unit is also provided with two differential clock input ends, an external pair of differential signals are input into the differential input end of the first shift unit, the differential output end of the Nth shift unit outputs a delayed differential signal, and the differential output ends of the other shift units are sequentially connected with the differential input ends; an external clock signal is input into the input end of the phase inverter, the external clock signal and the clock signal output by the phase inverter form a pair of differential clock signals, and the differential clock signals are respectively input into the differential clock input ends of the shift units; n is a natural number greater than 1. The half-period delay circuit reduces the number of field effect tubes required to be used, and saves power consumption and occupied area of a chip; and enhances the common mode noise interference resistance.

Description

Half-cycle delay circuit

Technical Field

The present invention relates to the field of integrated circuits, and more particularly, to a half-cycle delay circuit that delays an input differential digital signal by N half cycles.

Background

In some specific integrated circuit applications, such as high-speed data interface circuits, it is usually necessary to delay a digital signal by N/2 clock cycles, i.e., N half cycles, and a module implementing the delay of N half cycles is a half-cycle delay circuit.

Currently, a half-cycle delay circuit in the prior art is formed by cascading N D flip-flops, as shown in fig. 1 (illustrated by the case of N ═ 4), and the half-cycle delay circuit includes 4D flip-flops D1, D2, D3 and D4. The clock input of the odd-numbered stage D flip-flops is connected to the clock signal CLKN, and the clock input of the even-numbered stage D flip-flops is connected to the clock signal CLKP (as shown in fig. 1, CLKP and CLKN are complementary clock signals). Except the last stage of D trigger, the output end Q of each of the other D triggers is connected with the input end D of the next D trigger. If the input signal DIN is updated when the rising edge of the clock signal CLKP arrives, the 1 st stage D flip-flop samples the input signal DIN when the falling edge of the clock signal CLKP arrives, i.e., samples the input signal DIN for a half clock cycle (the clock cycle refers to the oscillation cycle of CLKP, CLKN) after the rising edge of the clock signal CLKP arrives, and outputs the signal O1. Therefore, the output signal O1 is actually output after delaying the input signal DIN by half a cycle, and the signal O1 is updated temporarily at the rising edge of the clock signal CLKN (equivalent to the falling edge of CLKP). Since the level 2D flip-flop samples the signal D1 when the rising edge of the clock signal CLKP arrives, the output signal D2 is updated half a clock cycle after the update of the signal O1, and thus the signal D2 is actually a half clock cycle delay of the signal O1. Similarly, the signal O3 is a half-cycle delay of the signal O2, and the signal O4 is a half-cycle delay of the signal O3. Therefore, in the circuit configuration shown in fig. 1, the signal O1 is delayed by 1 half cycle of the input signal DIN, the signal O2 is delayed by 2 half cycles of the input signal DIN, the signal O3 is delayed by 3 half cycles of the input signal DIN, and the signal O4 is delayed by 4 half cycles of the input signal DIN, so that the circuit realizes the function of delaying the input signal DIN by 4 half clock cycles; that is, when N D flip-flops are provided in the circuit, the function of delaying the input signal DIN by N half clock cycles can be realized.

The circuit structure of the D flip-flop in the prior art structure is shown in fig. 2. The inverter comprises 5 inverters (INV1, INV2, INV3, INV4 and INV5) and 4 transmission gates (T1, T2, T3 and T4). Each phase inverter is composed of 1P-type MOS tube and 1N-type MOS tube, and the transmission gate is composed of 1P-type MOS tube and 1N-type MOS tube; therefore, the D flip-flop shown in fig. 2 is composed of 18 MOS transistors (9N-type MOS transistors, 9P-type MOS transistors). When the half-cycle delay circuit of the prior art is an N-bit delay circuit, a total of 18N MOS transistors are required (wherein the MOS transistor required by the inverter INV0 for generating the inverted clock signal CLKN of CLKP in fig. 1 is also omitted). When the value of N is larger, the whole circuit needs more MOS tubes, thereby consuming large area and power consumption cost. In addition, the D flip-flop shown in fig. 2 is a single-ended signal input/output, and the single-ended signal has a weak ability to resist external common mode interference (such as unstable ripple on the power supply), which is likely to cause distortion in signal transmission.

Therefore, there is a need for an improved half-cycle delay circuit that has a smaller footprint, lower power consumption cost, and greater immunity to interference.

Disclosure of Invention

The half-cycle delay circuit reduces the number of field effect tubes required to be used, and saves power consumption and occupied area of a chip; meanwhile, the common mode noise interference resistance is enhanced.

In order to achieve the above object, the present invention provides a half-cycle delay circuit, which delays an input digital signal by N half cycles, and comprises a phase inverter and N shift units, each shift unit has two differential signal input terminals and two differential signal output terminals, and each shift unit also has two differential clock input terminals, an external pair of differential signals are input to the differential input terminal of the first shift unit, the differential output terminal of the nth shift unit outputs a delayed differential signal, and the differential output terminals of the other shift units are sequentially connected to the differential input terminals; an external clock signal is input into the input end of the phase inverter, the output end of the phase inverter outputs another clock signal, the external clock signal and the clock signal output by the phase inverter form a pair of differential clock signals, and the differential clock signals are respectively input into the differential clock input ends of the shift units; n is a natural number greater than 1.

Preferably, when the difference between the clock signals input to the two differential clock input terminals of the shift unit is positive, the differential input terminal of the current shift unit updates data.

Preferably, each of the shift units has identical structural features, and each of the shift units includes five P-type fets and five N-type fets.

Preferably, each of the shift units includes a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor, an eighth field effect transistor, a ninth field effect transistor, and a tenth field effect transistor; the source electrodes of the first field effect transistor and the second field effect transistor are connected with an external power supply, and the drain electrodes of the first field effect transistor, the third field effect transistor, the seventh field effect transistor and the ninth field effect transistor are connected with the grid electrodes of the second field effect transistor and the tenth field effect transistor together to form a differential signal output end of the shifting unit; the grid electrodes of the first field effect transistor and the ninth field effect transistor and the drain electrodes of the second field effect transistor, the fourth field effect transistor, the eighth field effect transistor and the tenth field effect transistor are connected together to form the other differential signal output end of the shifting unit; the grid electrodes of the third field effect transistor and the seventh field effect transistor are connected together to form a differential input end of the shift unit; the grids of the fourth field effect transistor and the eighth field effect transistor are connected together and form the other differential input end of the shift unit; the source electrodes of the third field effect transistor and the fourth field effect transistor are connected with the drain electrode of the fifth field effect transistor, the grid electrode of the fifth field effect transistor forms a clock input end of the shifting unit, and the source electrode of the fifth field effect transistor is grounded; the source electrode of the sixth field effect transistor is connected with an external power supply, the grid electrode of the sixth field effect transistor forms the other clock input end of the shifting unit, and the drain electrode of the sixth field effect transistor is respectively connected with the source electrodes of the seventh field effect transistor and the eighth field effect transistor; and the source electrodes of the ninth field effect transistor and the tenth field effect transistor are grounded.

Preferably, when the difference between the clock signal input to the gate of the fifth fet and the clock signal input to the gate of the sixth fet is positive, the differential signal input to the two differential input terminals of the current shift unit updates data.

Preferably, the first field effect transistor, the second field effect transistor, the sixth field effect transistor, the seventh field effect transistor and the eighth field effect transistor are all P-type field effect transistors; the third field effect transistor, the fourth field effect transistor, the fifth field effect transistor, the ninth field effect transistor and the tenth field effect transistor are all N-type field effect transistors.

Compared with the prior art, the half-cycle delay circuit delays the input differential signal by N half cycles in a differential input and output mode, so that the resistance of the signal to common-mode interference is enhanced, and the half-cycle delay circuit has stronger common-mode noise interference resistance; meanwhile, the half-period delay circuit of the invention needs fewer field effect tubes, thereby greatly saving power consumption and chip area.

The invention will become more apparent from the following description when taken in conjunction with the accompanying drawings, which illustrate embodiments of the invention.

Drawings

Fig. 1 is a block diagram of a prior art half-cycle delay circuit.

Fig. 2 is a block diagram of a D flip-flop in a prior art half-cycle delay circuit.

Fig. 3 is a block diagram of a half-cycle delay circuit of the present invention.

Fig. 4 is a circuit configuration diagram of a shift unit of the half-cycle delay circuit of the present invention.

Fig. 5 is a block diagram of one embodiment of a half-cycle delay circuit of the present invention.

Fig. 6 is a waveform diagram of the half-cycle delay circuit shown in fig. 5.

Detailed Description

Embodiments of the present invention will now be described with reference to the drawings, wherein like element numerals represent like elements. As described above, the present invention provides a half-cycle delay circuit, which reduces the number of field effect transistors to be used, and saves power consumption and chip occupation area; meanwhile, the common mode noise interference resistance is enhanced.

Referring to fig. 3, fig. 3 is a block diagram of a half-cycle delay circuit according to the present invention. As shown in the figure, the half-cycle delay circuit of the invention delays the input digital signals (DINN, DINP) by N half cycles; the half-period delay circuit comprises an inverter INV0 and N shifting units (shifting

units

1 and 2 … … N), wherein N is a natural number greater than 1, and the value of N can be flexibly selected according to specific conditions in the actual use process. Each of the shift cells has two differential signal inputs (vin, vip) and two differential signal outputs (von, vop), and each of the shift cells also has two differential clock inputs (ckn, ckp); an external pair of differential signals DINN and DINP are input into a differential input end of the first shifting unit, and a differential output end (von and vop) of the Nth shifting unit outputs delayed differential signals DNN and DNP; the differential output ends and the differential input ends of the rest of the shift units are sequentially connected in sequence (as shown in fig. 3); an external clock signal CLKP is input to an input end of the inverter INV0, an output end of the inverter INV0 outputs another clock signal CLKN, the external clock signal CLKP and the clock signal CLKN output by the inverter INV0 form a pair of differential clock signals, and the differential clock signals are respectively input to differential clock input ends (ckn, ckp) of the shift units, as shown in fig. 3. Further, when the difference of the clock signals input to the two differential clock inputs of the shift unit is positive, the differential input of the current shift unit updates data, that is, the values of ckp-ckn are positive, and the differential input (vin, vip) of each shift unit updates data; that is, when the clock signal input by the differential clock input end of each shift unit is inverted, the input differential signal is sequentially delayed and output, so that the delay of N half cycles of the input differential signals DINP and DINN is finally realized.

As a preferred embodiment of the present invention, N of the shift units have identical structural features, and each of the shift units includes five P-type fets and five N-type fets. Specifically, please refer to fig. 4 in combination, which takes any one of the shift units as an example for description. As shown in fig. 4, each of the shift units includes a first fet M1, a second fet M2, a third fet M3, a fourth fet M4, a fifth fet M5, a sixth fet M6, a seventh fet M7, an eighth fet M8, a ninth fet M9, and a tenth fet M10; the source electrodes of the first field-effect transistor M1 and the second field-effect transistor M2 are both connected with an external power supply VDD, and the drain electrodes of the first field-effect transistor M1, the third field-effect transistor M3, the seventh field-effect transistor M7, the ninth field-effect transistor M9, the second field-effect transistor M2 and the tenth field-effect transistor M10 are commonly connected to form a differential signal output end vop of the shift unit so as to output a differential signal which is delayed by half a cycle compared with the output signal of the previous shift unit; the gates of the first fet M1 and the ninth fet M9 and the drains of the second fet M2, the fourth fet M4, the eighth fet M8, and the tenth fet 10 are commonly connected to form another differential signal output terminal von of the shift unit, so as to output another differential signal that is delayed by half a cycle from the output signal of the previous shift unit; the gates of the third fet M3 and the seventh fet M7 are commonly connected to form a differential input vin of the shift unit, so that a differential signal output by the previous shift unit is input to the current shift unit through the differential input vin; the gates of the fourth fet M4 and the eighth fet M8 are commonly connected, and form another differential input vip of the shift unit, so that a differential signal output by the previous shift unit is input to the current shift unit through the differential input vip; the sources of the third field-effect transistor M3 and the fourth field-effect transistor M4 are both connected to the drain of the fifth field-effect transistor M5, the gate of the fifth field-effect transistor M5 forms a clock input end ckp of the shift unit, and the source of the fifth field-effect transistor M5 is grounded; the source of the sixth fet M6 is connected to an external power supply VDD, the gate of the sixth fet M6 forms another clock input ckn of the shift unit, and the drain of the sixth fet M6 is connected to the sources of the seventh fet M7 and the eighth fet M8, respectively; the sources of the ninth field effect transistor M9 and the tenth field effect transistor M10 are grounded. In this embodiment, when the difference between the clock signal input to the gate of the fifth fet M5 and the clock signal input to the gate of the sixth fet M6 is positive, that is, ckp to ckn are positive values, the differential signals input to the two differential input terminals vin and vip of the current shift unit update data. In the preferred embodiment, the first fet M1, the second fet M2, the sixth fet M6, the seventh fet M7, and the eighth fet M8 are all P-type fets, and the third fet M3, the fourth fet M4, the fifth fet M5, the ninth fet M9, and the tenth fet M10 are all N-type fets.

Specifically, the working process of the shift unit is as follows: when the clock signal input to the clock signal input terminal ckp is at a high level, i.e., ckp is equal to 1, and the clock signal input to the clock signal input terminal ckn is at a low level, i.e., ckn is equal to 0, the fifth fet M5 and the sixth fet M6 are turned on. As is well known, there are two cases of differential signal inputs: vip ═ 1 and vin ═ 0 or vip ═ 0 and vin ═ 1. When ckp is equal to 1 and ckn is equal to 0, when vip is equal to 1 and vin is equal to 0, since the fifth fet M5 and the seventh fet M7 are both turned on, the drain voltage of the seventh fet M7 is approximately equal to the power supply voltage VDD (high level), and thus the differential output terminal vop outputs a high level signal. In addition, since the drain of the seventh fet M7 is connected to the gate of the tenth fet M10, the gate voltage of the tenth fet M10 is also approximately equal to the power voltage VDD, and the tenth fet M10 is turned on to ground, the drain voltage of the tenth fet M10 will drop to 0, and the differential signal output terminal von outputs a low level signal; that is, vop ═ vip ═ 1, and von ═ vin ═ 0. When vip is 0 and vin is 1, the gate voltage of the third fet M3 is high, and at the same time, the third fet M3 and the fifth fet M5 are turned on to ground, the drain voltage of the third fet M3 will drop to approximately 0, that is, vop is 0, and the gate voltage of the second fet M2 is low as vop; when the second fet M2 is turned on to the power supply VDD, the drain voltage of the second fet M2 rises to a high level, von equals 1, where vp equals 0 and von equals 1. It follows that when ckp is equal to 1 and ckn is equal to 0, the differential outputs vop, von are equal to the values of vip, vin, respectively, regardless of whether the differential inputs vip, vin take positive or negative values. When the falling edge of the clock signal inputted to the clock input terminal ckp comes (according to the difference characteristics of ckp and ckn, the rising edge of ckn comes), the gate voltage of the fifth fet M5 becomes low, the gate voltage of the sixth fet M6 becomes high, the fifth fet M5 and the sixth fet M6 are turned off, and the signal paths of the third fet M3, the fourth fet M4, the seventh fet M7 and the eighth fet M8 are cut off, so that the output signals von and vop are not affected by the input signals vip and vin. At this time, if the instantaneous vop before the turn-off of the fifth fet M5 and the sixth fet M6 is 1 and von is 0, the gate of the tenth fet M10 is at a high level, the drain of the tenth fet M10 is at a low level, and the drain of the first fet M1 is at a low level, so that the instantaneous vop after the turn-off is 1 and the instantaneous von is 0. If the vop is 0 and the von is 1 immediately before the turn-off of the fifth fet M5 and the sixth fet M6, the gate of the second fet M2 is at a low level, the drain of the second fet M2 is at a high level, and the gate of the ninth fet M9 is at a high level, so that the vop is 0 and the von is 1 after the turn-off. It can therefore be concluded that when ckp is equal to 0(ckn is equal to 1), the value of vop, von will remain unchanged and equal to the value of the temporary vop, von at the falling edge of ckp.

From the above, each shifting unit adopted by the half-cycle delay circuit of the present invention only needs 10 field effect transistors while realizing half-cycle delay of the input signal, which is much smaller than 18 field effect transistors needed by the D flip-flop in the half-cycle delay circuit of the prior art; therefore, the half-period delay circuit greatly saves power consumption and chip area.

In addition, an embodiment of the present invention is described with reference to fig. 5 and fig. 6. As shown in fig. 4, the half-cycle delay circuit of the present embodiment is composed of 1 inverter INV0 and four shift units. Each shift cell has two differential signal inputs vip, vin, two differential signal outputs vop, von, and two differential clock signal inputs ckp and ckn. The inverter INV0 is mainly used for generating a difference signal CLKN of the input clock signal CLKP (CLKN is an inverted signal of CLKP). Each shifting unit has the function that when the difference value of the clock signals of the two differential clock input ends is positive, the differential input ends of the shifting unit update data; specifically, when the differential clock input ckp is high and ckn is low (i.e., when the differential clock signals ckp-ckn are positive), its output vop, von follows the input vip, vin (i.e., vop is vip, von is vin), and when the differential clock input ckp is low and ckn is high (i.e., when the differential signals ckp-ckn are negative), its output vop, von remains constant and has a value equal to the value at the time when the last falling edge at the input of ckp is imminent.

The overall operation of the half-cycle delay circuit shown in figure 5 is briefly described below. The input difference signals DINP and DINN are set to update data when the rising edge of the clock signal CLKP approaches (as shown in fig. 6, the gap delay between the DINP changing edge and the rising edge of CLKP is the signal propagation delay time), and the time when this occurs is t-0 (in fig. 6, time t is 1,2, and 3 … respectively represent the time when the rising edge and the falling edge of CLKP correspond to each other in sequence). Between time t1 and t2, the signal output by a differential output D1P of the shift unit 1 follows the input signal DINP, and between t2 and t3, the signal output by the differential output D1P is kept at the value of DINP corresponding to time t2, i.e., between t1 and t3, the value of D1P is equal to the value of DINP between t 0 and t2, corresponding to a half clock period delay for DINP. Similarly, the signal value output by the differential output terminal D2P of the shift unit 2 is the signal value delayed by half clock cycle from D1P, the signal value output by the differential output terminal D3P of the shift unit 3 is the signal value delayed by half clock cycle from D2P, and the signal value output by the differential output terminal D4P of the shift unit 4 is the signal value delayed by half clock cycle from D3P; similarly, the input differential signal DINN to the output differential signal D4N are similar to the above process, and will not be described herein again. The half-cycle delay circuit of the present embodiment thus implements a function of delaying the differential input signals DINP and DINN by 4 and a half clock cycles.

The present invention has been described in connection with the preferred embodiments, but the present invention is not limited to the embodiments disclosed above, and is intended to cover various modifications, equivalent combinations, which are made in accordance with the spirit of the present invention.

Claims

1. A half-cycle delay circuit, carry on N half-cycle delay to the digital signal input, characterized by that, including a phase inverter and N shift units, each said shift unit has two differential signal input ends and two differential signal output ends, and each said shift unit also has two differential clock input ends, the external one pair of differential signals inputs the differential input end of the first said shift unit, the differential output end of the Nth said shift unit outputs the differential signal after delaying, the differential output end and differential input end of every said shift unit of the others are connected sequentially; an external clock signal is input into the input end of the phase inverter, the output end of the phase inverter outputs another clock signal, the external clock signal and the clock signal output by the phase inverter form a pair of differential clock signals, and the differential clock signals are respectively input into the differential clock input ends of the shift units; n is a natural number greater than 1; each shifting unit has the same structural characteristics and comprises five P-type field effect transistors and five N-type field effect transistors;

each shifting unit comprises a first field effect tube, a second field effect tube, a third field effect tube, a fourth field effect tube, a fifth field effect tube, a sixth field effect tube, a seventh field effect tube, an eighth field effect tube, a ninth field effect tube and a tenth field effect tube; the source electrodes of the first field effect transistor and the second field effect transistor are connected with an external power supply, and the drain electrodes of the first field effect transistor, the third field effect transistor, the seventh field effect transistor and the ninth field effect transistor are connected with the grid electrodes of the second field effect transistor and the tenth field effect transistor together to form a differential signal output end of the shifting unit; the grid electrodes of the first field effect transistor and the ninth field effect transistor and the drain electrodes of the second field effect transistor, the fourth field effect transistor, the eighth field effect transistor and the tenth field effect transistor are connected together to form the other differential signal output end of the shifting unit; the grid electrodes of the third field effect transistor and the seventh field effect transistor are connected together to form a differential input end of the shift unit; the grids of the fourth field effect transistor and the eighth field effect transistor are connected together and form the other differential input end of the shift unit; the source electrodes of the third field effect transistor and the fourth field effect transistor are connected with the drain electrode of the fifth field effect transistor, the grid electrode of the fifth field effect transistor forms a clock input end of the shifting unit, and the source electrode of the fifth field effect transistor is grounded; the source electrode of the sixth field effect transistor is connected with an external power supply, the grid electrode of the sixth field effect transistor forms the other clock input end of the shifting unit, and the drain electrode of the sixth field effect transistor is respectively connected with the source electrodes of the seventh field effect transistor and the eighth field effect transistor; and the source electrodes of the ninth field effect transistor and the tenth field effect transistor are grounded.

2. The half-cycle delay circuit of claim 1, wherein the differential input terminal of the current shift cell updates data when the difference of the clock signals input to the two differential clock input terminals of the shift cell is positive.

3. The half-cycle delay circuit of claim 2, wherein the differential signal input to the two differential inputs of the current shift unit updates data when the difference between the clock signal input to the gate of the fifth fet and the clock signal input to the gate of the sixth fet is positive.

4. The half-cycle delay circuit of claim 3, wherein the first, second, sixth, seventh and eighth fets are P-fets; the third field effect transistor, the fourth field effect transistor, the fifth field effect transistor, the ninth field effect transistor and the tenth field effect transistor are all N-type field effect transistors.