CN102375906B - Pattern matching based FPGA (field-programmable gate array) logic synthesis method - Google Patents
Pattern matching based FPGA (field-programmable gate array) logic synthesis method Download PDFInfo
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Abstract
The invention relates to a pattern matching based FPGA (field-programmable gate array) logic synthesis method, which comprises the following steps of: firstly, generating data structures of modules to be matched according to an RTL (resistor transistor logic) level circuit set by a user; then, loading a predefined sequence module and a predefined combination module for explanation; selecting each module to be matched and corresponding data structure thereof in the RTL level circuit one by one, and judging whether the selected module to be matched is matched with each predefined module; and once the module to be matched is matched with one of the predefined modules, instantiating the predefined module. By using the logic synthesis method provided by the invention, the occupancy amount of on-chip logic resources is smaller, and the time delay for logic implementation is smaller, therefore, the method can be widely used in FPGA logic synthesis.
Description
Technical field
The present invention relates to integrated circuit, relate in particular to the fpga logic integrated approach.
Background technology
In the IC design cycle, logic synthesis is important link in the back end design.Logic synthesis is exactly the basic circuit cell library that provides according to chip manufacturer, and RTL level (Register Transfer Level, the register transfer level) circuit conversion that hardware description language is described is the process of circuit structure model (circuit meshwork list).
Existing logic synthesis process is from ifq circuit figure, through logic analysis, draw the detailed description of circuit, and then carry out logic optimization, the logical expression that obtains simplifying, obtain mapping relations with the side circuit unit by logical mappings, provide circuit analysis based on this mapping relations at last.
FPGA (Field Programmable Gate Array, field programmable gate array) is the product that on programming device bases such as PAL, GAL, CPLD, further develops, occur as a kind of semi-custom circuit in special IC (ASIC) field, FPGA had both overcome the deficiency of custom circuit, had solved the limited shortcoming of original programming device gate circuit number again.
Fig. 1 shows a kind of basic fpga logic unit (logic cell calls LC in the following text), and it comprises look-up table (look-up table, i.e. LUT) and d type flip flop (DFF).4 input LUT are shown having a configuration set storage unit, and totally 16, it can be configured or programme to be used to calculate the combination logic function of any 4 inputs.The output of LUT not only is directly connected to the output of LC, but also sends into the D input end of d type flip flop, and the Q output of d type flip flop can be used as another LC output.In this logical block, can provide MUX (multiplexer, i.e. MUX) and other logic so that allow the Q output terminal of trigger is connected to some input end of LUT.In addition, the output signal of logical block can be routed to the input end of logical block via some general interconnection network, so that make up any given DLC (digital logic circuit).
Improving logical block is the improvement of having done on Fig. 1 basic logic unit basis, and Fig. 2 shows the fpga logic unit after the improvement.For the ease of software modeling, the logical block after this improvement is divided into two kinds, a kind of is combined improvement logical block fc_comb, another kind is the improvement logical block fc_reg of sequential type.Fig. 3 is combined improvement logical block fc_comb synoptic diagram, and Fig. 4 is the improvement logical block fc_reg synoptic diagram of sequential type.
The improvement logical block can realize the quick logical operation between the Different L UT.Combined improvement logical block fc_comb comprises wlut chain (serial chain) and buddy chain (chain in parallel, partner's logic).The modified logical block can intactly be expressed functional characteristic and the Design Mode that meets chip structure, directly user's design map is become to satisfy the structuring net table of modified logical block function by logic synthesis tool, guarantees the optimum of area and performance.Therefore improvement logical block shown in Figure 2 can access better result aspect area and the sequential.
For comprising the fpga chip framework that improves logical block, if adopt existing logic synthesis method that it is carried out logic synthesis, then can not obtain optimum solution, promptly can't generate optimum equivalent logic net table by original fpga logic resource representation.
Summary of the invention
The invention provides a kind of fpga logic integrated approach based on pattern match that can overcome the above problems.
In first aspect, the invention provides a kind of logic synthesis method, this method generates the data structure of module to be matched at first according to the rtl circuit of user's setting; Load predefine tfi module and the explanation of predefine composite module then; Choose among the step a each module to be matched and respective data structures thereof in the rtl circuit more one by one, judge then whether module to be matched that this is chosen and each the predefine module among the step b mate; In case one in this module to be matched and the described predefine module is complementary, this predefine module of exampleization then so that the fpga logic resource after obtaining shining upon, and then is finished the logic synthesis of FPGA.
Further, when judging whether module to be matched and predefine module mate, at first detect the affiliated type of this module to be matched; If this module type to be matched is the combinational logic module, judge then whether this module by signal quantity is consistent with described predefine combinational logic module by signal quantity; If consistent, then continue to judge whether the signal type of this module is consistent with described predefine combinational logic module by signal type, if consistent, judge that then this module and this combinational logic module are complementary.
Further, when judging whether module to be matched and predefine module mate, at first detect the affiliated type of this module to be matched; If when this module type to be matched is the sequential logic module, judge whether this module by signal quantity is consistent with described predefine sequential logic module by signal quantity; If consistent, then continue to judge whether whether the signal type of this module consistent with described predefine sequential logic module by signal type, if consistent, illustrate that then this module and this sequential logic module are complementary.
Further, the predefine tfi module comprise the register (aclr_sload_reg) of supporting asynchronous clear position and set synchronously, one or more in the register (aset_sload_reg) of supporting asynchronous set and set synchronously.
Further, predefine combinational logic module comprise condition adder logic computing (condtional_adder), equate with constant relatively logical operation (cmp_eq), carry out more than or equal to one or more in the multichannel selection computing (lut_mux_lut) between NOR-operation (lut_nor_lut), the look-up table between exclusive disjunction (lut_or_lut), the look-up table between logical operation (cmp_ge) relatively, the look-up table with constant.
Further, in the predefine module is under the condition totalizer situation, logical circuit after the exampleization comprises that multichannel selects a chain and a carry chain (carry chain), and the control signal of this MUX is conditioned signal, and MUX is output as the input of carry chain.Wherein, multichannel selects chain to be made up of a plurality of MUX.
Further, in the predefine module is under the condition totalizer situation, logical circuit after the exampleization comprises a plurality of combined improvement logical blocks (fc_comb), and this combined improvement logical block (fc_comb) obtains by the constant that absorbs in the described condition totalizer.
Further, in the predefine module is under exclusive disjunction between the look-up table (lut_or_lut) situation, logical circuit after the exampleization is partner's logic (buddy chain), and this partner's logic (buddychain) is made of a plurality of combined improvement logical blocks (fc_comb).
The present invention inserts an integration algorithm based on pattern match in the traditional logic combined process, thereby obtains from rtl circuit to the coupling the predefine module.Advantage of the present invention is embodied on the sheet that the logical resource occupancy volume is little, and the logic realization clock delay is little, and the clock frequency height of supporting is low in energy consumption and can reach balance between area and performance.
Description of drawings
Below with reference to accompanying drawings specific embodiments of the present invention is described in detail, in the accompanying drawings:
Fig. 1 is basic fpga logic cellular construction synoptic diagram;
Fig. 2 improves fpga logic cellular construction synoptic diagram;
Fig. 3 is combined improvement logical block synoptic diagram;
Fig. 4 is the improvement logical block synoptic diagram of sequential type;
Fig. 5 is the logic synthesis process flow diagram of one embodiment of the invention;
Fig. 6 is the pattern matching algorithm process flow diagram of one embodiment of the invention;
Fig. 7 is the hardware configuration synoptic diagram of RTL level condition totalizer;
Fig. 8 is the logical circuit synoptic diagram that in the prior art Fig. 7 example is changed into;
Fig. 9 is the logical circuit synoptic diagram after one embodiment of the invention Fig. 7 is shone upon;
Figure 10 is the logical circuit synoptic diagram after another embodiment of the present invention Fig. 7 is shone upon;
Figure 11 is the hardware configuration synoptic diagram of RTL level or operation;
Figure 12 is to the logical circuit synoptic diagram after Figure 11 mapping in the prior art;
Figure 13 is the logical circuit synoptic diagram after one embodiment of the invention Figure 11 is shone upon;
Figure 14 is that synoptic diagram is realized in the inside of Figure 13.
Embodiment
Fig. 5 is the logic synthesis process flow diagram of one embodiment of the invention.
In step 510, this step is the rtl circuit design phase.In this stage, the user describes out it by hardware description language (Verilog, VHDL etc.) and wants to reach function.
In step 520, the rtl circuit in the step 510 is carried out grammer scanning, generative grammar tree ParserTree after grammer scanning, and then establishment and thinning process Elaboration generation internal data structure EDB (Elaborated Database).
Described grammer scanning can be adopted any one conventional grammer scan mode, carries out grammer scanning as the scanning sequence that adopts open source software instruments such as Flex, Flex++, Flexc++ to be generated, with generative grammar tree and internal data structure EDB.
In step 530, the syntax tree that traversal step 520 obtains, and execution pattern coupling integration algorithm (specific algorithm will partly obtain more elaboration by Fig. 6 and respective description thereof).
Whether this pattern match integration algorithm be used to judge between rtl circuit that the user designs and the predefine module and mate, if coupling then this predefine module of exampleization, if would not do not match then execution in step 540.
Described predefine module comprises two big classes, and a class is the predefine logic module of sequential type, and another kind of is combined predefine logic module, is defined as follows:
Sequential type predefine logic module:
r1.aclr_sload_reg
Support the register of asynchronous clear position and set synchronously;
r2.aset_sload_reg
Support the register of asynchronous set and set synchronously;
Combined predefine logic module:
t1.conditional_adder
The condition additive operation;
t2.cmp_eq
Equate logical operation relatively with a constant;
t3.cmp_ge
Carry out more than or equal to logical operation relatively with a constant;
t4.lut_or_lut
Exclusive disjunction between the look-up table, it does ' or ' operation to two outputs that are less than or equal to 4 input look-up tables;
t5.lut_nor_lut
NOR-operation between the look-up table, it does ' or non-' operation to two outputs that are less than or equal to 4 input look-up tables;
t6.lut_mux_lut
Multichannel is selected computing between the look-up table, and it does the multichannel selection operation to two outputs that are less than or equal to 4 input look-up tables;
In step 540, when not matching between the rtl circuit of judging user's design and the predefine module, at first rtl circuit is translated into the internal logic resource, then stratification net table is launched (flatten), actuating logic optimization process again, and the logical network after the optimization process is mapped to the fpga logic resource.
This step 540 be conventional logic synthesis the necessary process of carrying out, concrete grammar can be with reference to the ABC system that increases income in Berkeley branch school, California Institute of Technology.
In step 550, the logic netlist that output is made up of the fpga logic resource, thereby completion logic combined process.
Fig. 6 is the pattern matching algorithm process flow diagram of one embodiment of the invention.
In step 610, the rtl circuit designed according to the user generates the data structure of module to be matched, and this step 610 is step 510,520.Wherein, module to be matched is a module in the designed rtl circuit of user.
In the example, the user by the RTL level condition totalizer of Verilog language design is:
always@(*)begin
if(e)c＝a+1；
else?c＝a+3；
end
Hence one can see that, and when condition e set up, output variable c equaled input variable a and adds constant 1; Otherwise when condition e was false, output variable c equaled input variable a and adds constant 3, and therefore, the data structure of module to be matched is:
Module type: combinational logic
Input signal: a, 1,3
Output signal: c
Control signal: e
……
In step 620, load the predefine module declaration, this predefine module is the described predefine module of preamble, comprise predefine sequential logic module aclr_sload_reg, aset_sload_reg, and predefine combinational logic module condtional_adder, cmp_eq, cmp_ge, lut_or_lut, lut_nor_lut, lut_mux_lut.
In the example, the module declaration of condition addition conditional_adder predefine is:
(*cell＝″COMPARECONST″，param_str＝″width:masks″*)
module?cond_add(A，Y，SEL)；
parameter?width＝0；
parameter?consta＝64′b0；
parameter?constb＝64′b0；
input[width-1:0]A；
input?SEL；
output[width-1:0]Y；
...The concrete module of omitting/* realize */
endmodule
In step 630, travel through a module to be matched, promptly choose each module in the rtl circuit and the data structure of corresponding module one by one.
In step 640, detect the type of module to be matched that step 630 is chosen, if this type of module is a combinational logic, then continue execution in step 651, if this type of module is a sequential logic, then continue execution in step 661.
In step 651, judge whether combinational logic module by signal quantity to be matched and predefine combinational logic module by signal quantity mate, promptly the combinational logic module by signal quantity of comparison step 640 is consistent with which or which predefine combinational logic module (comprising conditional_adder, cmp_eq, cmp_ge, lut_or_lut, lut_nor_lut, lut_mux_lut) number of signals.
If the combinational logic module by signal quantity that this is to be matched and each predefine combinational logic module by signal quantity are all inconsistent, then return step 630, promptly get next module to be matched, and continue it is carried out The matching analysis; If this combinational logic module by signal quantity to be matched consistent with certain or some predefine combinational logic module by signal quantity (as with conditional_adder number of signals unanimity), then continue execution in step 652.
In step 652, judge in the signal type of this module to be matched and the step 651 whether mated by predefine combinational logic module (as the conditional_adder) signal type of matched signal quantity.
That is to say, if this predefine combinational logic module comprises input signal, output signal, control signal, then step 652 relatively this module to be matched whether also comprise input signal, output signal and control signal.
If step 652 judges that the signal type of predefine combinational logic module in the signal type of this module to be matched and the step 651 is inconsistent, then return step 630, promptly get next module to be matched, and continue it is carried out The matching analysis; If consistent, then continue execution in step 653.
In step 653, according to the optimization aim that the user sets, select the predefine combinational logic module that is complementary with this module to be matched, wherein, this optimization aim comprises that area is preferential, performance is preferential, power consumption is preferential and area performance balance etc.
This step 653 is better embodiment, when the signal type of the signal type of module to be matched in the step 652 and a plurality of predefine combinational logic modules all obtains mating, just understand execution in step 653, to obtain the needed predefine combinational logic of user module.
In step 661, judge whether mate from the sequential logic module by signal quantity to be matched and the predefine sequential logic module by signal quantity of step 640.
If the sequential logic module by signal quantity that this is to be matched and each predefine sequential logic module by signal quantity are all inconsistent, then return step 630; If this sequential logic module by signal quantity to be matched is consistent with certain or some predefine sequential logic module by signal quantity, then continue execution in step 662.
In step 662, judge in the signal type of this module to be matched and the step 661 whether mated by the signal type of the predefine sequential logic module of matched signal quantity.If judge that the signal type of the signal type of this module to be matched and this predefine sequential logic module is inconsistent, then return step 630; If consistent, then continue execution in step 663.
In step 663, according to the optimization aim that the user sets, select the predefine sequential logic module that is complementary with this module to be matched, wherein, this optimization aim comprises that area is preferential, performance is preferential, power consumption is preferential and area performance balance etc.
In step 670, the predefine module that exampleization has been mated (comprising predefine sequential logic module and predefine combinational logic module), connect the signal such as input signal, output signal, control signal of this predefine module of having been mated, calculate each parameter value in this predefine module of having been mated.
Be that conditional_adder (condition totalizer) is an example with the predefine module of having been mated below, how set forth this predefine module of exampleization.
Fig. 7 is the hardware configuration synoptic diagram of RTL level condition totalizer, and this hardware structure diagram is a kind of hardware structure diagram of usual terms totalizer, and it represents that output variable c equals input variable a and adds constant 1 when condition e sets up; When condition e was false, output variable c equaled input variable a and adds constant 3.
If adopt the common process mapping algorithm, the condition totalizer among Fig. 7 can be changed into logical circuit shown in Figure 8 by example.Fig. 8 is the logical circuit synoptic diagram that in the prior art Fig. 7 example is changed into, and this logical circuit comprises two carry chain (carry chain) and a multichannel selection chain.Wherein, a carry chain comprises ADD13, ADD12, ADD11, ADD10, and another carry chain comprises ADD03, ADD02, ADD01, ADD00; And this multichannel selects chain to be made of 4 MUX MUX, and each MUX MUX all selects the result according to the value of signal E.As seen from Figure 8, each logical device all needs to take one 4 input look-up table fc_comb (combined improvement logical block), and then needs 12 fc_comb (combined improvement logical block) altogether.
Fig. 9 is the logical circuit synoptic diagram that Fig. 7 example is changed into of one embodiment of the invention.Fig. 9 is on Fig. 8 basis, two carry chain among Fig. 8 merged, and selects the selecting side of chain to be advanced to this merging input end of carry chain afterwards multichannel, and the simplification logical circuit that obtains.Among Fig. 9, this logical circuit comprises a multichannel selection chain and a carry chain; Wherein, this multichannel selects chain to be made up of 4 MUX MUX; This carry chain is merged by two carry chains among Fig. 8.
As seen from Figure 9, this logical circuit only needs 8 fc_comb, therefore Fig. 7 example is changed into Fig. 9, for example changes into Fig. 8 (needing 12 fc_comb), has saved hardware resource.
Further, Fig. 9 logical circuit is absorbed constant handle, thereby obtain logical circuit shown in Figure 10.Figure 10 is the logical circuit synoptic diagram after another embodiment of the present invention Fig. 7 is shone upon.
Particularly, because the characteristics of LUT are, the mask value by its inside realizes importing the logical relation that number is not more than N arbitrarily, so when constant occurring in the circuit, can be with constant absorption to mask inside.In addition, because modified LUT supports the input number to be not more than any logic of 4, and constant unit appearred in Fig. 9 circuit, therefore can carry out constant absorption to Fig. 9 circuit.Therefore as seen from Figure 10, this logical circuit only needs 4 fc_comb, has significantly reduced hardware resource with respect to Fig. 9, and the degree of depth of this logical circuit also reduced to minimum number of layers (1 layer), and this means that also the circuit clock time-delay further obtains shortening.
Be example with the predefine module lut_or_lut (exclusive disjunction between the look-up table) that has been mated below, how set forth this predefine module of exampleization.
Lut_or_lut (exclusive disjunction between the look-up table) is meant do ' or ' operation between 2 LUT output.
Figure 11 is the hardware configuration synoptic diagram of RTL level or operation, this circuit be input as a[3..0] and b[3..0], be output as (a[3] ﹠a[2] ﹠a[1] ﹠a[0]) | (b[3] ﹠b[2] ﹠b[1] ﹠b[0]).
Figure 12 be in the prior art to the logical circuit synoptic diagram after Figure 11 mapping, this logical circuit comprises 3 fc_comb.
Figure 13 is the logical circuit synoptic diagram after one embodiment of the invention Figure 11 is shone upon.Because buddy chain has an internal logic resource, therefore can on Figure 12 basis, adopt the buddychain structure and then obtain logical circuit shown in Figure 13.As shown in Figure 13, adopt logical circuit shown in Figure 13 only to need 2 fc_comb, therefore Figure 11 is mapped to Figure 13 for being mapped to Figure 12, saved hardware resource, and the degree of depth of logical circuit has also reduced to minimum number of layers (1 layer), and this means that also the circuit clock time-delay further obtains shortening.
Figure 14 is that synoptic diagram is realized in the inside of Figure 13, the structure of Fc_comb among the inner structure of Figure 13, especially Figure 13 as seen from Figure 14, with and the implementation of input and output.
Obviously, under the prerequisite that does not depart from true spirit of the present invention and scope, the present invention described here can have many variations.Therefore, the change that all it will be apparent to those skilled in the art that all should be included within the scope that these claims contain.The present invention's scope required for protection is only limited by described claims.
Claims (10)
1. a logic synthesis method is characterized in that, comprising:
Step a according to the rtl circuit that the user sets, generates the data structure of module to be matched;
Step b loads predefine tfi module and the explanation of predefine composite module;
Step c chooses among the step a each module to be matched and respective data structures thereof in the rtl circuit one by one, judges then whether module to be matched that this is chosen and each the predefine module among the step b mate;
Steps d, in case in this module to be matched and the described predefine module is complementary, this predefine module of exampleization then so that the fpga logic resource after obtaining shining upon, and then is finished the logic synthesis of FPGA;
Judge described in the step c that the step whether module to be matched and predefine module mate comprises:
Step e detects the affiliated type of this module to be matched;
Step f if this module type to be matched is the combinational logic module, judges then whether this module by signal quantity is consistent with described predefine combinational logic module by signal quantity; If consistent, then continue to judge whether the signal type of this module is consistent with described predefine combinational logic module by signal type, if consistent, judge that then this module and this combinational logic module are complementary;
Judge described in the step c that the step whether module to be matched and predefine module mate comprises:
Step g detects the affiliated type of this module to be matched;
Step h when being the sequential logic module as if this module type to be matched, judges whether this module by signal quantity is consistent with described predefine sequential logic module by signal quantity; If consistent, then continue to judge whether whether the signal type of this module consistent with described predefine sequential logic module by signal type, if consistent, illustrate that then this module and this sequential logic module are complementary.
2. a kind of logic synthesis method as claimed in claim 1, it is characterized in that, described and all unmatched module of each predefine module for step c, at first this module is translated into the internal logic resource, then stratification net table is launched, actuating logic optimization process again, and then the logical network after the optimization process is mapped to the fpga logic resource.
3. a kind of logic synthesis method as claimed in claim 1 or 2 is characterized in that, comprises the step of the logic netlist that output is made up of the fpga logic resource after steps d.
4. a kind of logic synthesis method as claimed in claim 1 is characterized in that, also comprises after step f and after step h:
Step k according to the optimization aim that the user sets, selects the predefine combination or the sequential logic module that are complementary with this module to be matched; Wherein, described optimization aim comprise that area is preferential, performance is preferential, power consumption is preferential and the area performance balance in one or more.
5. a kind of logic synthesis method as claimed in claim 1, it is characterized in that one or more in the register (aset_sload_reg) that described predefine tfi module comprises the register (aclr_sload_reg) of supporting asynchronous clear position and set synchronously, support asynchronous set and set synchronously.
6. a kind of logic synthesis method as claimed in claim 1, it is characterized in that described predefine combinational logic module comprises condition adder logic computing (condtional_adder), equate logical operation (cmp_eq) relatively with constant, carry out more than or equal to one or more in the multichannel selection computing (lut_mux_lut) between NOR-operation (lut-nor_lut), the look-up table between exclusive disjunction (lut_or_lut), the look-up table between logical operation (cmp_ge) relatively, the look-up table with constant.
7. a kind of logic synthesis method as claimed in claim 1 is characterized in that, comprises after the steps d:
Step t connects one or more in the input signal, output signal, control signal of the predefine module after the described exampleization, and calculates each parameter value in this module.
8. a kind of logic synthesis method as claimed in claim 1 is characterized in that, the described predefine module of steps d is the condition totalizer, and the logical circuit after the exampleization comprises a multichannel selection chain and a carry chain (carry chain); Wherein, this multichannel selects chain to be made up of a plurality of MUX;
And the control signal of described MUX is a conditioned signal, and MUX is output as the input of described carry chain.
9. a kind of logic synthesis method as claimed in claim 1, it is characterized in that, the described predefine module of steps d is the condition totalizer, logical circuit after the exampleization comprises a plurality of combined improvement logical blocks (fc_comb), and this combined improvement logical block (fc_comb) obtains by the constant that absorbs in the described condition totalizer.
10. a kind of logic synthesis method as claimed in claim 1, it is characterized in that, the described predefine module of steps d is exclusive disjunction between the look-up table (lut_or_lut), logical circuit after the exampleization is partner's logic (buddy chain), and this partner's logic (buddy chain) is made of a plurality of combined improvement logical blocks (fc_comb).
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| CN105589981B (en) * | 2014-10-22 | 2019-04-09 | 京微雅格（北京）科技有限公司 | The process mapping method of the adder of optimization layout structure based on FPGA |
| US9584128B2 (en) * | 2014-12-11 | 2017-02-28 | Capital Microelectronics Co., Ltd. | Structure of multi-mode supported and configurable six-input LUT, and FPGA device |
| CN106649905B (en) * | 2015-11-04 | 2023-04-07 | 京微雅格（北京）科技有限公司 | Process mapping method using carry chain |
| CN110457868B (en) * | 2019-10-14 | 2020-01-21 | 广东高云半导体科技股份有限公司 | Optimization method, device and system for FPGA (field programmable Gate array) logic synthesis |
| CN113283203A (en) * | 2021-07-21 | 2021-08-20 | 芯华章科技股份有限公司 | Method, electronic device and storage medium for simulating logic system design |
| CN115577662B (en) * | 2022-11-23 | 2023-03-10 | 山东启芯软件科技有限公司 | Sequential device resource optimization method based on multi-fanout logic |
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| CN1641651A (en) * | 1999-12-14 | 2005-07-20 | 爱特梅尔股份有限公司 | Method for implementing physical design for dynamically reconfigurable logic circuit |
| CN1786968A (en) * | 2005-12-08 | 2006-06-14 | 复旦大学 | FPGA logic unit functional model and universal logic unit containing computing method |
| EP1708109A1 (en) * | 2005-04-01 | 2006-10-04 | Altera Corporation | Methods for producing equivalent field-programmable gate arrays and structured application-specific integrated circuits |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1641651A (en) * | 1999-12-14 | 2005-07-20 | 爱特梅尔股份有限公司 | Method for implementing physical design for dynamically reconfigurable logic circuit |
| EP1708109A1 (en) * | 2005-04-01 | 2006-10-04 | Altera Corporation | Methods for producing equivalent field-programmable gate arrays and structured application-specific integrated circuits |
| CN1786968A (en) * | 2005-12-08 | 2006-06-14 | 复旦大学 | FPGA logic unit functional model and universal logic unit containing computing method |
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