CN105069227A - Method for establishing functional verification platform on the basis of Wishbone bus design - Google Patents
Method for establishing functional verification platform on the basis of Wishbone bus design Download PDFInfo
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- CN105069227A CN105069227A CN201510482827.5A CN201510482827A CN105069227A CN 105069227 A CN105069227 A CN 105069227A CN 201510482827 A CN201510482827 A CN 201510482827A CN 105069227 A CN105069227 A CN 105069227A
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Abstract
The invention relates to the technical field of integrated circuit design verification, particularly relates to the design of a verification method and a verification platform of an internal register and an RAM (Random Access Memory) module on the basis of Wishbone bus design, and specifically relates to a method for establishing a functional verification platform on the basis of the Wishbone bus design. The method comprises the following steps: firstly, according to the parameters of the tested internal register and the tested RAM module, establishing a register information document; then, designing an automatic script, using the automatic script to generate a test vector according to the register information document, and carrying out corresponding regulation in the test vector if a relevant register has a special data processing process; then, designing an output information control script of the verification platform and an operation script of the verification platform; and finally, debugging to operate the test vector to finish a verification process. The verification platform established through the method can finish testing the register and the RAM module in the design on the basis of a Wishbone bus, has the characteristics of being short in development period, high in universality and high in automation degree and can greatly improve chip verification efficiency.
Description
Technical field
Patent of the present invention relates to verifying design of integrated circuit technical field, especially relate to based on the internal register of Wishbone bus design and the verification method of RAM module and Design for Verification Platform, specifically relate to a kind of building method of the functional verification platform based on WISHBONE bus design.
Background technology
At present, ic manufacturing technology is progress rapidly, and the demand of market to high integration product constantly increases simultaneously, causes the complexity of integrated circuit exponentially to increase.Along with the increase of IC complexity, validation difficulty increases with higher speed.Therefore, improve the fulfillment capability of checking work, become the Focal point and difficult point of large scale integrated circuit exploitation.
On the other hand, because the advantage such as open, easy-to-use of Wishbone bus, design based on Wishbone bus is very many, and is that each design based on Wishbone bus needs exploitation verification platform to be used for carrying out emulation testing to the register and ram module that design inside.
At present, for the verification platform of integrated circuit, there is checking flow process complicated, implement inconvenience, proof procedure is stable not, the weak point that verification efficiency is low more.
Summary of the invention
In order to solve the problem of prior art, the invention provides a kind of building method of the functional verification platform based on WISHBONE bus design, it uses automatized script to control document automation according to internal register and RAM module information document, chip initiation and completes test vector generation and operation, the method is implemented convenient, flow process is simple, efficient stable, significantly can shorten to the construction cycle that functional verification platform is built in the different designs based on Wishbone bus, improve functional verification efficiency.
The technical solution adopted in the present invention is as follows:
Based on a building method for the functional verification platform of WISHBONE bus design, comprising:
Control document for the internal register of current tested design and RAM module information document and chip initiation, use multiple automatized script to complete generation, the operation and control of validation test vector;
Wherein, described internal register and RAM module information document complete according to the design based on Wishbone bus and write; Described chip initiation control document completes according to the initial work flow process of the design based on Wishbone bus to be write; Described each automatized script comprises test vector generation script, output information controls script and Run Script.
Internal register and RAM module conduct interviews by using Wishbone bus.
Information document comprises address, data width, the degree of depth, reading/writing characteristics, the read write command delay of internal register and RAM module and reads and writes associated order information.
Automatized script uses perl or tcl or c-shell scripting language.
Test vector generation script is by reading internal register and the RAM module information document structure tree specific test vector for each register and RAM module.
Output information controls script by reserved control port, and the convenient classification carrying out output information in test process according to actual needs controls.
Run Script controls document according to chip initiation and automatically generates the initial environment configuration order for the design based on Wishbone bus and perform, and performs test vector afterwards, completes test process and generate test report.
The beneficial effect that technical scheme provided by the invention is brought is:
By using automatized script, realizing robotization and completing building of verification platform and operation work; By the order of measured Wishbone bus protocol design verification platform test, realize the general readwrite tests to each design based on Wishbone bus; The correct test for particular memory module is realized by use internal register and ram module information document; The configuration of document realization to the initial authentication environment of different designs is controlled by using chip initiation.The method is implemented convenient, and flow process is simple, and efficient stable, significantly can shorten to the construction cycle that functional verification platform is built in the different designs based on Wishbone bus, improves functional verification efficiency.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the method flow diagram of the building method of a kind of functional verification platform based on WISHBONE bus design of the present invention.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, embodiment of the present invention is described further in detail.
Embodiment one
As shown in Figure 1, the verification platform of the present embodiment is built flow process and is comprised the following steps:
A, basis, based on the initial work process of the design of Wishbone bus, comprise the stable clock signal time, the reset signal enable time, the timely sequence of inner each Special controlling signal list, and design chips initialization controls document;
B, basis are based on the design internal register of Wishbone bus and address, data width, the degree of depth, reading/writing characteristics, the read write command delay of ARM module and read and write associated order information, write information document;
C, write automatized script, comprise test vector generation script, output information controls script and Run Script, needs the read write command template base of writing protocol compliant timing requirements according to Wishbone agreement simultaneously;
Above-mentioned automatized script and command module storehouse be all can carry out in the design of difference based on Wishbone bus multiplexing.
D, use test vector generation script, for based on the design internal register of Wishbone bus and the information document of RAM module, generate the selected register that will test or the test vector of RAM module;
E, the control port using output information control script reserved, arrange the information category that current test needs to output to log file;
F, the initialization command sequence using Run Script corresponding according to the chip initiation control document structure tree of design, perform, testing results vector, generates test report, completes this test process afterwards.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1., based on a building method for the functional verification platform of WISHBONE bus design, comprising:
Control document for the internal register of current tested design and RAM module information document and chip initiation, use multiple automatized script to complete generation, the operation and control of validation test vector;
Wherein, described internal register and RAM module information document complete according to the design based on Wishbone bus and write; Described chip initiation control document completes according to the initial work flow process of the design based on Wishbone bus to be write; Described each automatized script comprises test vector generation script, output information controls script and Run Script.
2. the building method of a kind of functional verification platform based on WISHBONE bus design according to claim 1, is characterized in that, described internal register and RAM module conduct interviews by using Wishbone bus.
3. the building method of a kind of functional verification platform based on WISHBONE bus design according to claim 1, it is characterized in that, described information document comprises address, data width, the degree of depth, reading/writing characteristics, the read write command delay of internal register and RAM module and reads and writes associated order information.
4. the building method of a kind of functional verification platform based on WISHBONE bus design according to claim 1, is characterized in that, described automatized script uses perl or tcl or c-shell scripting language.
5. the building method of a kind of functional verification platform based on WISHBONE bus design according to claim 1, it is characterized in that, described test vector generation script is by reading internal register and the RAM module information document structure tree specific test vector for each register and RAM module.
6. the building method of a kind of functional verification platform based on WISHBONE bus design according to claim 1, it is characterized in that, described output information controls script by reserved control port, and the convenient classification carrying out output information in test process according to actual needs controls.
7. the building method of a kind of functional verification platform based on WISHBONE bus design according to claim 1, it is characterized in that, described Run Script controls document according to chip initiation and automatically generates the initial environment configuration order for the design based on Wishbone bus and perform, perform test vector afterwards, complete test process and generate test report.
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| CN105354121A (en) * | 2015-11-20 | 2016-02-24 | 浪潮集团有限公司 | Establishment method of verification platform used for verifying memory modules of various read-write modes |
| CN105956219A (en) * | 2016-04-18 | 2016-09-21 | 浪潮集团有限公司 | Functional verification method for neural network based design |
| CN106845004A (en) * | 2017-02-15 | 2017-06-13 | 济南浪潮高新科技投资发展有限公司 | It is a kind of that system and method is built based on script for functional verification platform |
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| CN107943644A (en) * | 2017-11-22 | 2018-04-20 | 济南浪潮高新科技投资发展有限公司 | A kind of building method of functional verification platform for the design based on LOCAL BUS buses |
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| CN105354121A (en) * | 2015-11-20 | 2016-02-24 | 浪潮集团有限公司 | Establishment method of verification platform used for verifying memory modules of various read-write modes |
| CN105956219A (en) * | 2016-04-18 | 2016-09-21 | 浪潮集团有限公司 | Functional verification method for neural network based design |
| CN106845004A (en) * | 2017-02-15 | 2017-06-13 | 济南浪潮高新科技投资发展有限公司 | It is a kind of that system and method is built based on script for functional verification platform |
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| CN107943644A (en) * | 2017-11-22 | 2018-04-20 | 济南浪潮高新科技投资发展有限公司 | A kind of building method of functional verification platform for the design based on LOCAL BUS buses |
| CN109446677A (en) * | 2018-11-02 | 2019-03-08 | 南京贝伦思网络科技股份有限公司 | General-purpose platform and its building method based on network chip |
| CN109446677B (en) * | 2018-11-02 | 2023-07-14 | 南京贝伦思网络科技股份有限公司 | Universal platform based on network chip and construction method thereof |
| TWI819764B (en) * | 2022-08-25 | 2023-10-21 | 大陸商北京歐錸德微電子技術有限公司 | Project management tracking visualization method and integrated circuit design verification system |
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