CN105069227A - Method for building function verification platform based on WISHBONE bus design - Google Patents

Abstract

The present invention relates to the technical field of integrated circuit design verification, in particular to a verification method and verification platform design for internal registers and RAM modules based on Wishbone bus design, and in particular to a method for building a function verification platform based on WISHBONE bus design. This method first establishes the register information file according to the parameters of the internal register and ram module under test; then, an automatic script is designed, and the test vector is generated according to the register information file with the automatic script. If the relevant register has a special data processing process, the test vector Then, design the output information control script of the verification platform and the operation script of the verification platform; finally, debug and run the test vector to complete the verification process. The verification platform built by this method can complete the test of the register and ram module in the design based on the Wishbone bus. It has the characteristics of short development cycle, strong versatility and high degree of automation, and can greatly improve the efficiency of chip verification.

Description

A method of building a functional verification platform based on WISHBONE bus design

technical field

The patent of the present invention relates to the technical field of integrated circuit design verification, especially relates to the verification method and verification platform design of internal registers and RAM modules based on the Wishbone bus design, and specifically relates to a method of building a functional verification platform based on the WISHBONE bus design.

Background technique

At present, the rapid progress of integrated circuit manufacturing technology and the increasing market demand for highly integrated products have led to an exponential increase in the complexity of integrated circuits. As the complexity of integrated circuits increases, the difficulty of verification increases at a higher rate. Therefore, improving the realization ability of the verification work has become the focus and difficulty of the development of large-scale integrated circuits.

On the other hand, because of the openness and ease of use of the Wishbone bus, there are many designs based on the Wishbone bus. For each design based on the Wishbone bus, a verification platform needs to be developed to simulate the internal registers and ram modules of the design. test.

At present, most of the verification platforms for integrated circuits have the disadvantages of complex verification process, inconvenient implementation, unstable verification process, and low verification efficiency.

Contents of the invention

In order to solve the problems of the prior art, the present invention provides a method for building a functional verification platform based on the WISHBONE bus design, which uses automated scripts to automatically complete the generation and operation of test vectors according to internal registers and RAM module information files, chip initialization control files , the method is easy to implement, has a simple process, is efficient and stable, can greatly shorten the development cycle of building a functional verification platform for different designs based on the Wishbone bus, and improves the efficiency of functional verification.

The technical scheme adopted in the present invention is as follows:

A method for building a functional verification platform based on WISHBONE bus design, including:

For the internal register and RAM module information documents and chip initialization control documents of the current design under test, use a variety of automated scripts to complete the generation, operation and control of verification test vectors;

Wherein, the internal register and RAM module information documents are written according to the design based on the Wishbone bus; the chip initialization control document is written according to the initialization workflow based on the Wishbone bus design; each of the automated scripts includes test vector generation Scripts, Output Information Control Scripts, and Run Scripts.

Internal registers and RAM blocks are accessed using the Wishbone bus.

The information file contains the address, data width, depth, read and write characteristics, read and write command delay, and read and write related sequence information of internal registers and RAM modules.

Automation scripts are written in perl or tcl or c-shell scripting language.

The test vector generation script generates specific test vectors for each register and RAM module by reading the internal register and RAM module information files.

The output information control script reserves the control port to facilitate the classification control of the output information during the test process according to the actual needs.

The running script automatically generates and executes the initial environment configuration commands for the Wishbone bus-based design according to the chip initialization control document, and then executes the test vector to complete the test process and generate a test report.

The beneficial effects brought by the technical scheme provided by the invention are:

Through the use of automated scripts, the construction and operation of the verification platform can be automatically completed; through the design of the verification platform test commands based on the standard Wishbone bus protocol, the general read and write test of each design based on the Wishbone bus can be realized; through the use of internal registers and ram modules Information files enable correct testing for specific memory modules; configuration of initial verification environments for different designs is enabled by using chip initialization control files. The method is easy to implement, has a simple process, is efficient and stable, can greatly shorten the development cycle of building a functional verification platform for different Wishbone bus-based designs, and improves the efficiency of functional verification.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.

Fig. 1 is a method flowchart of a method for building a function verification platform based on WISHBONE bus design according to the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the implementation manner of the present invention will be further described in detail below in conjunction with the accompanying drawings.

Embodiment one

As shown in Figure 1, the verification platform construction process of this embodiment includes the following steps:

A. According to the initialization work process based on the Wishbone bus design, including clock signal stabilization time, reset signal enable time, internal special control signal list and timing, design chip initialization control documents;

B. According to the address, data width, depth, read and write characteristics, read and write command delay and read and write related sequence information of the designed internal registers and ARM modules based on the Wishbone bus, write information documents;

C. Write automated scripts, including test vector generation scripts, output information control scripts and running scripts. At the same time, it is necessary to write a read and write command template library that meets the protocol timing requirements according to the Wishbone protocol;

The above automation scripts and command module libraries can be reused in different Wishbone bus-based designs.

D. Use the test vector generation script to generate the test vectors of the selected registers or RAM modules to be tested for the information files of the internal registers and RAM modules based on the Wishbone bus;

E. Use the control port reserved by the output information control script to set the information category that needs to be output to the log file for the current test;

F. Use the running script to generate the corresponding initialization command sequence according to the designed chip initialization control document, execute it, and then run the test vector, generate a test report, and complete the test process.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within range.

Claims (7)

1., based on a building method for the functional verification platform of WISHBONE bus design, comprising:

Control document for the internal register of current tested design and RAM module information document and chip initiation, use multiple automatized script to complete generation, the operation and control of validation test vector;

Wherein, described internal register and RAM module information document complete according to the design based on Wishbone bus and write; Described chip initiation control document completes according to the initial work flow process of the design based on Wishbone bus to be write; Described each automatized script comprises test vector generation script, output information controls script and Run Script.

2. the building method of a kind of functional verification platform based on WISHBONE bus design according to claim 1, is characterized in that, described internal register and RAM module conduct interviews by using Wishbone bus.

3. the building method of a kind of functional verification platform based on WISHBONE bus design according to claim 1, it is characterized in that, described information document comprises address, data width, the degree of depth, reading/writing characteristics, the read write command delay of internal register and RAM module and reads and writes associated order information.

4. the building method of a kind of functional verification platform based on WISHBONE bus design according to claim 1, is characterized in that, described automatized script uses perl or tcl or c-shell scripting language.

5. the building method of a kind of functional verification platform based on WISHBONE bus design according to claim 1, it is characterized in that, described test vector generation script is by reading internal register and the RAM module information document structure tree specific test vector for each register and RAM module.

6. the building method of a kind of functional verification platform based on WISHBONE bus design according to claim 1, it is characterized in that, described output information controls script by reserved control port, and the convenient classification carrying out output information in test process according to actual needs controls.

7. the building method of a kind of functional verification platform based on WISHBONE bus design according to claim 1, it is characterized in that, described Run Script controls document according to chip initiation and automatically generates the initial environment configuration order for the design based on Wishbone bus and perform, perform test vector afterwards, complete test process and generate test report.