CN107168843A - A kind of building method of the functional verification platform based on AXI buses - Google Patents
A kind of building method of the functional verification platform based on AXI buses Download PDFInfo
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- CN107168843A CN107168843A CN201710431840.7A CN201710431840A CN107168843A CN 107168843 A CN107168843 A CN 107168843A CN 201710431840 A CN201710431840 A CN 201710431840A CN 107168843 A CN107168843 A CN 107168843A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
Abstract
The present invention discloses a kind of building method of the functional verification platform based on AXI buses, is related to IC design verifications field；According to the initial work process of tested AXI bus architectures, chip initiation control document is write；According to tested AXI bus architectures, the parameter information of bus architecture is determined, bus architecture information document is write；Set up verification platform bus arbiter module model and generate script, read bus architecture information document, generate bus arbiter module model top document；Register information document is set up according to the parameter of tested AXI bus architectures internal register and ram modules, and generates automatic script, with the automatic script according to register information document structure tree test vector；The output information control script of verification platform and the Run Script of verification platform are generated, commissioning test test vector carries out the verification process of functional verification platform.
Description
Technical field
The present invention discloses a kind of building method of the functional verification platform based on AXI buses, is related to IC design verifications field.
Background technology
AXI full name Advanced eXtensible Interface, are the microcontroller bus men that ARM is proposed for 1996
A part in race AMBA.AXI first version appears in AMBA3.0 and is published on 2003, and AXI4.0 is published on 2010,
Xilinx is introduced since the FPGA of 6 series, essentially describes the data transfer mode between main equipment and slave unit.Because
AXI bus architectures are flexible, it is easy-to-use the advantages of, the design based on AXI buses is very more, and the main supplier of in the market includes
Altera, Xilinx etc..And each design based on AXI buses is required for one verification platform of exploitation to be used for design inside
Register and ram modules carry out emulation testing, with ensure design AXI buses validity.But based on the product of AXI buses
Too much, it is so not only cumbersome, increase cost, and waste limited resources.
The present invention provides a kind of building method of the functional verification platform based on AXI buses, for the rule of AXI bus protocols
Drawing property, describes the building method of the functional verification platform for testing the product based on AXI buses, by using automation pin
This controls document, automation according to bus architecture information document, internal register and ram module informations document, chip initiation
Complete test vector generation and operation.And the inventive method is easy to implement, flow is simple, and efficient stable can significantly shorten
Design based on AXI buses is built the construction cycle of functional verification platform, improves functional verification efficiency.
The content of the invention
The present invention provides a kind of building method of the functional verification platform based on AXI buses, with highly versatile, implements letter
Just the features such as, have broad application prospects.
Concrete scheme proposed by the present invention is：
A kind of building method of the functional verification platform based on AXI buses：
According to the initial work process of tested AXI bus architectures, chip initiation control document is write；
According to tested AXI bus architectures, the parameter information of bus architecture is determined, bus architecture information document is write；
Set up verification platform bus arbiter module model and generate script, read bus architecture information document, generate bus arbitration
Modular model top document；
Register information document is set up according to the parameter of tested AXI bus architectures internal register and ram modules, and generated automatic
Script, with the automatic script according to register information document structure tree test vector；
The output information control script of verification platform and the Run Script of verification platform are generated, commissioning test test vector is carried out
The verification process of functional verification platform.
According to the stable clock signal time during the initial work of tested AXI bus architectures, reset signals are enabled
Time, internal each timely sequence information of Special controlling signal list writes chip initiation control document.
The initial environment that the Run Script controls document to automatically generate for AXI bus architectures according to chip initiation is matched somebody with somebody
Put order and perform, test vector is performed afterwards, carry out test checking and generate test report.
The bus architecture information document includes the quantity of master-slave equipment in tested AXI bus architecture types, bus architecture
And its device id, the device id that the axi_interconnect_1 IP kernels quantity and name used and each IP kernel are arbitrated.
Address of the register information document comprising internal register and ram modules, data width, depth, read-write are special
Levy, read write command postpones and read-write associated order information.
The output information control script is exported according to actual needs by reserving control port in test process
The classification control of information.
Usefulness of the present invention is：
The present invention proposes a kind of building method of the functional verification platform based on AXI buses, by using chip initiation control
Document processed realizes the configuration to the initial authentication environment of different designs, by using internal register and ram module information documents
Realization is tested for memory module；By using automatized script, realization automatically completes building and transporting for verification platform
Row work；It can be realized by measured AXI bus protocols design verification platform test order to being respectively based on AXI buses
Design general readwrite tests；The inventive method understands that verification platform does not have language threshold for designer, is easy to design
Personnel are exchanged with checking personnel, and easy to implement, and flow is simple, and efficient stable can significantly shorten to different bases
Built the construction cycle of functional verification platform in the design of AXI buses, improve functional verification efficiency.
Brief description of the drawings
Fig. 1 the inventive method schematic flow sheets.
Embodiment
The present invention provides a kind of building method of the functional verification platform based on AXI buses：
According to the initial work process of tested AXI bus architectures, chip initiation control document is write；
According to tested AXI bus architectures, the parameter information of bus architecture is determined, bus architecture information document is write；
Set up verification platform bus arbiter module model and generate script, read bus architecture information document, generate bus arbitration
Modular model top document；
Register information document is set up according to the parameter of tested AXI bus architectures internal register and ram modules, and generated automatic
Script, with the automatic script according to register information document structure tree test vector；
The output information control script of verification platform and the Run Script of verification platform are generated, commissioning test test vector is carried out
The verification process of functional verification platform.
The present invention is further described with reference to accompanying drawing.It is using the detailed process of the inventive method：
First, according to the initial work process of the design of tested AXI buses, including stable clock signal time, reset signals
Enable time, the information such as internal each timely sequence of Special controlling signal list writes chip initiation control document；
Bus architecture information document is write according to tested AXI bus architectures type, it is total that bus architecture information document includes tested AXI
The quantity and its device id of master-slave equipment in line architecture type, bus architecture, the axi_interconnect_1 IP kernel numbers used
Amount and name and the device id of each IP kernel arbitration；
According to the address of the design internal register of tested AXI buses and ram modules, data width, depth, reading/writing characteristics, reading
Write order postpones and read-write associated order information, writes register information document；
Write automatized script, including bus arbitration model top document generation script, test vector generation script, output information
Script and Run Script are controlled, while the read write command ATL for meeting AXI protocol timing requirements can be write as needed；On
Stating automatized script and command module storehouse can be multiplexed being Bu Tong tested in the design of AXI buses；
Script is generated by reading the total of bus architecture information document generation checking needs using bus arbitration model top document
Line arbitration model top document；
It is raw using test vector generation script for design internal register and the information document of ram modules based on AXI buses
Into the test vector of the selected register to be tested or ram modules；
The reserved control port of script is controlled using output information, sets current test to need to be output to the information of log files
Classification；
The corresponding initialization command sequence of document structure tree is controlled according to chip initiation using Run Script, performs, runs afterwards
Test vector, generates test report, completes this test.
Script in above-mentioned functions verification platform can use the scripting languages such as perl/tcl/c-shell.
According to tested design needs, the functional verification platform of different type of architecture is generated using present invention automation.Pass through
The verification platform that the inventive method is built can complete register in the design based on AXI buses of a variety of type of architecture and
The test of ram modules, with the construction cycle is short, highly versatile and the characteristics of high automaticity, can increase substantially chip
Verification efficiency.
Claims (6)
1. a kind of building method of the functional verification platform based on AXI buses, it is characterized in that
According to the initial work process of tested AXI bus architectures, chip initiation control document is write；
According to tested AXI bus architectures, the parameter information of bus architecture is determined, bus architecture information document is write；
Set up verification platform bus arbiter module model and generate script, read bus architecture information document, generate bus arbitration
Modular model top document；
Register information document is set up according to the parameter of tested AXI bus architectures internal register and ram modules, and generated automatic
Script, with the automatic script according to register information document structure tree test vector；
The output information control script of verification platform and the Run Script of verification platform are generated, commissioning test test vector is carried out
The verification process of functional verification platform.
2. according to the method described in claim 1, it is characterized in that during according to the initial work of tested AXI bus architectures
Stable clock signal time, reset signal enable times, internal each timely sequence information of Special controlling signal list writes chip
Initialization control document.
3. method according to claim 1 or 2, it is characterized in that the Run Script controls document certainly according to chip initiation
Dynamic generation is directed to the initial environment configuration order of AXI bus architectures and performed, and test vector is performed afterwards, carries out test checking simultaneously
Generate test report.
4. method according to claim 3, it is characterized in that the bus architecture information document includes tested AXI bus architectures
The quantity and its device id of master-slave equipment in type, bus architecture, the axi_interconnect_1 IP kernels quantity and name used
Word and the device id of each IP kernel arbitration.
5. the method according to claim 1 or 2 or 4, it is characterized in that the register information document includes internal register
With the address of ram modules, data width, depth, reading/writing characteristics, read write command delay and read-write associated order information.
6. method according to claim 5, it is characterized in that the output information controls script by reserving control port,
The classification control of output information is carried out in test process according to actual needs.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108319534A (en) * | 2018-01-25 | 2018-07-24 | 济南浪潮高新科技投资发展有限公司 | A kind of test vector generating method and device |
| CN109697310A (en) * | 2018-12-07 | 2019-04-30 | 天津津航计算技术研究所 | A kind of function verification method and system applied to ahb bus matrix design |
| CN111858218A (en) * | 2020-07-29 | 2020-10-30 | 浪潮(北京)电子信息产业有限公司 | FPGA AMBA bus interface debugging method and device and FPGA |
| CN112286746A (en) * | 2020-10-31 | 2021-01-29 | 拓维电子科技(上海)有限公司 | Universal verification platform and method for AXI slave device interface |
| CN113010361A (en) * | 2021-02-22 | 2021-06-22 | 无锡中微亿芯有限公司 | MIO function rapid verification method of fully programmable SOC chip |
| CN117234831A (en) * | 2023-11-14 | 2023-12-15 | 鹏钛存储技术(南京)有限公司 | Chip function test method and system based on multi-core CPU |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108319534A (en) * | 2018-01-25 | 2018-07-24 | 济南浪潮高新科技投资发展有限公司 | A kind of test vector generating method and device |
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| CN111858218A (en) * | 2020-07-29 | 2020-10-30 | 浪潮(北京)电子信息产业有限公司 | FPGA AMBA bus interface debugging method and device and FPGA |
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| CN112286746A (en) * | 2020-10-31 | 2021-01-29 | 拓维电子科技(上海)有限公司 | Universal verification platform and method for AXI slave device interface |
| CN112286746B (en) * | 2020-10-31 | 2023-01-24 | 拓维电子科技(上海)有限公司 | Universal verification platform and method for AXI slave device interface |
| CN113010361A (en) * | 2021-02-22 | 2021-06-22 | 无锡中微亿芯有限公司 | MIO function rapid verification method of fully programmable SOC chip |
| CN117234831A (en) * | 2023-11-14 | 2023-12-15 | 鹏钛存储技术(南京)有限公司 | Chip function test method and system based on multi-core CPU |
| CN117234831B (en) * | 2023-11-14 | 2024-01-26 | 鹏钛存储技术(南京)有限公司 | Chip function test method and system based on multi-core CPU |
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Application publication date: 20170915 |