CN107491605A - A kind of function verification method and platform for chip design - Google Patents
A kind of function verification method and platform for chip design Download PDFInfo
- Publication number
- CN107491605A CN107491605A CN201710702836.XA CN201710702836A CN107491605A CN 107491605 A CN107491605 A CN 107491605A CN 201710702836 A CN201710702836 A CN 201710702836A CN 107491605 A CN107491605 A CN 107491605A
- Authority
- CN
- China
- Prior art keywords
- information
- test
- register
- module
- script
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
It is as follows the step of this method in the chip design based on PLB buses, testing the register in the chip and the read-write capability of ram modules the invention discloses a kind of function verification method and platform for chip design：First by reading the information of register and ram modules, register information document is established；Automatic script module is designed, the automatic script module is directed to the test vector testing results according to register information document structure tree test vector, finally exports test result, completes verification process.A kind of function verification method and platform for chip design of the present invention is compared with prior art, the test of the register and ram modules in the design based on PLB buses can be completed, with the characteristics of construction cycle is short, versatile and automaticity is high, chip checking efficiency can be increased substantially；It is practical, it is applied widely, it is easy to spread, have broad application prospects.
Description
Technical field
The present invention relates to electronic applications, specifically a kind of function verification method and platform for chip design.
Background technology
In the prior art, ic manufacturing technology improves rapidly, while market is continuous to the demand of high integration product
Increase, cause the complexity of integrated circuit in exponential increase.With the increase of IC complexity, validation difficulty is with higher
Speed increase.Therefore, the fulfillment capability of checking work is improved, has become the emphasis and difficult point of large scale integrated circuit exploitation.
Core connect be IBM Corporation propose towards core+ASIC exploitation or SoC design bus specification, can be
Whole system provides efficient, complete connected mode.It includes three kinds of different bus types, i.e. processor internal bus PLB
（Process Local Bus）, peripheral bus OPB on piece（On-Chip Peripheral Bus) and equipment controlling bus DCR
（Devices Control Register）.PLB buses are used to connect high-speed peripheral, have 64 bit address buses and 128 digits
According to bus.Each PLB main equipments are connected to PLB by independent address, reading data and write data bus, and PLB slave units are then led to
Shared address, reading data and write data bus is crossed to be connected with PLB.The bus right to use is allocated by moderator, arbitrates machine
System is flexibly and supporting bus locks, so as to allow main equipment to enter row bus atomic operation.PLB is a global synchronization bus,
The PLB signals of all master-slave equipments are all driven by unified clock.Therefore, PLB buses are in Core connect buses
Chip design based on PLB buses that mostly important and complicated part is each develops verification platform and is used for pair setting
Register and ram modules inside meter carry out the work that emulation testing is very very complicated.
The content of the invention
The technical assignment of the present invention is to be directed to above weak point, there is provided a kind of function verification method for chip design
And platform.
It is a kind of for chip design function verification method, for based on PLB buses chip design when, to the chip
Interior register and the test of the read-write capability of ram modules, it is as follows the step of this method：
First, register information document is established by reading the information of register and ram modules first；
2nd, automatic script module is designed, the automatic script module is directed to and is somebody's turn to do according to register information document structure tree test vector
Test vector testing results, finally export test result, complete verification process.
Before establishing register information document, design chips initialization control document, initialization control document are initially set up
For the initial work entirely designed, its content initialized include the stable clock signal time, reset signal enable time,
Chip internal control signal list and timing information.
The information of register and the ram module includes address, data width, depth, reading/writing characteristics, read write command delay
And read-write order information.
The automatic script module designed in step 2 includes test vector generation script, output information control script and operation
Script, wherein test vector generation script are used for according to register information document structure tree test vector；Output information controls script
Information for being exported to test process carries out classification control；Run Script is then used to perform test process.
The detailed process of testing results is in step 2：
Test vector generation script generates the selected deposit to be tested according to register and the information document of ram modules first
The test vector of device or ram modules；
Output information control script reserves control port, sets current test to need to be output to the information category of log files；
Run Script initialization command sequence according to corresponding to the chip initiation of design controls document structure tree, is transported again after performing
Row test vector, test report is generated, completes this test process.
When designing automatic script module, the read write command template for meeting agreement timing requirements is write always according to PLB agreements
Storehouse, the read write command ATL can be multiplexed with automatic script module in the chip design process based on PLB buses.
A kind of functional verification platform for chip design, for the functional verification of the chip design based on PLB buses, bag
Include,
Initialization information module, by reading the information of the register to be tested selected in chip design or ram modules, build
Vertical register information document；
Automatic script module, according to register information document structure tree test vector, and the test vector testing results are directed to, finally
Test result is exported, completes verification process.
The register information document that the initialization information module is established includes the address of register and ram modules, number
According to width, depth, reading/writing characteristics, read write command delay and read-write order information.
The automatic script module includes test vector generation module, output information control module and operation module, wherein
Test vector generation module is used for according to register information document structure tree test vector；Operation module is used to perform test process,
Commissioning test test vector；Output information control module is used to carry out classification control to the information of test process output, completes to survey
Try the output of information.
In the automatic script module, test vector generation module is according to register and the information document of ram modules, generation
The selected register to be tested or the test vector of ram modules；Output information control module reserves control port, sets current
Test need to be output to the information category of log files；Module generation initialization command sequence is run, to based on PLB buses
The environment initial configuration of chip design, performs test vector afterwards, completes test process and generates test report.
Compared to the prior art a kind of function verification method and platform for chip design of the present invention, has with following
Beneficial effect：
A kind of function verification method and platform for chip design of the present invention, is entered using script and hardware description language
Row verification platform is built, and is understood that verification platform does not have language threshold for designer, is easy to designer and checking personnel
Exchanged；The verification platform built by this method can complete register and ram modules in the design based on PLB buses
Test, there is the characteristics of construction cycle is short, versatile and automaticity is high, chip checking effect can be increased substantially
Rate；It is practical, it is applied widely, it is easy to spread, have broad application prospects.
Embodiment
In order that those skilled in the art more fully understand the solution of the present invention, with reference to embodiment to this
Invention is described in further detail.Obviously, described embodiment is only part of the embodiment of the present invention, rather than all
Embodiment.Based on the embodiment in the present invention, those of ordinary skill in the art institute under the premise of creative work is not made
The every other embodiment obtained, belongs to the scope of protection of the invention.
The present invention is directed to the disclosure and versatility of PLB bus protocols, describes a kind of functional verification for chip design
Method, realize and document and secondary is controlled according to internal register and ram module informations document, chip initiation using automatized script
Cut out module working method and describe document automation completion test vector generation and operation.This method is easy to implement, and flow is simple, high
Effect is stable, can significantly shorten to the construction cycle that functional verification platform is built in the different designs based on PLB buses, improves work(
It is able to verify that efficiency.
The step of this method, is as follows：
First, register information document is established by reading the information of register and ram modules first；
2nd, automatic script module is designed, the automatic script module is directed to and is somebody's turn to do according to register information document structure tree test vector
Test vector testing results, finally export test result, complete verification process.
Above method step is initial for the internal register and ram module informations document and chip of current tested design
Change control document, generation, operation and the control of validation test vector are completed using a variety of automatized scripts.
Internal register and ram module informations document are completed to write according to the design based on PLB buses.
Chip initiation controls document to complete to write according to the initial work flow of the design based on PLB buses.
Arbitration modules working method describes document based on the arbitration mode selected in design, such as whether supporting bus locking and
Atomic operation etc., completed according to regulation form.
Internal register and ram module informations document are completed to write according to the design based on PLB buses, in addition to：It is tested
Design internal register and ram modules can be conducted interviews by using PLB buses.
Automatized script can use the various scripting languages such as perl/tcl/c-shell, thus method has height
Versatility.
Before establishing register information document, design chips initialization control document, initialization control document are initially set up
For the initial work entirely designed, its content initialized include the stable clock signal time, reset signal enable time,
Chip internal control signal list and timing information.
The information of register and the ram module includes address, data width, depth, reading/writing characteristics, read write command delay
And read-write order information.
Before step 2 is performed, in addition to the step of arbitration modules working method describes document is write, based in design
The arbitration mode of selection, such as whether supporting bus locking and atomic operation etc., are completed according to regulation form.
The automatic script module designed in step 2 includes test vector generation script, output information control script and operation
Script, wherein test vector generation script are used for according to register information document structure tree test vector；Output information controls script
Information for being exported to test process carries out classification control；Run Script is then used to perform test process.
The detailed process of testing results is in step 2：
Test vector generation script generates the selected deposit to be tested according to register and the information document of ram modules first
The test vector of device or ram modules；
Output information control script reserves control port, sets current test to need to be output to the information category of log files；
Run Script initialization command sequence according to corresponding to the chip initiation of design controls document structure tree, is transported again after performing
Row test vector, test report is generated, completes this test process.
When designing automatic script module, the read write command template for meeting agreement timing requirements is write always according to PLB agreements
Storehouse, the read write command ATL can be multiplexed with automatic script module in the chip design process based on PLB buses.
A kind of functional verification platform for chip design, for the functional verification of the chip design based on PLB buses, bag
Include,
Initialization information module, by reading the information of the register to be tested selected in chip design or ram modules, build
Vertical register information document；
Automatic script module, according to register information document structure tree test vector, and the test vector testing results are directed to, finally
Test result is exported, completes verification process.
The register information document that the initialization information module is established includes the address of register and ram modules, number
According to width, depth, reading/writing characteristics, read write command delay and read-write order information.
The automatic script module includes test vector generation module, output information control module and operation module, wherein
Test vector generation module is used for according to register information document structure tree test vector；Operation module is used to perform test process,
Commissioning test test vector；Output information control module is used to carry out classification control to the information of test process output, completes to survey
Try the output of information.
In the automatic script module, test vector generation module is according to register and the information document of ram modules, generation
The selected register to be tested or the test vector of ram modules；Output information control module reserves control port, sets current
Test need to be output to the information category of log files；Module generation initialization command sequence is run, to based on PLB buses
The environment initial configuration of chip design, performs test vector afterwards, completes test process and generates test report.
Method provided by the invention and platform automatically complete building for verification platform by using automatized script, realization
With operation work；By measured PLB bus protocols design verification platform test order, realize to being respectively based on PLB buses
Design general readwrite tests；Realized by using internal register and ram module informations document and be directed to particular memory module
Correct test；The configuration to the initial authentication environment of different designs is realized by using chip initiation control document.The party
Method is easy to implement, and flow is simple, efficient stable, can significantly shorten to the different designs based on PLB buses and build function to test
The construction cycle of platform is demonstrate,proved, improves functional verification efficiency.
By embodiment above, the those skilled in the art can readily realize the present invention.But should
Work as understanding, the present invention is not limited to above-mentioned embodiment.On the basis of disclosed embodiment, the technical field
Technical staff can be combined different technical characteristics, so as to realize different technical schemes.
It is the known technology of those skilled in the art in addition to the technical characteristic described in specification.
Claims (10)
1. a kind of function verification method for chip design, it is characterised in that in the chip design based on PLB buses
When, the register in the chip and the read-write capability of ram modules are tested, it is as follows the step of this method：
First, register information document is established by reading the information of register and ram modules first；
2nd, automatic script module is designed, the automatic script module is directed to and is somebody's turn to do according to register information document structure tree test vector
Test vector testing results, finally export test result, complete verification process.
2. a kind of function verification method for chip design according to claim 1, it is characterised in that establish register
Before information document, design chips initialization control document is initially set up, initialization control document is initial for entirely designing
Chemical industry is made, and its content initialized includes stable clock signal time, reset signal enable time, chip internal control signal row
Table and timing information.
A kind of 3. function verification method for chip design according to claim 2, it is characterised in that the register
Include address, data width, depth, reading/writing characteristics, read write command delay and read-write order information with the information of ram modules.
A kind of 4. function verification method for chip design according to Claims 2 or 3, it is characterised in that step 2
The automatic script module of middle design includes test vector generation script, output information control script and Run Script, wherein testing
Vector generation script is used for according to register information document structure tree test vector；Output information control script is used for test process
The information of output carries out classification control；Run Script is then used to perform test process.
5. a kind of function verification method for chip design according to claim 4, it is characterised in that transported in step 2
Row test detailed process be：
Test vector generation script generates the selected deposit to be tested according to register and the information document of ram modules first
The test vector of device or ram modules；
Output information control script reserves control port, sets current test to need to be output to the information category of log files；
Run Script initialization command sequence according to corresponding to the chip initiation of design controls document structure tree, is transported again after performing
Row test vector, test report is generated, completes this test process.
6. a kind of function verification method for chip design according to claim 5, it is characterised in that automatic in design
During script module, the read write command ATL for meeting agreement timing requirements is write always according to PLB agreements, the read write command ATL
It can be multiplexed with automatic script module in the chip design process based on PLB buses.
A kind of 7. functional verification platform for chip design, it is characterised in that the work(for the chip design based on PLB buses
It is able to verify that, including,
Initialization information module, by reading the information of the register to be tested selected in chip design or ram modules, build
Vertical register information document；
Automatic script module, according to register information document structure tree test vector, and the test vector testing results are directed to, finally
Test result is exported, completes verification process.
A kind of 8. function verification method for chip design according to claim 7, it is characterised in that the initialization
The register information document that information module is established includes the address of register and ram modules, data width, depth, read-write spy
Sign, read write command delay and read-write order information.
9. according to claim 7 or 8 it is a kind of for chip design function verification method, it is characterised in that it is described from
Dynamic script module includes test vector generation module, output information control module and operation module, wherein test vector generation mould
Block is used for according to register information document structure tree test vector；Operation module is used to perform test process, commissioning test test to
Amount；Output information control module is used to carry out classification control to the information of test process output, completes the output of test information.
10. a kind of function verification method for chip design according to claim 9, it is characterised in that described automatic
In script module, test vector generation module according to register and the information document of ram modules, generate it is selected to be tested post
The test vector of storage or ram modules；Output information control module reserves control port, sets current test to need to be output to
The information category of log files；Module generation initialization command sequence is run, at the beginning of the environment of the chip design based on PLB buses
Begin to configure, perform test vector afterwards, complete test process and simultaneously generate test report.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710702836.XA CN107491605A (en) | 2017-08-16 | 2017-08-16 | A kind of function verification method and platform for chip design |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710702836.XA CN107491605A (en) | 2017-08-16 | 2017-08-16 | A kind of function verification method and platform for chip design |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107491605A true CN107491605A (en) | 2017-12-19 |
Family
ID=60646186
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710702836.XA Pending CN107491605A (en) | 2017-08-16 | 2017-08-16 | A kind of function verification method and platform for chip design |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107491605A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113009318A (en) * | 2021-02-25 | 2021-06-22 | 合肥宏晶微电子科技股份有限公司 | Test equipment and test method for video processing chip |
| CN113010361A (en) * | 2021-02-22 | 2021-06-22 | 无锡中微亿芯有限公司 | MIO function rapid verification method of fully programmable SOC chip |
| CN113094274A (en) * | 2021-04-14 | 2021-07-09 | 深圳忆联信息系统有限公司 | Python-based FPGA (field programmable Gate array) verification method and device, computer equipment and storage medium |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106845004A (en) * | 2017-02-15 | 2017-06-13 | 济南浪潮高新科技投资发展有限公司 | It is a kind of that system and method is built based on script for functional verification platform |
-
2017
- 2017-08-16 CN CN201710702836.XA patent/CN107491605A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106845004A (en) * | 2017-02-15 | 2017-06-13 | 济南浪潮高新科技投资发展有限公司 | It is a kind of that system and method is built based on script for functional verification platform |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113010361A (en) * | 2021-02-22 | 2021-06-22 | 无锡中微亿芯有限公司 | MIO function rapid verification method of fully programmable SOC chip |
| CN113009318A (en) * | 2021-02-25 | 2021-06-22 | 合肥宏晶微电子科技股份有限公司 | Test equipment and test method for video processing chip |
| CN113009318B (en) * | 2021-02-25 | 2023-07-18 | 宏晶微电子科技股份有限公司 | Testing equipment and testing method for video processing chip |
| CN113094274A (en) * | 2021-04-14 | 2021-07-09 | 深圳忆联信息系统有限公司 | Python-based FPGA (field programmable Gate array) verification method and device, computer equipment and storage medium |
| CN113094274B (en) * | 2021-04-14 | 2023-10-13 | 深圳忆联信息系统有限公司 | Python-based FPGA verification method and device, computer equipment and storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101183406B (en) | Method for establishing network chip module level function checking testing platform | |
| CN102169846B (en) | Method for writing multi-dimensional variable password in parallel in process of testing integrated circuit wafer | |
| CN101153892B (en) | Verification method for field programmable gate array input/output module | |
| CN102262212B (en) | System for detecting trigger single particle effect in digital application specific integrated circuit | |
| CN107491605A (en) | A kind of function verification method and platform for chip design | |
| CN105069227A (en) | Method for building function verification platform based on WISHBONE bus design | |
| CN103268380A (en) | Analogue integrated circuit layout designing method capable of improving layout efficiency | |
| CN106294144B (en) | Generation method, system and the server of the test vector of serial communication protocol | |
| CN104407279A (en) | Code type data, apparatus and test method for automatically testing chip MDIO bus protocol | |
| CN112214957B (en) | Cake type integrated circuit layout method and system for chip | |
| CN107329872A (en) | A kind of application verification plate of coprocessor | |
| CN107168843A (en) | A kind of building method of the functional verification platform based on AXI buses | |
| CN103942379B (en) | All-digital silicon controlled rectifier controller chip for three-phase alternating-current voltage regulation and rectification | |
| CN106773954A (en) | A kind of operating mode control method in microcontroller chip | |
| CN112597719A (en) | Data network design verification method and device and verification equipment | |
| CN110750949A (en) | Method for simulating system-in-package dose rate effect based on IBIS model | |
| CN107943644A (en) | A kind of building method of functional verification platform for the design based on LOCAL BUS buses | |
| CN107122562B (en) | Active power distribution network real-time simulator serial communication method based on multiple FPGA | |
| CN102446557B (en) | A kind of a kind of method of chip and chip parallel test | |
| CN106845004A (en) | It is a kind of that system and method is built based on script for functional verification platform | |
| CN202815170U (en) | Chip test system | |
| CN108957301A (en) | Test method, test device and built-in chip type circuit can be tested | |
| CN110045782A (en) | A kind of reading and writing data synchronous circuit and data read-write method | |
| CN109426671B (en) | Method and device for generating boundary scan chain and computer readable storage medium | |
| CN113128144A (en) | Prototype verification system and simulation platform for verifying logic system design |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20171219 |
|
| RJ01 | Rejection of invention patent application after publication |