CN105573881A - BFM-based method and system for rapidly verifying address of large-sized inter-connected chip - Google Patents
BFM-based method and system for rapidly verifying address of large-sized inter-connected chip Download PDFInfo
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- CN105573881A CN105573881A CN201510927414.3A CN201510927414A CN105573881A CN 105573881 A CN105573881 A CN 105573881A CN 201510927414 A CN201510927414 A CN 201510927414A CN 105573881 A CN105573881 A CN 105573881A
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Abstract
The embodiment of the invention discloses a BFM-based method and system for rapidly verifying an address of a large-sized inter-connected chip. The method comprises the following steps of sending a writing instruction to a target chip by a forwarding chip, wherein the writing instruction comprises target address information and verification data; receiving feedback information sent by the forwarding chip after the verification data is written into a target address by the target chip; and sending a reading instruction to the target chip by the forwarding chip, receiving the verification data read from the target address through the target chip by the forwarding chip, judging whether the verification data written into the target address is consistent with the verification data read from the target address or not, if yes, the target address is successfully verified. Therefore, in the embodiment, the verification correctness is ensured through address verification of first writing and then reading, a verification code is simple and short and is high in readability, the verification speed is greatly increased, and the production period of the chip is shortened.
Description
Technical field
The present invention relates to chip address read-write technical field, more particularly, relate to a kind of method and system based on the large-scale interconnect die address of BFM fast verification.
Background technology
Along with developing rapidly of integrated circuit fabrication process, the construction cycle of chip shortens gradually, and the time of the product release of said function, more early competitive power was larger.Time needed for checking work becomes the bottleneck of limit product construction cycle.Because large-scale interconnect die NC is in large scale, be not suitable for doing the checking of large-scale module level, be therefore combined BFM model and carry out the verification method that system-level simulating, verifying becomes a kind of necessity verifying large-scale interconnect die NC.The checking of Large-Scale Interconnected chip NC is loaded down with trivial details, a time-consuming job, in order to improve the verification efficiency of integrated circuit, shortens production life cycle, and checking personnel must ensure shorten proving period as far as possible under the prerequisite that chip checking is errorless.Because the address read-write correctness of Large-Scale Interconnected chip is the prerequisite ensureing that other functional verifications are carried out smoothly, can lay a good foundation for completing of other subsequent authentication so carry out address read-write checking fast.
Therefore, how to carry out address read-write checking fast, the time shortened needed for the checking of chip entirety is the problem needing now to solve.
Summary of the invention
The object of the present invention is to provide a kind of method and system based on the large-scale interconnect die address of BFM fast verification, to carry out read-write checking to address fast, shorten the time needed for the checking of chip entirety.
For achieving the above object, following technical scheme is embodiments provided:
Based on a verification method for the large-scale interconnect die address of BFM fast verification, comprising:
Write command is sent to objective chip by forwarding chip; Wherein, described write command comprises target address information and verification msg;
Receive described objective chip by after described verification msg write destination address, the feedback information sent by described forwarding chip;
Instruction is read to described objective chip transmission by described forwarding chip, and receive by described forwarding chip the verification msg that described objective chip reads from described destination address, and judge that whether the verification msg writing described destination address is consistent with the verification msg read from described destination address;
If consistent, then described destination address is proved to be successful.
Preferably, the router simulated by BFM between described forwarding chip and described objective chip and Physical layer path carry out the transmission of data.
Preferably, sent before write command to objective chip by forwarding chip, also comprise:
Destination address to be verified is written as array formats to store;
Wherein, describedly send write command by forwarding chip to objective chip, comprising:
Obtain destination address to be verified, determine the objective chip at described destination address place, by forwarding chip, described write command is sent to objective chip.
Preferably, judge to write the verification msg of described destination address whether consistent with the verification msg read from described destination address before, also comprise:
Generate the proof procedure corresponding with described destination address to report.
Preferably, if the verification msg writing described destination address is inconsistent with the verification msg read from described destination address, then described method also comprises:
Analyze described proof procedure report generation interpretation of result report, and again described destination address is verified according to described interpretation of result report.
Based on a verification system for the large-scale interconnect die address of BFM fast verification, comprising: controller, forwarding chip and objective chip;
Described controller comprises:
Write command performance element, for sending write command by forwarding chip to objective chip; Wherein, described write command comprises target address information and verification msg;
Read instruction execution unit, for receiving described objective chip by after described verification msg write destination address, the feedback information sent by described forwarding chip; And to be sent to described objective chip by described forwarding chip and read instruction, receive by described forwarding chip the verification msg that described objective chip reads from described destination address;
Judging unit, for judging that whether the verification msg writing described destination address is consistent with the verification msg read from described destination address; If consistent, then described destination address is proved to be successful.
Preferably, the router simulated by BFM between described forwarding chip and described objective chip and Physical layer path carry out the transmission of data.
Preferably, described controller also comprises:
Poke unit, stores for destination address to be verified being written as array formats;
Wherein, write command performance element specifically for:
Obtain destination address to be verified, determine the objective chip at described destination address place, by forwarding chip, described write command is sent to objective chip.
Preferably, described controller also comprises:
Generation unit, for generating the proof procedure corresponding with described destination address report.
Preferably, if when described judging unit judges that the verification msg of the described destination address of write and the verification msg read from described destination address are inconsistent, described verification system also comprises triggering analysis unit;
Described analytic unit for analyzing described proof procedure report generation interpretation of result report, and triggers described write command performance element again according to described interpretation of result report, again verifies described destination address.
Known by above scheme, a kind of verification method based on the large-scale interconnect die address of BFM fast verification that the embodiment of the present invention provides and system, comprising: send write command by forwarding chip to objective chip; Wherein, described write command comprises target address information and verification msg; Receive described objective chip by after described verification msg write destination address, the feedback information sent by described forwarding chip; Instruction is read to described objective chip transmission by described forwarding chip, and receive by described forwarding chip the verification msg that described objective chip reads from described destination address, and judge that whether the verification msg writing described destination address is consistent with the verification msg read from described destination address; If consistent, then described destination address is proved to be successful.
Visible, in the present embodiment, the router simulated by BFM and Physical layer path carry out the transmission of data, when making checking slip-stick artist write verification msg, the thinking of interface data operation can be absorbed in, and ignore the sequential of bottom layer signal completely, alleviate the workload of writing excitation, improve efficiency, and destination address to be verified is written as array number poke, the correctness of the checking that the address validation carrying out write-then-read not only ensures, also make Validation Code brief, readable high, more substantially increase the speed of checking, shorten the production cycle of chip.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is a kind of verification method based on the large-scale interconnect die address of BFM fast verification disclosed in the embodiment of the present invention;
Fig. 2 is verification system structural representation disclosed in the embodiment of the present invention;
Fig. 3 is a kind of verification system structural representation based on the large-scale interconnect die address of BFM fast verification disclosed in the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The embodiment of the invention discloses a kind of method and system based on the large-scale interconnect die address of BFM fast verification, to carry out read-write checking to address fast, shorten the time needed for the checking of chip entirety.
See Fig. 1, a kind of verification method based on the large-scale interconnect die address of BFM fast verification that the embodiment of the present invention provides, comprising:
S101, send write command by forwarding chip to objective chip; Wherein, described write command comprises target address information and verification msg;
Concrete, see Fig. 2, verification system structural representation disclosed in the embodiment of the present invention, comprise 2 clump, i.e. clump1 and clump2, wherein each clump cpu model of being simulated by 4 BFM and two NC chips are formed, wherein cpu model is the controller in the present embodiment, NC chip 1 in clump1 is the forwarding chip in the present embodiment, NC chip 3 in clump2 is the objective chip in the present embodiment, controller 1 is the controller in the present embodiment, and wherein destination address is the address in objective chip.In the verification environment of these 2 clump, under the testbench built by verilog, be connected by pli (ProgramLanguageInterface) interface between the cpu model that NC chip and BFM simulate.
In the address of 2clump read-write verification environment, mainly build the path in two pieces of different clump between NC chip with BFM, removing practical function on equivalence and simulation velocity lifting outside, the simulation of this part can also utilize SystemC to realize the higher operation of level of abstraction and data monitoring as the advantage of software language.Be connected with the testbench of verilog by pli interface, the action of simulating CPU with BFM (sends or receives instruction, and respond), by writing with systemC code under BFM, the read and write access of address is encouraged, monitoring mechanism and corresponding various rule.
Wherein, the router simulated by BFM between described forwarding chip and described objective chip and Physical layer path carry out the transmission of data.
Concrete, in the present embodiment, controller sends write command to destination address, namely write command is sent by the controller in clump1 to NC chip 1, wherein carry target address information in write command, according to target address information, and write command is sent to NC chip 3 by the router simulated by BFM between NC chip 1 and NC chip 3 and Physical layer path.
S102, receive described objective chip by after described verification msg write destination address, the feedback information sent by described forwarding chip;
Concrete, in the present embodiment, cpu1 needs to determine that write command performs end, after therefore verification msg is write destination address by NC chip 3 before instruction is read in NC chip 3 transmission, need to send to cpu1 feedback information, namely determine that write command performs end.
S103, to be sent to described objective chip by described forwarding chip and read instruction, and receive by described forwarding chip the verification msg that described objective chip reads from described destination address;
Concrete, in the present embodiment, cpu1, by the path identical with write command, will read instruction by the NC chip 1 in clum1 send to NC chip 3 by reading instruction, and the test data write before reading from the destination address of NC chip 3.
S104, judge that whether the verification msg writing described destination address is consistent with the verification msg read from described destination address; If if consistent, then described destination address is proved to be successful, if inconsistent, authentication failed.
Concrete, when in the present embodiment read-write checking being carried out to destination address, GreateWrTrans (write address excitation) and GreateRdTrans (reading address excitation) is successively sent at cpu model end, write address excitation can be interpreted as write command in the present embodiment here, the excitation of degree address be interpreted as and in the present embodiment, read instruction.When the test data read from destination address is consistent with the test data of write, illustrates and be verified, inconsistent will tracing problem based changing.
Wherein, sent before write command to objective chip by forwarding chip, also comprise:
Destination address to be verified is written as array formats to store;
Wherein, describedly send write command by forwarding chip to objective chip, comprising:
Obtain destination address to be verified, determine the objective chip at described destination address place, by forwarding chip, described write command is sent to objective chip.
Wherein, judge to write the verification msg of described destination address whether consistent with the verification msg read from described destination address before, also comprise:
Generate the proof procedure corresponding with described destination address to report.
Wherein, if the verification msg writing described destination address is inconsistent with the verification msg read from described destination address, then described method also comprises:
Analyze described proof procedure report generation interpretation of result report, and again described destination address is verified according to described interpretation of result report.
Concrete, in the present embodiment, array formats is become to store by needing the address preparation of checking, GreateWrTrans (the write address function in BFM) is first utilized to perform data writing operation toward destination address to destination address, recycling GreateRdTrans (reading address function in BFM) reads the data in destination address, compare with the data previously write into after reading, if comparison unanimously, represents this destination address by checking, find erroneous point if the inconsistent needs of comparison carry out labor to result and simulation process and report to designer, design is corrected by designer, checking is re-started again after design corrigendum.Namely the report of corresponding proof procedure can be generated when verifying each destination address, when the verification msg writing destination address is inconsistent with the verification msg read from destination address, then can according to proof procedure report analysis error reason, thus generate interpretation of result report, and again destination address is verified according to described interpretation of result report.
Concrete, when needing the chip address space of checking very large, checking personnel will shorten the length of testcase as far as possible, under the prerequisite of the readability of the comprehensive and Validation Code of guarantee address validation, shorten the simulation time of testcase, rapidly and efficiently comprehensively complete validation task.
A kind of verification method based on the large-scale interconnect die address of BFM fast verification that the embodiment of the present invention provides, comprising: send write command by forwarding chip to objective chip; Wherein, described write command comprises target address information and verification msg; Receive described objective chip by after described verification msg write destination address, the feedback information sent by described forwarding chip; Instruction is read to described objective chip transmission by described forwarding chip, and receive by described forwarding chip the verification msg that described objective chip reads from described destination address, and judge that whether the verification msg writing described destination address is consistent with the verification msg read from described destination address; If consistent, then described destination address is proved to be successful.
Visible, in the present embodiment, the router simulated by BFM and Physical layer path carry out the transmission of data, when making checking slip-stick artist write verification msg, the thinking of interface data operation can be absorbed in, and ignore the sequential of bottom layer signal completely, alleviate the workload of writing excitation, improve efficiency, and destination address to be verified is written as array number poke, the correctness of the checking that the address validation carrying out write-then-read not only ensures, also make Validation Code brief, readable high, more substantially increase the speed of checking, shorten the production cycle of chip.
Be introduced the verification system based on the large-scale interconnect die address of BFM fast verification that the embodiment of the present invention provides below, the verification system based on BFM fast verification large-scale interconnect die address described below and the above-described verification method based on BFM fast verification large-scale interconnect die address can be cross-referenced.
See Fig. 3, a kind of verification system based on the large-scale interconnect die address of BFM fast verification that the embodiment of the present invention provides, comprising: controller 100, forwarding chip 200 and objective chip 300;
Described controller 100 comprises:
Write command performance element 110, for sending write command by forwarding chip to objective chip; Wherein, described write command comprises target address information and verification msg;
Read instruction execution unit 120, for receiving described objective chip by after described verification msg write destination address, the feedback information sent by described forwarding chip; And to be sent to described objective chip by described forwarding chip and read instruction, receive by described forwarding chip the verification msg that described objective chip reads from described destination address;
Judging unit 130, for judging that whether the verification msg writing described destination address is consistent with the verification msg read from described destination address; If consistent, then described destination address is proved to be successful.
Wherein, the router simulated by BFM between described forwarding chip and described objective chip and Physical layer path carry out the transmission of data.
Wherein, described controller 100 also comprises:
Poke unit, stores for destination address to be verified being written as array formats;
Wherein, write command performance element specifically for:
Obtain destination address to be verified, determine the objective chip at described destination address place, by forwarding chip, described write command is sent to objective chip.
Wherein, described controller 100 also comprises:
Generation unit, for generating the proof procedure corresponding with described destination address report.
Wherein, if when described judging unit judges that the verification msg of the described destination address of write and the verification msg read from described destination address are inconsistent, described verification system also comprises triggering analysis unit;
Described analytic unit for analyzing described proof procedure report generation interpretation of result report, and triggers described write command performance element again according to described interpretation of result report, again verifies described destination address.
In this instructions, each embodiment adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar portion mutually see.
To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (10)
1., based on a verification method for the large-scale interconnect die address of BFM fast verification, it is characterized in that, comprising:
Write command is sent to objective chip by forwarding chip; Wherein, described write command comprises target address information and verification msg;
Receive described objective chip by after described verification msg write destination address, the feedback information sent by described forwarding chip;
Instruction is read to described objective chip transmission by described forwarding chip, and receive by described forwarding chip the verification msg that described objective chip reads from described destination address, and judge that whether the verification msg writing described destination address is consistent with the verification msg read from described destination address;
If consistent, then described destination address is proved to be successful.
2. verification method according to claim 1, is characterized in that, the router simulated by BFM between described forwarding chip and described objective chip and Physical layer path carry out the transmission of data.
3. verification method according to claim 2, is characterized in that, is sent before write command, also comprise by forwarding chip to objective chip:
Destination address to be verified is written as array formats to store;
Wherein, describedly send write command by forwarding chip to objective chip, comprising:
Obtain destination address to be verified, determine the objective chip at described destination address place, by forwarding chip, described write command is sent to objective chip.
4. verification method according to claim 3, is characterized in that, judge to write the verification msg of described destination address whether consistent with the verification msg read from described destination address before, also comprise:
Generate the proof procedure corresponding with described destination address to report.
5. verification method according to claim 4, is characterized in that, if the verification msg writing described destination address is inconsistent with the verification msg read from described destination address, then described method also comprises:
Analyze described proof procedure report generation interpretation of result report, and again described destination address is verified according to described interpretation of result report.
6. based on a verification system for the large-scale interconnect die address of BFM fast verification, it is characterized in that, comprising: controller, forwarding chip and objective chip;
Described controller comprises:
Write command performance element, for sending write command by forwarding chip to objective chip; Wherein, described write command comprises target address information and verification msg;
Read instruction execution unit, for receiving described objective chip by after described verification msg write destination address, the feedback information sent by described forwarding chip; And to be sent to described objective chip by described forwarding chip and read instruction, receive by described forwarding chip the verification msg that described objective chip reads from described destination address;
Judging unit, for judging that whether the verification msg writing described destination address is consistent with the verification msg read from described destination address; If consistent, then described destination address is proved to be successful.
7. verification system according to claim 6, is characterized in that, the router simulated by BFM between described forwarding chip and described objective chip and Physical layer path carry out the transmission of data.
8. verification system according to claim 7, is characterized in that, described controller also comprises:
Poke unit, stores for destination address to be verified being written as array formats;
Wherein, write command performance element specifically for:
Obtain destination address to be verified, determine the objective chip at described destination address place, by forwarding chip, described write command is sent to objective chip.
9. verification system according to claim 8, is characterized in that, described controller also comprises:
Generation unit, for generating the proof procedure corresponding with described destination address report.
10. verification system according to claim 9, is characterized in that, if when described judging unit judges that the verification msg of the described destination address of write and the verification msg read from described destination address are inconsistent, described verification system also comprises triggering analysis unit;
Described analytic unit for analyzing described proof procedure report generation interpretation of result report, and triggers described write command performance element again according to described interpretation of result report, again verifies described destination address.
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