CN105447215B - Digital circuit design method and relevant system - Google Patents
Digital circuit design method and relevant system Download PDFInfo
- Publication number
- CN105447215B CN105447215B CN201410495863.0A CN201410495863A CN105447215B CN 105447215 B CN105447215 B CN 105447215B CN 201410495863 A CN201410495863 A CN 201410495863A CN 105447215 B CN105447215 B CN 105447215B
- Authority
- CN
- China
- Prior art keywords
- shelves
- standard delay
- circuit
- delay format
- specific node
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
Present disclose provides a kind of digital circuit design method and relevant systems.The digital circuit design method includes：Before carrying out entity design：It is designed according to a Method at Register Transfer Level and is synthesized to carry out logic at least to generate a circuit program shelves, a standard delay format shelves and one first restrictive condition shelves with multiple restrictive conditions；At least information of a specific node is extracted in circuit from the first restrictive condition shelves, to generate one second restrictive condition shelves；Standard delay format shelves after a update are generated according at least to the standard delay format shelves and the second restrictive condition shelves, the retardation of the specific node is smaller than the retardation of the specific node in the standard delay format shelves in standard delay format shelves wherein after the update；And it is simulated after using standard delay format shelves after the circuit program shelves and the update carrying out an advance circuit layout.
Description
Technical field
The present invention relates to technical field of circuit design, more particularly to a kind of digital circuit design method and relevant system.
Background technology
Traditional Design of Digital Circuit is broadly divided into front section and hindfoot portion, and wherein front section is mainly contained and posted
Storage transmitting stage (Register Transfer Level, RTL) design with functional simulation (functional simulation),
And logic synthesis (logic synthesis), and hindfoot portion then contains entity design (physical design), electricity
It is simulated after road autoplacement and circuit layout (post layout simulation) etc..
In general, it can need not be done before being completed to entity design (physical design) after logic synthesis
Have the functional simulation of sequential time delay information, and do this analoglike also to have its difficulty, for example, in the setting of logic synthesis,
Node (high fan-out net) with high load number in circuit synthesizes generated timing information in logic
A huge delay time can be labeled out in (timing information), so that electricity caused by logic synthesis
Distance sequence shelves (netlist) can not arrange in pairs or groups the timing information to be simulated.
These above-mentioned nodes with high load number can carry out other processing in subsequent entity design and make
Its delay time will not be too long, if however, to wait until to simulate after just carrying out circuit layout after entity design, due at this time
Between put usually already close to throw piece produce (tape out) time therefore just pinpoint the problems if being simulated after circuit layout,
Often the time-histories table of product is impacted.
For Digital Design, if the restrictive condition (constraint) set when logic synthesizes it is correct and
Enough, and make correct static timing analysis (static timing analysi) according to this and by verification, in general circuit
Mistake can not too much occur for post layout simulation, however, sometimes due to engineer, when inputting restrictive condition, an error has occurred, lead
It has caused not find mistake in static timing analysis, but has just realized or certain designs after being simulated after making circuit layout
On mistake may also escape static timing analysis, and be only capable of after circuit layout simulate after just find.However, such as epimere institute
State, to wait until entity design after could find that this kind of mistake usually seems too late.
Invention content
It therefore, can be with one of the objects of the present invention is to provide a kind of digital circuit design method and relevant system
(pre-post-layout simulation) is simulated after can carrying out advance circuit layout before carrying out entity design, with
The upper possible mistake of discovery circuit design in advance, it is described in the prior art to solve the problems, such as.
An embodiment according to the present invention, a kind of digital circuit design method include：Before carrying out entity design：According to
To carry out, logic is synthesized at least to generate a circuit program shelves design of one Method at Register Transfer Level, a standard is prolonged with multiple restrictive conditions
Slow format shelves and one first restrictive condition shelves；An at least specific node in circuit is extracted from the first restrictive condition shelves
Information, to generate one second restrictive condition shelves；Come according at least to the standard delay format shelves and the second restrictive condition shelves
Standard delay format shelves after one update of generation, the retardation ratio of the specific node should in standard delay format shelves wherein after the update
The retardation of the specific node is small in standard delay format shelves；And use standard delay after the circuit program shelves and the update
Format shelves are simulated after carrying out an advance circuit layout.
Another embodiment according to the present invention discloses a kind of system for carrying out Design of Digital Circuit, via computer
The system is loaded into execute；The system includes the first program instruction module, the second program instruction module, third program instruction module
And fourth program instructions module；Before carrying out entity design：The first program instruction module, according to a Method at Register Transfer Level
Design with multiple restrictive conditions come carry out logic synthesize at least generate a circuit program shelves, a standard delay format shelves and
One first restrictive condition shelves；The second program instruction module extracts at least one spy in circuit from the first restrictive condition shelves
The information for determining node, to generate one second restrictive condition shelves；The third program instruction module, according at least to the standard delay format
Shelves and the second restrictive condition shelves generate standard delay format shelves after a update, wherein standard delay format shelves after the update
In the specific node retardation it is smaller than the retardation of the specific node in the standard delay format shelves；And the 4th program refer to
Module is enabled, is simulated after carrying out an advance circuit layout using standard delay format shelves after the circuit program shelves and the update.
Another embodiment according to the present invention, a kind of digital circuit design method include：Before carrying out entity design：Root
It designs according to a Method at Register Transfer Level and is synthesized to carry out logic at least to generate a circuit program shelves, a standard with multiple restrictive conditions
Standard delay format shelves are marked wherein for an at least specific node in circuit after the update after delay format shelves and a update
The retardation of the specific node is smaller than the retardation of the specific node in the standard delay format shelves in quasi- delay format shelves；And
It is simulated after carrying out an advance circuit layout using standard delay format shelves after the circuit program shelves and the update.
Another embodiment according to the present invention discloses a kind of system for carrying out Design of Digital Circuit, via computer
The system is loaded into execute：Before carrying out entity design：First program instruction module, according to a Method at Register Transfer Level design with
Multiple restrictive conditions synthesize to carry out logic at least to generate a circuit program shelves, a standard delay format shelves and a update
Standard delay format shelves afterwards, wherein for an at least specific node in circuit, this in standard delay format shelves is specific after the update
The retardation of node is smaller than the retardation of the specific node in the standard delay format shelves；And the second program instruction module, make
It is simulated after carrying out an advance circuit layout with standard delay format shelves after the circuit program shelves and the update.
Description of the drawings
Fig. 1 is the flow chart of the digital circuit design method of an embodiment according to the present invention.
Fig. 2 is the flow chart of the digital circuit design method of another embodiment according to the present invention.
Reference sign：
102~120,202~216 steps
Specific implementation mode
Referring to FIG. 1, Fig. 1 is the flow chart of the digital circuit design method of an embodiment according to the present invention.In this implementation
In example, digital circuit design method is used for carrying out after the system of Design of Digital Circuit is loaded by one computer/processor by one,
Performed by multiple program instruction modules, with reference to figure 1, the flow of digital circuit design method is described below.
First, in a step 102, it is designed according to a Method at Register Transfer Level (Register Transfer Level, RTL)
(logic synthesis) operation is synthesized carrying out logic with multiple restrictive conditions (constraint), with step 104,
106, generate in 108 a circuit program shelves (netlist), a standard delay format shelves (Standard Delay Format,
) and one first restrictive condition shelves (constraint file) SDF.Above-mentioned restrictive condition be inputted by engineer, and
Etc. contents that it is clock pulse input point mainly to contain which pin, and the frequency of clock pulse is how many ...；Circuit program shelves are a kind of
The file format of circuit is described, logically can the design of coincidence register transmitting stage, and engineer institute can be met in sequential
The restrictive condition of input；Standard delay format shelves mainly describe the retardation between each circuit unit and interconnection circuit
Between retardation ... etc.；First restrictive condition shelves mainly depict the content of above-mentioned restrictive condition, and about electricity
The information of node with high load number in road.It is noted that it is above-mentioned about restrictive condition, standard delay format shelves and
Content described in first restrictive condition shelves only relates to the part of the disclosure of invention, and those skilled in the art should be able to understand this
A little files also may include other required information.
Then, in step 110, at least information of a specific node is extracted in circuit from the first restrictive condition shelves,
In the present embodiment, which is that will produce the point of huge retardation in logic synthesis, such as have in circuit high negative
Carry the node ... etc. of number.Then, in step 112, the relevant information of the specific node extracted is stored as one
Two restrictive condition shelves.
Then, in step 114, according to circuit program shelves, standard delay format shelves, the first restrictive condition shelves, Yi Ji
Two restrictive condition shelves carry out static timing analysis, with generated in step 116,118 respectively static timing analysis report 116 with
And standard delay format shelves after update.Specifically, it is according to circuit program shelves, standard delay lattice in static timing analysis
Formula shelves (or update after standard delay format shelves) and the first restrictive condition shelves carry out static timing analysis, in step
Static timing analysis report is generated in 116；And according at least to standard delay format shelves and the second restrictive condition shelves in step
Standard delay format shelves after update are generated in rapid 118, wherein after update in standard delay format shelves the specific node retardation
Retardation than the specific node in the standard delay format shelves is small.In addition, in the present embodiment, in static timing analysis,
It is that the retardation of the specific node in the standard delay format shelves is set as zero or the specific node close to after entity design
Retardation, to generate standard delay format shelves after update, for example, assuming that the standard delay format caused by step 106
In shelves, it is 100 microseconds (micro-second) for retardation described in a node with high load number, is then updating
Afterwards in standard delay format shelves, retardation described in this node with high load number is to be modified to 0 or approach
Retardation after entity design (after clock pulse tree synthesis (clock tree synthesis)), such as 2 nanoseconds
(nano-second)。
Then, in the step 120, an advance electricity is carried out using standard delay format shelves after circuit program shelves and update
Road post layout simulation is to generate an analog result, so that engineer judges that used multiple restrictive conditions are in a step 102
The no situation for having input error.
It is noted that above-mentioned steps 102~120 are carried out before carrying out entity design, and therefore, Ke Yijin
Whether have whether multiple restrictive conditions used in potential problems, especially step 102 have input in early discovery circuit design
The situation of mistake occurs, and is impacted to avoid the time-histories table to product.
In addition, step 102 shown in Fig. 1~120 complete after, can carry out again entity design, circuit automatic placement, with
And simulated after circuit layout ... and hindfoot portions is waited to design.
Referring to FIG. 2, Fig. 2 is the flow chart of the digital circuit design method of another embodiment according to the present invention.In this reality
It applies in example, digital circuit design method is after being loaded by one computer/processor by a system, to pass through multiple program instruction modules
Performed, with reference to figure 2, the flow of digital circuit design method is described below.
First, in step 202, it is designed according to a Method at Register Transfer Level and synthesizes behaviour with multiple restrictive conditions to carry out logic
Make, to generate a circuit program shelves, one first standard delay format shelves and a restrictive condition in step 204,206,208
Shelves.Above-mentioned restrictive condition is to be inputted by engineer, and it is clock pulse input point mainly to contain which pin, and the frequency of clock pulse
Etc. contents that rate is how many ...；Circuit program shelves are a kind of file formats of description circuit, logically can coincidence register
Transmitting stage designs, and can meet in sequential the restrictive condition that engineer is inputted；First standard delay format shelves are mainly retouched
State the retardation ... etc. between retardation and the interconnection circuit between each circuit unit；Restrictive condition shelves are mainly retouched
The content of above-mentioned restrictive condition, and the information about the node with high load number in circuit are stated.It is noted that
It is above-mentioned to only relate to of the invention disclose about content described in restrictive condition, the first standard delay format shelves and restrictive condition shelves
The part of content, those skilled in the art should be able to understand these files and also may include other required information.
In addition, also will produce one second standard delay format shelves (step in the logic synthetic operation that step 202 is carried out
210), wherein the content of the second standard delay format shelves is similar to standard delay lattice after the update described in the embodiment of Fig. 1
Formula shelves, that is, the retardation ratio of a specific node in the second standard delay format shelves (for example, node with high load number)
The retardation of the specific node is small in first standard delay format shelves, is by the first standard delay format shelves in the present embodiment
In the specific node retardation be set as zero or close to after entity design the specific node retardation, to generate the second standard
Delay format shelves, for example, assuming that in the first standard delay format shelves, retouched for a node with high load number
The retardation stated is 100 microseconds, then in the second standard delay format shelves, prolongs described in this node with high load number
Late amount be can be modified to 0 or close to after entity design (for example, by using clock pulse tree synthesis after) retardation, such as 2 how
Second.
Then, in the step 212, according to circuit program shelves, restrictive condition shelves and first or second standard delay format
Shelves carry out static timing analysis, in step 214 to generate static timing analysis report.
Then, in the step 216, an advance circuit is carried out using circuit program shelves and the second standard delay format shelves
Post layout simulation to generate an analog result, for engineer judge in step 202 used in multiple restrictive conditions whether
There is the situation of input error.
It is noted that above-mentioned steps 202~216 are carried out before carrying out entity design, and therefore, Ke Yijin
Whether have whether multiple restrictive conditions used in potential problems, especially step 202 have input in early discovery circuit design
The situation of mistake occurs, and is impacted to avoid the time-histories table to product.
In addition, step 202 shown in Fig. 2~216 complete after, can carry out again entity design, circuit automatic placement, with
And simulated after circuit layout ... and hindfoot portions is waited to design.
The brief summary present invention is to carry out entity in the digital circuit design method of the present invention and relevant system
It is simulated after just first carrying out advance circuit layout before design, to shift to an earlier date the upper possible mistake of discovery circuit design, to avoid to production
The time-histories table of product impacts.
The foregoing is merely presently preferred embodiments of the present invention, all equivalent changes done according to the claims in the present invention with repair
Decorations should all belong to the covering scope of the present invention.
Claims (14)
1. a kind of digital circuit design method, includes：
Before carrying out entity design：
According to a Method at Register Transfer Level design with multiple restrictive conditions come carry out logic synthesize at least generate a circuit program shelves,
One standard delay format shelves and one first restrictive condition shelves；
At least information of a specific node is extracted in circuit from the first restrictive condition shelves, to generate one second restrictive condition
Shelves；
Standard delay format shelves after a update are generated according at least to the standard delay format shelves and the second restrictive condition shelves,
Wherein after the update in standard delay format shelves the retardation of the specific node than the specific node in the standard delay format shelves
Retardation it is small；And
It is simulated after carrying out an advance circuit layout using standard delay format shelves after the circuit program shelves and the update.
2. digital circuit design method as described in claim 1, the wherein specific node are to have high load number in circuit
Node.
3. digital circuit design method as described in claim 1, wherein the step of generating standard delay format shelves after the update
Include：
The retardation of the specific node in the standard delay format shelves is set as zero or the specific node close to after entity design
Retardation, to generate standard delay format shelves after the update.
4. digital circuit design method as described in claim 1, has additionally comprised：
Judge whether multiple restrictive condition is wrong according to the analog result simulated after the advance circuit layout.
5. a kind of system for carrying out Design of Digital Circuit is loaded into the system to execute via computer；The system includes first
Program instruction module, the second program instruction module, third program instruction module and fourth program instructions module；
Before carrying out entity design：
The first program instruction module, according to a Method at Register Transfer Level design with multiple restrictive conditions come carry out logic synthesize down to
A circuit program shelves, a standard delay format shelves and one first restrictive condition shelves are generated less；
The second program instruction module extracts in circuit at least information of a specific node from the first restrictive condition shelves,
To generate one second restrictive condition shelves；
The third program instruction module, one is generated more according at least to the standard delay format shelves and the second restrictive condition shelves
Standard delay format shelves after new, wherein after the update in standard delay format shelves the retardation of the specific node than the standard delay
The retardation of the specific node is small in format shelves；And
The fourth program instructions module carries out one in advance using standard delay format shelves after the circuit program shelves and the update
It is simulated after circuit layout.
6. system as claimed in claim 5, the wherein specific node are the node with high load number in circuit.
7. system as claimed in claim 5 wherein generates standard delay format shelves after the update in third program instruction module
The step of include：
The retardation of the specific node in the standard delay format shelves is set as zero or the specific node close to after entity design
Retardation, to generate standard delay format shelves after the update.
8. a kind of digital circuit design method, includes：
Before carrying out entity design：
According to a Method at Register Transfer Level design with multiple restrictive conditions come carry out logic synthesize at least generate a circuit program shelves,
One first standard delay format shelves and one second standard delay format shelves, wherein for an at least specific node in circuit, it should
The retardation of the specific node is prolonged than the specific node in the first standard delay format shelves in second standard delay format shelves
It measures late small；And
It is simulated after carrying out an advance circuit layout using the circuit program shelves and the second standard delay format shelves.
9. digital circuit design method as claimed in claim 8, the wherein specific node are to have high load number in circuit
Node.
10. digital circuit design method as claimed in claim 8, wherein the step of generating the second standard delay format shelves is wrapped
Contain：
The retardation of the specific node in the first standard delay format shelves is set as zero or this is specific close to after entity design
The retardation of node, to generate the second standard delay format shelves.
11. digital circuit design method as claimed in claim 8, has additionally comprised：
Judge whether multiple restrictive condition is wrong according to the analog result simulated after the advance circuit layout.
12. a kind of system for carrying out Design of Digital Circuit is loaded into the system to execute via computer；The system includes first
Program instruction module and the second program instruction module；
Before carrying out entity design：
The first program instruction module, according to a Method at Register Transfer Level design with multiple restrictive conditions come carry out logic synthesize down to
A circuit program shelves, one first standard delay format shelves and one second standard delay format shelves are generated less, wherein being directed to circuit
In an at least specific node, the retardation of the specific node is than first standard delay format in the second standard delay format shelves
The retardation of the specific node is small in shelves；And
It is electric in advance to carry out one using the circuit program shelves and the second standard delay format shelves for the second program instruction module
Road post layout simulation.
13. Design of Digital Circuit system as claimed in claim 12, the wherein specific node are to have high load in circuit
Several nodes.
14. Design of Digital Circuit system as claimed in claim 12, wherein generating second mark in the first program instruction module
The step of quasi- delay format shelves includes：
The retardation of the specific node in the first standard delay format shelves is set as zero or this is specific close to after entity design
The retardation of node, to generate the second standard delay format shelves.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410495863.0A CN105447215B (en) | 2014-09-24 | 2014-09-24 | Digital circuit design method and relevant system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410495863.0A CN105447215B (en) | 2014-09-24 | 2014-09-24 | Digital circuit design method and relevant system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105447215A CN105447215A (en) | 2016-03-30 |
| CN105447215B true CN105447215B (en) | 2018-07-27 |
Family
ID=55557388
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410495863.0A Active CN105447215B (en) | 2014-09-24 | 2014-09-24 | Digital circuit design method and relevant system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105447215B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107368643B (en) * | 2017-07-13 | 2020-12-01 | 湖南中易利华信息技术有限公司 | RTL-based module partitioning method and device and terminal equipment |
| TWI664546B (en) * | 2018-06-21 | 2019-07-01 | 瑞昱半導體股份有限公司 | Clock tree synthesis method |
| TWI739101B (en) * | 2019-05-07 | 2021-09-11 | 瑞昱半導體股份有限公司 | Ic design data base generating method and ic design method |
| CN112632880B (en) * | 2020-12-28 | 2023-04-14 | 芯华章科技股份有限公司 | Compiling method for logic system design, electronic device, and storage medium |
| CN113111622B (en) * | 2021-04-29 | 2023-01-31 | 上海阵量智能科技有限公司 | Circuit layout generation method and device, computer equipment and storage medium |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1776698A (en) * | 2005-11-29 | 2006-05-24 | 知亿科技股份有限公司 | Circuit design assisting method |
| CN103177145A (en) * | 2011-12-20 | 2013-06-26 | 国际商业机器公司 | Method and system of combination of multiple time sequence modes of integrated circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3953756B2 (en) * | 2001-07-12 | 2007-08-08 | 富士通株式会社 | Timing budget design method |
| US8056037B2 (en) * | 2007-09-24 | 2011-11-08 | International Business Machines Corporation | Method for validating logical function and timing behavior of a digital circuit decision |
-
2014
- 2014-09-24 CN CN201410495863.0A patent/CN105447215B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1776698A (en) * | 2005-11-29 | 2006-05-24 | 知亿科技股份有限公司 | Circuit design assisting method |
| CN103177145A (en) * | 2011-12-20 | 2013-06-26 | 国际商业机器公司 | Method and system of combination of multiple time sequence modes of integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105447215A (en) | 2016-03-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105447215B (en) | Digital circuit design method and relevant system | |
| JP5410414B2 (en) | Circuit emulation input and delay input multiplexing | |
| CN102866349B (en) | Integrated circuit testing method | |
| US10372841B2 (en) | Self-testing graphical component algorithm specification | |
| US10354042B2 (en) | Selectively reducing graph based analysis pessimism | |
| CN108830008A (en) | A kind of test method and test macro of standard cell lib full model | |
| TWI533154B (en) | Digital circuit design method and associated computer program product | |
| US20110107281A1 (en) | Tiered schematic-driven layout synchronization in electronic design automation | |
| CN108052769A (en) | Netlist emulation verification method and device | |
| US10489534B1 (en) | Support for multiple user defined assertion checkers in a multi-FPGA prototyping system | |
| CN104899076A (en) | Super-large-scale integrated circuit gate-level net list simulation acceleration method | |
| WO2014106038A1 (en) | Local clock skew optimization and incremental clock tree synthesis | |
| CN103150441A (en) | Software and hardware synergic simulation verification platform and construction method thereof | |
| US7254793B2 (en) | Latch modeling technique for formal verification | |
| CN107844678B (en) | Spice simulation method containing IP/Memory time sequence path | |
| CN109902318A (en) | The method and apparatus of generation standard delay formatted file | |
| CN113343629B (en) | Integrated circuit verification method, code generation method, system, device, and medium | |
| CN107784185B (en) | Method and device for extracting pseudo path in gate-level netlist and terminal equipment | |
| CN105701294A (en) | Method and system for realizing complex project modification of chips | |
| US20220327269A1 (en) | Computing device and method for detecting clock domain crossing violation in design of memory device | |
| JP2009223661A (en) | Verification support program, recording medium with the program recorded therein, verification support apparatus, and verification support method | |
| US9104829B2 (en) | Method of validating timing issues in gate-level simulation | |
| US20140325468A1 (en) | Storage medium, and generation apparatus for generating transactions for performance evaluation | |
| US8555228B2 (en) | Tool for glitch removal | |
| KR101683636B1 (en) | Mixing circuit simulation system and method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |