CN105701294A - Method and system for realizing complex project modification of chips - Google Patents
Method and system for realizing complex project modification of chips Download PDFInfo
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- CN105701294A CN105701294A CN201610021204.2A CN201610021204A CN105701294A CN 105701294 A CN105701294 A CN 105701294A CN 201610021204 A CN201610021204 A CN 201610021204A CN 105701294 A CN105701294 A CN 105701294A
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- G06F30/30—Circuit design
Abstract
The invention provides a method and system for realizing complex project modification of chips. The method comprises the following steps: searching an original register conversion-level circuit and an original gate-level netlist, and obtaining key signals mutually corresponding to the original register conversion-level circuit and the original gate-level netlist; modifying the key signal in the original register conversion-level circuit to generate a register conversion-level circuit 1; inserting a first register after the key signal of the register conversion-level circuit 1, and caching the result of modifying the key signal of the original register conversion-level circuit into the first register so as to generate a register conversion-level circuit 2; inserting a second register after the key signal of the original gate-level netlist so as to generate a gate-level netlist 1; obtaining a gate-level netlist 2 according to the register conversion-level circuit 2 and the gate-level netlist 1; and storing and/or outputting the register conversion-level circuit 1 and the gate-level netlist 2 so as to complete the complex projects modification of the chips. According to the method and system provided by the invention, the modification of target projects can be modified via least logic modification, and the re-design periods of the chips can be accelerated.
Description
Technical field
The present invention relates to network communication field, particularly relate to a kind of method and system realizing the amendment of chip complex engineering。
Background technology
At present, it is universal that the development of network technology and informationization are applied, and various hardware chips obtain and are increasingly widely applied。
Along with the development of science and technology, chip complexity is more and more higher, simultaneously, it is desirable to the R&D cycle of chip is shorter and shorter, so, to adapt to the speed of development in science and technology；Accordingly, in order to meet above-mentioned requirements, increasing chip is had to after chip development later stage or chip flow return to find chip defect, further makes engineering amendment and makes up。
Engineering is revised mainly for gate level netlist, the readability of gate level netlist is excessively poor, and complex optimization can be done based on register transfer level circuit when comprehensive, the engineering amendment of this complexity is typically all needs and adds in substantial amounts of combination logic or amendment part logic, the difficulty of this amendment has at least 2 points, first it is difficult to inside gate level netlist and signal corresponding in register transfer level circuit, next to that the amount of logic changed is a lot, the logic of impact is a lot, causing that engineering amendment is increasingly difficult to, the engineering amendment of some complexity even can not realize。
Summary of the invention
It is an object of the invention to provide a kind of method and system realizing the amendment of chip complex engineering。
One of for achieving the above object, the method realizing the amendment of chip complex engineering of an embodiment of the present invention includes:
Search original register transfer level circuit and original gate level netlist, obtain its mutually corresponding key signal；
Key signal in original register transfer level circuit is modified, generates register transfer level circuit 1；
After the key signal of described register transfer level circuit 1, insert the first depositor, by the amendment result cache after the key signal of original register transfer level circuit is modified to described first depositor, generate register transfer level circuit 2；
After the key signal of original gate level netlist, insert the second depositor, generate gate level netlist 1；
According to register transfer level circuit 2 and gate level netlist 1, obtain gate level netlist 2；
Preserve and/or output register switching stage circuit 1 and gate level netlist 2, complete the amendment of chip complex engineering。
Being expanded on further as an embodiment of the present invention, after " inserting the first depositor after the key signal of described register transfer level circuit 1, generate register transfer level circuit 2 ", described method also includes:
Gate level netlist 2a is generated according to described register transfer level circuit 2 coupling。
Being expanded on further as an embodiment of the present invention, " according to register transfer level circuit 2 and gate level netlist 1, obtain gate level netlist 2 " specifically includes:
According to gate level netlist 2a and gate level netlist 1, obtain the ECO script file of the original gate level netlist of coupling；
Original gate level netlist loads described ECO script file, obtains gate level netlist 2。
Being expanded on further as an embodiment of the present invention, described method also includes:
Adopt gate level netlist 2a and gate level netlist 1 described in Conformal software comparison, obtain the ECO script file of the original gate level netlist of coupling。
Being expanded on further as an embodiment of the present invention, after " preserving and/or export new register transfer level circuit and new gate level netlist ", described method also includes:
Described register transfer level circuit 1 and gate level netlist 2 are carried out formal verification, after being identified through checking, completes the amendment of chip complex engineering。
One of for achieving the above object, the system realizing the amendment of chip complex engineering of an embodiment of the present invention, described system includes: data acquisition module, for searching original register transfer level circuit and original gate level netlist, obtains its mutually corresponding key signal；
Data processing module, for the key signal in original register transfer level circuit is modified, generates register transfer level circuit 1；
After the key signal of described register transfer level circuit 1, insert the first depositor, by the amendment result cache after the key signal of original register transfer level circuit is modified to described first depositor, generate register transfer level circuit 2；
After the key signal of original gate level netlist, insert the second depositor, generate gate level netlist 1；
According to register transfer level circuit 2 and gate level netlist 1, obtain gate level netlist 2；
Storage output module, is used for preservation and/or output register switching stage circuit 1 and gate level netlist 2, completes the amendment of chip complex engineering。
Being expanded on further as an embodiment of the present invention, described data processing module is additionally operable to: generate gate level netlist 2a according to described register transfer level circuit 2 coupling。
Being expanded on further as an embodiment of the present invention, described data processing module is additionally operable to:
According to gate level netlist 2a and gate level netlist 1, obtain the ECO script file of the original gate level netlist of coupling；
Original gate level netlist loads described ECO script file, obtains gate level netlist 2。
Being expanded on further as an embodiment of the present invention, described data processing module is additionally operable to:
Adopt gate level netlist 2a and gate level netlist 1 described in Conformal software comparison, obtain the ECO script file of the original gate level netlist of coupling。
Being expanded on further as an embodiment of the present invention, described data processing module is additionally operable to:
Described register transfer level circuit 1 and gate level netlist 2 are carried out formal verification, after being identified through checking, completes the amendment of chip complex engineering。
Compared with prior art, the invention has the beneficial effects as follows: the present invention realizes the method and system of chip complex engineering amendment, by finding out key signal common on register transfer level circuit and gate level netlist, and after its key signal, increase the netlist that the generation of corresponding depositor is new respectively, produce engineering amendment script based on new netlist and apply to original gate level netlist, realize the amendment of chip complex engineering, purpose project amendment, the redesign cycle of speed-up chip is realized so that changing by minimum logic。
Accompanying drawing explanation
Fig. 1 is the flow chart of the method realizing the amendment of chip complex engineering in an embodiment of the present invention；
Fig. 2 a-2i is instantiation application schematic diagram in an embodiment of the present invention；
Fig. 3 is the module map of the system realizing the amendment of chip complex engineering in an embodiment of the present invention in embodiment。
Detailed description of the invention
Describe the present invention below with reference to detailed description of the invention shown in the drawings。But these embodiments are not limiting as the present invention, those of ordinary skill in the art is all contained in protection scope of the present invention according to the made structure of these embodiments, method or conversion functionally。
As it is shown in figure 1, the method realizing the amendment of chip complex engineering provided in one embodiment of the present invention, described method includes:
S1, search original register transfer level circuit and original gate level netlist, obtain the key signal of its correspondence。
In the concrete example of the present invention one, it is necessary to compare original register transfer level circuit and original gate level netlist respectively, search its common key signal needing amendment。
Described register transfer level circuit is generally referred to as RTL。
Describe in order to convenient below, lift a concrete example and describe in detail。
Shown in Fig. 2 a, 2b, Fig. 2 a is original register transfer level circuit；Fig. 2 b is original gate level netlist。
By comparison it can be seen that the key signal in original register transfer level circuit is " a ", key signal corresponding in original gate level netlist is " n4 "。
Further, the described method realizing the amendment of chip complex engineering also includes:
S2, the key signal in original register transfer level circuit is modified, generate register transfer level circuit 1。
Continue above-mentioned example, during the amendment of this engineering, it is necessary to " in0&&in1 " in described key signal " a " is revised as " in0 | | in1 "。
Shown in Fig. 2 c, 2d, Fig. 2 c is the logical code that the key signal " a " in original register transfer level circuit is modified；Fig. 2 d is the register transfer level circuit 1 generated after the key signal in original register transfer level circuit is revised。
By Fig. 2 d it can be seen that in amended register transfer level circuit, key signal " a ", be revised as by " in0&&in1 " " in0 | | in1 ", it is not described in detail at this。
Further, the described method realizing the amendment of chip complex engineering also includes:
S3, after the key signal of described register transfer level circuit 1, insert the first depositor, by in the amendment result cache after the key signal of original register transfer level circuit is modified to described first depositor, generate register transfer level circuit 2 and generate register transfer level circuit 2；
Continue above-mentioned example, traditional register transfer level circuit modification, after key signal " a " is modified by it, it may proceed to affect signal b and output out0, after namely the place's signal in register transfer level circuit being fixed, circuit after this amendment signal is all affected, so, in amendment register transfer level circuitry processes, it is necessary to change substantial amounts of logic circuit, amendment complexity, and error probability is high。
In the present invention, the first depositor is inserted after the key signal of register transfer level circuit 1, and by the amendment result cache after the key signal of original register transfer level circuit is modified to described first depositor, when formal verification, the amendment of key signal is only affected the circuit before the first newly inserted depositor, so, in amendment process, it is possible to reduce the location revision of logic circuit, complicated logic Modification process is simplified, meanwhile, successful probability is higher。Continue above-mentioned example, and shown in Fig. 2 e, Fig. 2 e is newly-generated register transfer level circuit 2。
By Fig. 2 e it can be seen that after the key signal " a " of original register transfer level circuit is modified, its amendment result represents with " aF1 ", and individual described in " aF1 " write in the first depositor, generate new register transfer level circuit 2。
Further, after described step S3, described method also includes:
S4, according to described register transfer level circuit 2 coupling generate gate level netlist 2a。
Continue above-mentioned example, and shown in Fig. 2 g, Fig. 2 g is newly-generated gate level netlist 2a。
It should be noted that the software according to register transfer level circuit production gate level netlist has multiple, it is not described in detail at this。
Further, the described method realizing the amendment of chip complex engineering also includes:
S5, after the key signal of original gate level netlist, insert the second depositor, generate gate level netlist 1；
Continue above-mentioned example, and shown in Fig. 2 f, Fig. 2 f is newly-generated gate level netlist 1。
Contrast original gate level netlist as shown in Figure 2 b, and newly-generated gate level netlist 1 is known:
In newly-generated gate level netlist 1 increase logical code "
//addforECO
SDFFQ_X1M_A9TUaF1_reg(.D(n4),.SI(1′b0),.SE(1′b0),.CK(ClockCore),.Q(aF1));”
Further, described method also includes:
S6, according to register transfer level circuit 2 and gate level netlist 1, obtain gate level netlist 2。
In the present invention one preferred implementation, described step S5 specifically includes:
M1, according to gate level netlist 2a and gate level netlist 1, obtain the ECO script file of the original gate level netlist of coupling。
It should be noted that, in above-mentioned example, it is possible to adopt gate level netlist 2a and gate level netlist 1 described in various ways comparison, in the preferred embodiment of the present invention, adopt gate level netlist 2a and gate level netlist 1 described in Conformal software comparison, obtain the ECO script file of the original gate level netlist of coupling。
Continue above-mentioned example, and shown in Fig. 2 h, Fig. 2 h is the ECO script file of the gate level netlist that coupling is original。
M2, on original gate level netlist, load described ECO script file, obtain gate level netlist 2。
Continue above-mentioned example, and shown in Fig. 2 i, Fig. 2 i is the gate level netlist 2 that will eventually obtain。
Further, described method also includes:
S7, preservation and/or output register switching stage circuit 1 and gate level netlist 2, complete the amendment of chip complex engineering。
In the present invention one preferred implementation, described step S6 also includes:
Described register transfer level circuit 1 and gate level netlist 2 are carried out formal verification, after being identified through checking, completes the amendment of chip complex engineering, be not described in detail at this。
It should be noted that, in above-mentioned example, part steps in S1 to S7 can carry out simultaneously, can also successively carrying out, its acquisition order does not affect final amendment result, in the concrete example of the present invention, for convenient explanation, adopt step S1 ~ S7 that the whole method realizing the amendment of chip complex engineering is elaborated, but in actual application, above-mentioned part steps execution sequence is successively not concrete to be limited。
Such as: step S2 and step S5 can successively carry out, it is also possible to carries out simultaneously, is not described in detail at this。
Shown in Fig. 3, in one embodiment of the present invention, multiplex system in same framework, described system includes: data acquisition module 100, data processing module 200, storage output module 300。
Data acquisition module 100, for searching original register transfer level circuit and original gate level netlist, obtains the key signal of its correspondence。
In the concrete example of the present invention one, data acquisition module 100 needs to compare original register transfer level circuit and original gate level netlist respectively, searches its common key signal needing amendment。
Described register transfer level circuit is generally referred to as RTL。
Describe in order to convenient below, lift a concrete example and describe in detail。
Shown in Fig. 2 a, 2b, Fig. 2 a is original register transfer level circuit；Fig. 2 b is original gate level netlist。
By comparison it can be seen that the key signal in original register transfer level circuit is " a ", key signal corresponding in original gate level netlist is " n4 "。
Further, in an embodiment of the present invention, data processing module 200, for the key signal in original register transfer level circuit is modified, generates register transfer level circuit 1。
Continue above-mentioned example, during the amendment of this engineering, it is necessary to " in0&&in1 " in described key signal " a " is revised as " in0 | | in1 "。
Shown in Fig. 2 c, 2d, Fig. 2 c is the logical code that the key signal " a " in original register transfer level circuit is modified；Fig. 2 d is the register transfer level circuit 1 generated after the key signal in original register transfer level circuit is revised。
By Fig. 2 d it can be seen that in amended register transfer level circuit, key signal " a ", be revised as by " in0&&in1 " " in0 | | in1 ", it is not described in detail at this。
Further, in an embodiment of the present invention, data processing module 200 is additionally operable to: insert the first depositor after the key signal of described register transfer level circuit 1, by in the amendment result cache after the key signal of original register transfer level circuit is modified to described first depositor, generate register transfer level circuit 2 and generate register transfer level circuit 2；
Continue above-mentioned example, traditional register transfer level circuit modification, after key signal " a " is modified by it, it may proceed to affect signal b and output out0, after namely the place's signal in register transfer level circuit being fixed, circuit after this amendment signal is all affected, so, in amendment register transfer level circuitry processes, it is necessary to change substantial amounts of logic circuit, amendment complexity, and error probability is high。
In the present invention, the first depositor is inserted after the key signal of register transfer level circuit 1, and by the amendment result cache after the key signal of original register transfer level circuit is modified to described first depositor, when formal verification, the amendment of key signal is only affected the circuit before the first newly inserted depositor, so, in amendment process, it is possible to reduce the location revision of logic circuit, complicated logic Modification process is simplified, meanwhile, successful probability is higher。Continue above-mentioned example, and shown in Fig. 2 e, Fig. 2 e is newly-generated register transfer level circuit 2。
By Fig. 2 e it can be seen that after the key signal " a " of original register transfer level circuit is modified, its amendment result represents with " aF1 ", and individual described in " aF1 " write in the first depositor, generate new register transfer level circuit 2。
Further, in an embodiment of the present invention, data processing module 200 is additionally operable to: generate gate level netlist 2a according to described register transfer level circuit 2 coupling。
Continue above-mentioned example, and shown in Fig. 2 g, Fig. 2 g is newly-generated gate level netlist 2a。
It should be noted that the software according to register transfer level circuit production gate level netlist has multiple, it is not described in detail at this。
Further, in an embodiment of the present invention, data processing module 200 is additionally operable to: insert the second depositor after the key signal of original gate level netlist, generates gate level netlist 1；
Continue above-mentioned example, and shown in Fig. 2 f, Fig. 2 f is newly-generated gate level netlist 1。
Contrast original gate level netlist as shown in Figure 2 b, and newly-generated gate level netlist 1 is known:
In newly-generated gate level netlist 1 increase logical code "
//addforECO
SDFFQ_X1M_A9TUaF1_reg(.D(n4),.SI(1′b0),.SE(1′b0),.CK(ClockCore),.Q(aF1));”
Further, in an embodiment of the present invention, data processing module 200 is additionally operable to: according to register transfer level circuit 2 and gate level netlist 1, obtains gate level netlist 2。
In the present invention one preferred implementation, data processing module 200 specifically for:
According to gate level netlist 2a and gate level netlist 1, obtain the ECO script file of the original gate level netlist of coupling。
It should be noted that, in above-mentioned example, data processing module 200 can adopt gate level netlist 2a described in various ways comparison and gate level netlist 1, in the preferred embodiment of the present invention, adopt gate level netlist 2a and gate level netlist 1 described in Conformal software comparison, obtain the ECO script file of the original gate level netlist of coupling。
Continue above-mentioned example, and shown in Fig. 2 h, Fig. 2 h is the ECO script file of the gate level netlist that coupling is original。
Data processing module 200 also loads described ECO script file on original gate level netlist, obtains gate level netlist 2。
Continue above-mentioned example, and shown in Fig. 2 i, Fig. 2 i is the gate level netlist 2 that will eventually obtain。
Further, in an embodiment of the present invention, storage output module 300 is used for: preserves and/or output register switching stage circuit 1 and gate level netlist 2, completes the amendment of chip complex engineering。
In the present invention one preferred implementation, data processing module is additionally operable to:
Described register transfer level circuit 1 and gate level netlist 2 are carried out formal verification, after being identified through checking, completes the amendment of chip complex engineering, be not described in detail at this。
In sum, the method and system realizing the amendment of chip complex engineering of the present invention, by finding out key signal common on register transfer level circuit and gate level netlist, and after its key signal, increase the netlist that the generation of corresponding depositor is new respectively, produce engineering amendment script based on new netlist and apply to original gate level netlist, thus realizing the amendment of chip complex engineering。
The present invention by adding one-level depositor after key signal, formal verification tool is so made not need the substantial amounts of combination logic after analysis of key signal and register logical, and only need the logic before analysis of key signal, the amount of logic making formal verification tool analysis greatly reduces, and then obtains engineering modification；The present invention after key signal, insert corresponding depositor after the gate level netlist obtained and original gate level netlist except differing except a cycle in sequential, its logical operations behavior is identical, and then then the engineering obtained based on the gate level netlist after conversion amendment script can be applied directly on original gate level netlist, thus realize the complex engineering amendment of original netlist；Simultaneously, owing to the present invention adds corresponding depositor after key signal, so making when formal verification tool is revised in analysis project, the register number related to is relatively fewer, the combination logic quantity of its correspondence analysis is also relatively fewer, show that the probability of engineering modification is higher；And then realize purpose project amendment, the redesign cycle of speed-up chip with minimum logic change。
For convenience of description, it is divided into various module to be respectively described with function when describing apparatus above。Certainly, the function of each module can be realized in same or multiple softwares and/or hardware when implementing the application。
As seen through the above description of the embodiments, those skilled in the art is it can be understood that can realize by the mode of general hardware platform to the application。Based on such understanding, the part that prior art is contributed by the technical scheme of the application substantially in other words embodies with the form of the product of switch。
Device embodiments described above is merely schematic, the wherein said module illustrated as separating component can be or may not be physically separate, the parts shown as module can be or may not be physical module, namely may be located at a place, or can also be distributed on multiple mixed-media network modules mixed-media。Some or all of module therein can be selected according to the actual needs to realize the purpose of present embodiment scheme。Those of ordinary skill in the art, when not paying creative work, are namely appreciated that and implement。
The application can described in the general context of computer executable instructions, for instance program module。Usually, program module includes performing particular task or realizing the routine of particular abstract data type, program, object, assembly, data structure etc.。The application can also be put into practice in a distributed computing environment, in these distributed computing environment, the remote processing devices connected by communication network perform task。In a distributed computing environment, program module may be located in the local and remote computer preservation medium including preservation equipment。
It is to be understood that, although this specification is been described by according to embodiment, but not each embodiment only comprises an independent technical scheme, this narrating mode of description is only for clarity sake, description should be made as a whole by those skilled in the art, technical scheme in each embodiment through appropriately combined, can also form other embodiments that it will be appreciated by those skilled in the art that。
The a series of detailed description of those listed above is only for illustrating of the feasibility embodiment of the present invention; they also are not used to limit the scope of the invention, and all should be included within protection scope of the present invention without departing from the skill of the present invention equivalent implementations made of spirit or change。
Claims (10)
1. the method realizing the amendment of chip complex engineering, it is characterised in that described method includes:
Search original register transfer level circuit and original gate level netlist, obtain its mutually corresponding key signal；
Key signal in original register transfer level circuit is modified, generates register transfer level circuit 1；
After the key signal of described register transfer level circuit 1, insert the first depositor, by the amendment result cache after the key signal of original register transfer level circuit is modified to described first depositor, generate register transfer level circuit 2；
After the key signal of original gate level netlist, insert the second depositor, generate gate level netlist 1；
According to register transfer level circuit 2 and gate level netlist 1, obtain gate level netlist 2；
Preserve and/or output register switching stage circuit 1 and gate level netlist 2, complete the amendment of chip complex engineering。
2. the method realizing the amendment of chip complex engineering according to claim 1, it is characterised in that
After " inserting the first depositor after the key signal of described register transfer level circuit 1, generate register transfer level circuit 2 ", described method also includes:
Gate level netlist 2a is generated according to described register transfer level circuit 2 coupling。
3. the method realizing the amendment of chip complex engineering according to claim 2, it is characterised in that " according to register transfer level circuit 2 and gate level netlist 1, obtain gate level netlist 2 " specifically includes:
According to gate level netlist 2a and gate level netlist 1, obtain the ECO script file of the original gate level netlist of coupling；
Original gate level netlist loads described ECO script file, obtains gate level netlist 2。
4. the method realizing the amendment of chip complex engineering according to claim 3, it is characterised in that
Described method also includes:
Adopt gate level netlist 2a and gate level netlist 1 described in Conformal software comparison, obtain the ECO script file of the original gate level netlist of coupling。
5. the method realizing the amendment of chip complex engineering according to any one of claim 1-4, it is characterised in that after " preserving and/or export new register transfer level circuit and new gate level netlist ", described method also includes:
Described register transfer level circuit 1 and gate level netlist 2 are carried out formal verification, after being identified through checking, completes the amendment of chip complex engineering。
6. the system realizing the amendment of chip complex engineering, it is characterised in that described system includes:
Data acquisition module, for searching original register transfer level circuit and original gate level netlist, obtains its mutually corresponding key signal；
Data processing module, for the key signal in original register transfer level circuit is modified, generates register transfer level circuit 1；
After the key signal of described register transfer level circuit 1, insert the first depositor, by the amendment result cache after the key signal of original register transfer level circuit is modified to described first depositor, generate register transfer level circuit 2；
After the key signal of original gate level netlist, insert the second depositor, generate gate level netlist 1；
According to register transfer level circuit 2 and gate level netlist 1, obtain gate level netlist 2；
Storage output module, is used for preservation and/or output register switching stage circuit 1 and gate level netlist 2, completes the amendment of chip complex engineering。
7. the system realizing the amendment of chip complex engineering according to claim 6, it is characterised in that described data processing module is additionally operable to: generate gate level netlist 2a according to described register transfer level circuit 2 coupling。
8. the system realizing the amendment of chip complex engineering according to claim 7, it is characterised in that described data processing module is additionally operable to:
According to gate level netlist 2a and gate level netlist 1, obtain the ECO script file of the original gate level netlist of coupling；
Original gate level netlist loads described ECO script file, obtains gate level netlist 2。
9. the system realizing the amendment of chip complex engineering according to claim 8, it is characterised in that described data processing module is additionally operable to:
Adopt gate level netlist 2a and gate level netlist 1 described in Conformal software comparison, obtain the ECO script file of the original gate level netlist of coupling。
10. the system realizing the amendment of chip complex engineering according to any one of claim 6-9, it is characterised in that described data processing module is additionally operable to:
Described register transfer level circuit 1 and gate level netlist 2 are carried out formal verification, after being identified through checking, completes the amendment of chip complex engineering。
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| CN112329362A (en) * | 2020-10-30 | 2021-02-05 | 盛科网络（苏州）有限公司 | Universal method, device and storage medium for complex engineering modification of chips |
| CN112347722A (en) * | 2020-11-12 | 2021-02-09 | 盛科网络（苏州）有限公司 | Method and device for efficiently evaluating chip Feed-through flow stage number |
| CN113919254A (en) * | 2021-11-13 | 2022-01-11 | 奇捷科技(深圳)有限公司 | Register transfer level signal mapping construction method, device, equipment and storage medium |
| CN116542191A (en) * | 2023-07-06 | 2023-08-04 | 奇捷科技(深圳)有限公司 | Logic correction method, device, equipment and storage medium |
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| CN113919254B (en) * | 2021-11-13 | 2022-05-31 | 奇捷科技(深圳)有限公司 | Register transfer level signal mapping construction method, device, equipment and storage medium |
| CN116542191A (en) * | 2023-07-06 | 2023-08-04 | 奇捷科技(深圳)有限公司 | Logic correction method, device, equipment and storage medium |
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