CN113901745A - Chip testing method and device, electronic equipment and computer readable storage medium - Google Patents
Chip testing method and device, electronic equipment and computer readable storage medium Download PDFInfo
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Abstract
The embodiment of the application provides a chip testing method and device, electronic equipment and a computer readable storage medium, and relates to the field of integrated circuit design. The method comprises the following steps: determining original simulation data of a chip to be tested and a target test module of the chip to be tested; determining target simulation data corresponding to the target test module in the original simulation data; and testing the target test module according to the target simulation data. The embodiment of the application provides a new chip testing method, the software design of the testing method is independent of the logic function development of the chip, the consistency of the chip from design to release is ensured, the development efficiency of the chip is improved, and the reliability of the chip testing result is ensured by adopting a mode of simulation data post-processing.
Description
Technical Field
The present disclosure relates to the field of integrated circuit design technologies, and in particular, to a chip testing method and apparatus, an electronic device, and a computer-readable storage medium.
Background
SoC (System on Chip) Chip is a Chip of integrated circuit, which can effectively reduce the development cost of electronic/information System products, shorten the development period, and improve the competitiveness of the products, and is the most important product development mode to be adopted in the future industry. With the occurrence of application scenes such as big data processing, cloud computing, deep learning and the like, higher and more diversified requirements are put forward on the development and design of the SoC chip.
In the prior art, a technician usually develops and designs a logic function of an SoC chip and a test unit simultaneously by using a hardware design language based on an RTL (Register Transfer Level) Level model, wherein a code of the test unit is mixed with a logic function code of the chip, but the test unit is usually used only in a test stage, and the code of the test unit is usually removed in a chip compiling and issuing stage, so that the test scheme causes redundancy of a chip design code and reduces chip development efficiency.
Disclosure of Invention
The embodiment of the application provides a chip testing method and device, electronic equipment and a computer readable storage medium, which are used for solving the technical problem of low chip development efficiency.
According to an aspect of an embodiment of the present application, there is provided a chip testing method, including:
determining original simulation data of a chip to be tested and a target test module of the chip to be tested;
determining target simulation data corresponding to the target test module in the original simulation data;
and testing the target test module according to the target simulation data.
Optionally, the determining the original simulation data of the chip to be tested and the target test module of the chip to be tested include:
simulating a chip to be tested based on a preset simulator to generate original simulation data;
and receiving the indication information, and determining the target test module of the chip to be tested according to the indication information.
Optionally, the determining target simulation data corresponding to the target test module in the original simulation data includes:
and inquiring the original simulation data based on the label of the original simulation data, and determining the target simulation data corresponding to the target test module.
Optionally, the testing the target test module according to the target simulation data includes:
performing performance analysis processing on the target simulation data to obtain performance data; the performance data represents the statistical characteristics of the target simulation data;
a test result of the target test module is determined based on the performance data.
Optionally, the performing performance analysis on the target simulation data to obtain performance data includes:
determining the data type of the target simulation data;
and performing performance analysis on the target simulation data based on the data type to obtain performance data.
Optionally, the determining the data type of the target simulation data includes:
judging whether the target simulation data has corresponding target comparison data;
when the target simulation data does not have corresponding target comparison data, determining that the data type of the target simulation data is a first data type;
and when the target simulation data has corresponding target comparison data, determining that the data type of the target simulation data is a second data type.
Optionally, the performing performance analysis on the target simulation data based on the data type to obtain performance data includes:
when the data type is a first data type, carrying out cluster statistics on the numerical value of the target simulation data to generate performance data;
and when the data type is a second data type, comparing the target simulation data with the target comparison data to obtain the discrimination information of the target simulation data, and performing cluster statistics on the discrimination information to generate performance data.
Optionally, the determining a test result of the target test module based on the performance data includes:
acquiring a target threshold corresponding to target simulation data;
the test results are determined based on the target threshold and the performance data.
According to another aspect of the embodiments of the present application, there is also provided a chip testing apparatus, including:
the first determining module is used for determining original simulation data of the chip to be tested and a target testing module of the chip to be tested;
the second determining module is used for determining target simulation data corresponding to the target testing module in the original simulation data;
and the test module is used for testing the target test module according to the target simulation data.
Optionally, the first determining module is configured to:
simulating a chip to be tested based on a preset simulator to generate original simulation data;
and receiving the indication information, and determining the target test module of the chip to be tested according to the indication information.
Optionally, the second determining module is configured to:
and inquiring the original simulation data based on the label of the original simulation data, and determining the target simulation data corresponding to the target test module.
Optionally, the test module includes:
the analysis unit is used for carrying out performance analysis processing on the target simulation data to obtain performance data; the performance data represents the statistical characteristics of the target simulation data;
and the determining unit is used for determining the test result of the target test module based on the performance data.
In another possible implementation manner, the analysis unit includes:
the determining subunit is used for determining the data type of the target simulation data;
and the analysis subunit is used for performing performance analysis on the target simulation data based on the data type to obtain performance data.
Optionally, the determining subunit is configured to:
judging whether the target simulation data has corresponding target comparison data;
when the target simulation data does not have corresponding target comparison data, determining that the data type of the target simulation data is a first data type;
and when the target simulation data has corresponding target comparison data, determining that the data type of the target simulation data is a second data type.
Optionally, the analysis subunit is configured to:
when the data type is a first data type, carrying out cluster statistics on the numerical value of the target simulation data to generate performance data;
and when the data type is a second data type, comparing the target simulation data with the target comparison data to obtain the discrimination information of the target simulation data, and performing cluster statistics on the discrimination information to generate performance data.
Optionally, the determining unit is configured to:
acquiring a target threshold corresponding to target simulation data;
the test results are determined based on the target threshold and the performance data.
According to another aspect of an embodiment of the present application, there is provided an electronic apparatus including:
the device comprises a memory, a processor and a computer program stored on the memory, wherein the processor executes the computer program to realize the steps of the method shown in the first aspect of the embodiment of the application.
According to a further aspect of embodiments of the present application, there is provided a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the method as set forth in the first aspect of embodiments of the present application.
According to an aspect of embodiments of the present application, there is provided a computer program product comprising a computer program that, when executed by a processor, performs the steps of the method illustrated in the first aspect of embodiments of the present application.
The technical scheme provided by the embodiment of the application has the following beneficial effects:
compared with the technical scheme that the logic function and the test unit of the chip are developed and designed simultaneously based on the hardware design language in the prior art, the method and the device for testing the chip test data improve the flexibility and comprehensiveness of data analysis and improve the reliability of the chip test result by testing the simulation data in a post-processing mode; meanwhile, the test scheme provided by the embodiment of the application is independent of the logic function development of the chip, the consistency of the chip from design to release is ensured, and compared with the prior art that the code of the test unit and the logic function code of the chip need to be separated in the compiling and releasing stages of the chip, the test method provided by the application cannot cause the redundancy of the chip design code, the difficulty and the error rate of the chip development are reduced, and the development efficiency of the chip is effectively improved.
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In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the description of the embodiments of the present application will be briefly described below.
Fig. 1 is a schematic view of an application scenario of a chip testing scheme according to an embodiment of the present application;
fig. 2 is a schematic flowchart of a chip testing method according to an embodiment of the present disclosure;
fig. 3 is a schematic flowchart of deterministic performance data in a chip testing method according to an embodiment of the present disclosure;
fig. 4 is a schematic flowchart illustrating a process of determining a data type in a chip testing method according to an embodiment of the present application;
fig. 5 is a schematic flowchart of deterministic performance data in a chip testing method according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram of a system architecture for implementing a chip test scheme according to an embodiment of the present application;
fig. 7 is a schematic flowchart of another chip testing method according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of a chip testing apparatus according to an embodiment of the present disclosure;
fig. 9 is a schematic structural diagram of a chip testing electronic device according to an embodiment of the present disclosure.
Detailed Description
Embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the embodiments set forth below in connection with the drawings are exemplary descriptions for explaining technical solutions of the embodiments of the present application, and do not limit the technical solutions of the embodiments of the present application.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the terms "comprises" and/or "comprising," when used in this specification in connection with embodiments of the present application, specify the presence of stated features, information, data, steps, operations, elements, and/or components, but do not preclude the presence or addition of other features, information, data, steps, operations, elements, components, and/or groups thereof, as embodied in the art. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. The term "and/or" as used herein indicates at least one of the items defined by the term, e.g., "a and/or B" indicates either an implementation as "a", or an implementation as "a and B".
To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
SoC (System-on-a-Chip) is called a System-on-Chip, also called System-on-Chip, meaning that it is a product, an integrated circuit with a dedicated target, which contains the complete System and has the entire content of embedded software. Meanwhile, the method is a technology for realizing the whole process from the determination of system functions to the software/hardware division and completing the design. From a narrow sense, the method is the chip integration of the core of an information system, and integrates key components of the system on one chip; in a broad sense, the SoC is a micro-miniature system, and if the CPU (central processing unit) is the brain, the SoC is a system including the brain, the heart, the eyes, and the hands. The academics at home and abroad generally tend to define SoC as integrating a microprocessor, an analog IP (Interrupt Priority register) core, a digital IP core and a memory (or off-chip memory control interface) on a single chip, which is usually custom-made or standard product oriented to a specific application.
With the development of design and manufacturing technologies, integrated circuit designs have evolved from the integration of transistors to the integration of logic gates, and now to the integration of IP, i.e., SoC design technologies. The SoC can effectively reduce the development cost of electronic/information system products, shorten the development period, and improve the competitiveness of the products, and is the most important product development mode to be adopted in the future industry.
In digital circuit design, RTL (register-transfer level) is an abstract model of a synchronous digital circuit, which is determined according to the flow of digital signals between logic units such as hardware registers, memories, combinational logic devices, and buses, and the logical algebraic operation thereof. Digital integrated circuits are typically designed using hardware description languages, for example, when designing SoC chips, designers often do not design at the transistor level, but rather engineer at a higher level of abstraction (hierarchy). In a hardware description language, a designer need only declare registers (as if variables were declared in a computer programming language), and then use operators like conditions (if... the. Such a level of design as described above is often referred to as a register transfer level of design.
With the occurrence of application scenes such as big data processing, cloud computing, deep learning and the like, higher and more diversified requirements are put forward on the development and design of the SoC chip. In the prior art, technicians usually develop and design logic functions and test units of an SoC chip simultaneously by using a hardware design language based on an RTL level model, wherein codes of the test units are mixed with logic function codes of the SoC chip, and the applicant finds that the above manner has the following problems:
1. the test unit is usually used only in the test stage, and the code of the test unit is usually removed in the compiling and releasing stage of the SoC chip, so that the redundancy of the design code of the SoC chip is caused, and the development efficiency of the SoC chip is reduced.
2. At each stage from the design to the release of the SoC chip, the RTL design code of the SoC chip cannot keep consistency, and the RTL design cannot be concentrated on the logic function of the SoC chip, so that the error rate of the development of the SoC chip is high.
3. The test unit based on RTL design can only verify the current simulation data of the SoC chip, when a temporary function needs to be added to the test unit, the latest simulation data needs to be extracted and analyzed based on the re-simulation of the updated test unit, the test scheme has low adaptability and high development cost.
The chip testing method, the chip testing device, the electronic equipment and the computer readable storage medium provided by the application aim to solve the technical problems in the prior art.
The embodiment of the application provides a chip testing method, which can be realized by a terminal or a server. The terminal or the server related to the embodiment of the application can be independent of the logic function development work of the SoC chip, and the SoC chip is tested in a mode of carrying out post-processing on the acquired simulation data, so that the technical scheme of the embodiment of the application can achieve the effects of effectively improving the development efficiency of the SoC chip and improving the flexibility and comprehensiveness of the test.
The technical solutions of the embodiments of the present application and the technical effects produced by the technical solutions of the present application will be described below through descriptions of several exemplary embodiments. It should be noted that the following embodiments may be referred to, referred to or combined with each other, and the description of the same terms, similar features, similar implementation steps and the like in different embodiments is not repeated.
As shown in fig. 1, the chip testing method of the present application may be applied to the scenario shown in fig. 1, specifically, the simulation system 101 simulates a chip to be tested to obtain original simulation data, a tester instructs a target test module for the chip to be tested based on the user terminal 102, and after obtaining the original simulation data and the target test module, the server 103 determines target simulation data corresponding to the target test module in the original simulation data, and then performs a test for the target test module based on the target simulation data, and outputs a test result.
In the scenario shown in fig. 1, the chip testing method may be performed in a server, or in another scenario, may be performed in a terminal.
Those skilled in the art will understand that the "terminal" used herein may be a Mobile phone, a tablet computer, a PDA (Personal Digital Assistant), an MID (Mobile Internet Device), etc.; a "server" may be implemented as a stand-alone server or as a server cluster comprised of multiple servers.
An embodiment of the present application provides a chip testing method, as shown in fig. 2, the method includes the following steps:
s201, determining original simulation data of a chip to be tested and a target test module of the chip to be tested.
The chip to be tested may be an SoC chip, and the SoC chip may include a plurality of IP core modules, where an IP core module is an integrated circuit, a device, or a component that is designed in advance and even verified to have a certain function.
In general, the IP core module may be a CPU, a DSP (Digital Signal processor), a DRAM (Dynamic Random Access Memory), an SRAM (Static Random Access Memory), a PCI bus (Peripheral Component Interconnect standard), a standard interface, a network unit, a compiler, a coder/decoder, an analog device module, and the like. The IP core module may be used as a test module of a chip to be tested.
Specifically, the terminal or the server for performing the chip test may determine the target test module from the plurality of test modules of the chip to be tested based on the instruction of the user.
In some embodiments, a terminal or a server for chip testing may obtain the stored original simulation data of the chip to be tested from a preset database.
In other embodiments, the terminal or the server for chip testing may collect the original simulation data of the chip to be tested directly from the simulator, and the specific collection process will be described in detail below.
S202, determining target simulation data corresponding to the target test module in the original simulation data.
The target simulation data is obtained by simulating the logic function of the target test module. For example, in practical applications, when the target test module is a CPU, the corresponding target simulation data may be a branch prediction result, a service response time, and the like; when the target test module is a bus, the corresponding target simulation data may be throughput, channel utilization, and the like.
In some embodiments, the corresponding relationship between the original simulation data and each test module may be established in advance, and then the target simulation data corresponding to the target test module may be determined based on the corresponding relationship.
In other embodiments, the target simulation data corresponding to the target test module may be determined based on the label information of the raw simulation data, and the specific determination process will be described in detail below.
And S203, testing the target test module according to the target simulation data.
One or more target simulation data may be provided. Each target test module corresponds to at least one type of target simulation data.
Specifically, when there is one type of target simulation data, the target test module may be tested based on the target simulation data to obtain a test result; when the target simulation data are various, the target test module corresponding to the target simulation data can be tested based on the target simulation data, and then the test result for the target test module is obtained according to the test data corresponding to the target simulation data.
Compared with the technical scheme that the logic function and the test unit of the chip are developed and designed simultaneously based on the hardware design language in the prior art, the method and the device for testing the chip test data improve the flexibility and comprehensiveness of data analysis and improve the reliability of the chip test result by testing the simulation data in a post-processing mode; meanwhile, the test scheme provided by the embodiment of the application is independent of the logic function development of the chip, the consistency of the chip from design to release is ensured, and compared with the prior art that the code of the test unit and the logic function code of the chip need to be separated in the compiling and releasing stages of the chip, the test method provided by the application cannot cause the redundancy of the chip design code, the difficulty and the error rate of the chip development are reduced, and the development efficiency of the chip is effectively improved.
A possible implementation manner is provided in the embodiment of the present application, where the determining the original simulation data of the chip to be tested and the target test module of the chip to be tested in step S201 includes:
(1) and simulating the chip to be tested based on a preset simulator to generate original simulation data.
Specifically, the logic function of the chip to be tested may be simulated based on a simulator.
The chip to be tested is developed based on a hardware description language; VHDL (Very High-Speed Integrated Circuit hardware Description Language) and Verilog HDL (a hardware Description Language used for digital system modeling of various abstract design levels from the algorithm level, gate level to the switch level) are two of the most popular hardware Description languages currently.
In the embodiment of the present application, taking the hardware description language is Verilog as an example, the corresponding preset simulator may be a VCS (Compiled Verilog simulator), and the VCS combines a beat algorithm and an event-driven algorithm, has the characteristics of high performance, large scale and high precision, and is suitable for various stages from behavioral level, RTL to Sign-Off and the like.
Among other things, VCS can provide industry-leading performance and capacity while supporting a whole set of advanced debugging, defect finding, coverage, verification planning, and assertion technologies. Its debugging technique can understand the verification methodology and provide for the debugging of random constraints. The multi-core technology of the VCS can run design, test platform, assertion and debugging functions on a plurality of multi-core machines in parallel, improves the verification speed by 2 times, and shortens the verification time. The Partition compilation (Partition compiler) flow of the VCS just recompiles the modified code, shortening the iterative compilation cycle of the user by as much as 10 times. The VCS can also provide a whole set of comprehensive diagnosis tools including simulation memory consumption and simulation time analysis, interactive constraint debugging, intelligent recording and the like, and helps a user to quickly analyze problems. The VCS can support native low Power consumption simulation and UPF (Unified Power Format) Format, and can provide innovative voltage perception verification technology and position defects in modern low Power consumption design on the basis of the existing complete debugging means and high-performance simulation. The VCS has a built-in debugging and visualization environment, supports all popular design and Verification languages, including Verilog, VHDL, systemveilog (a language for hardware design and Verification based on Verilog language), VMM (virtual Machine monitor), UVM (Universal Verification Methodology), and other methodologies, and can help users deliver high-quality designs.
Specifically, the source code of the chip to be tested, i.e., the Verilog HDL source code, can be compiled and linked based on the VCS simulator to generate an executable file, and a simulation waveform can be obtained through the executable file. VCS can incorporate a Verdi (an advanced solution for debugging digital circuit designs) automated debugging platform to achieve waveform visualization. In addition, the VCS may also obtain raw simulation data via the UCLI interface.
(2) And receiving the indication information, and determining the target test module of the chip to be tested according to the indication information.
The indication information may be input by a user based on a mouse, a keyboard, a touch screen, or other peripheral of a terminal or a server for performing a chip test, and is used to indicate a target test module specified by the user.
Specifically, interface element components corresponding to icons or character identifications of a chip to be tested and a test module can be displayed on an interactive interface of a terminal or a server for chip testing, and then indication information is generated based on a trigger operation of a user so as to determine a target test module from each test module; wherein the triggering operation of the user may comprise at least one of:
dragging or moving the interface element component to an operation within a preset range of the current interface;
clicking operation aiming at the interface element component;
and inputting the identification of the interface element component in the preset input control.
In some embodiments, the chip to be tested and the icons of the test modules included in the chip to be tested may be presented in the preset interactive interface in the form of a list component, and a user may perform a click operation on the list component to select a target test module from the test modules.
According to the embodiment of the application, the logic function of the chip to be tested is simulated through the simulator, the original simulation data is generated, then the target test module is determined based on the indication information of the user, so that the post-processing operation is carried out on the original simulation data, compared with the prior art, the scheme for testing the current simulation data by adopting the hardware design language based on the RTL is adopted, the test is carried out in the mode of the post-processing analysis of the simulation data, the chip test is more flexible and comprehensive, and the reliability of the test result is higher.
A possible implementation manner is provided in this embodiment of the present application, where the determining, in the step S202, target simulation data corresponding to the target test module in the original simulation data includes:
and inquiring the original simulation data based on the label of the original simulation data, and determining the target simulation data corresponding to the target test module.
The label of the original simulation data can represent the test module corresponding to the data.
Specifically, the terminal or the server for chip testing may display the original simulation data and the icon or the text identifier of the corresponding tag in the form of an interface element component in a preset interactive interface, and then perform query on each original simulation data based on an input operation of a user for the interface element component to determine the target simulation data.
In some embodiments, the original simulation data and the name identifier of the test module corresponding to the original simulation data may be presented in the preset interactive interface in the form of a list component, and a user may click on the list component to select target simulation data corresponding to a target test module from the original simulation data.
In this embodiment, another possible implementation manner is provided, and the step S203 of testing the target test module according to the target simulation data includes:
(1) performing performance analysis processing on the target simulation data to obtain performance data; the performance data characterizes statistical characteristics of the target simulation data.
In some embodiments, a terminal or a server for performing chip testing may directly perform clustering processing on target simulation data, and analyze the target simulation data to obtain performance data of a corresponding target testing module.
In another embodiment, a terminal or a server for chip testing may first determine a data type of target simulation data, then perform analysis processing on the target simulation data based on the data type, and confirm to obtain performance data of a corresponding target test module; the specific steps will be described in detail below.
Another possible implementation manner is provided in the embodiment of the present application, as shown in fig. 3, the performing performance analysis on the target simulation data to obtain performance data includes:
a. the data type of the target simulation data is determined.
In the embodiment of the application, the target simulation data is classified firstly, and the data type of the target simulation data is confirmed, so that the subsequent data analysis and statistics work can be facilitated, and the performance data can have multi-dimensional data characteristics.
In an embodiment of the present application, a further possible implementation manner is provided, as shown in fig. 4, the determining a data type of the target simulation data includes:
a1, judging whether the target simulation data has corresponding target comparison data.
Specifically, whether corresponding target comparison data exists may be determined by querying from a preset database based on a tag of the target simulation data. Wherein the label of the target simulation data may characterize the simulation type.
In the embodiment of the application, taking a target test module as an example of a CPU, a database of tags of target simulation data and corresponding comparison data may be pre-constructed; when the target simulation data is branch prediction data, the corresponding label is a branch prediction instruction, and the target simulation data can be inquired in a preset database based on the branch prediction instruction to obtain corresponding target comparison data as a branch prediction result; when the target simulation data has a response time of 10ms, the corresponding label is "response time", and the target simulation data can be queried from a preset database based on the "response time", and corresponding target comparison data does not exist.
a2, when the target simulation data does not have corresponding target comparison data, determining the data type of the target simulation data as a first data type.
In this embodiment, taking the target test module as the CPU as an example, when the target simulation data has a response time of 10ms, the corresponding tag is "response time", and the target simulation data may be determined to be the first data type if the target simulation data is queried from a preset database based on the "response time" and no corresponding target comparison data exists.
a3, when the target simulation data has corresponding target comparison data, determining the data type of the target simulation data as the second data type.
In this embodiment, taking the target test module as the CPU as an example, when the target simulation data is branch prediction data, the corresponding tag is a "branch prediction instruction", and the target comparison data obtained by querying from a preset database based on the "branch prediction instruction" is a branch prediction result, and the type of the target simulation data is determined to be the second data type.
The Branch Prediction (Branch Prediction) is a data processing method for solving pipeline failure caused by processing a Branch instruction (if-then-else), and the CPU determines the proceeding direction of a program Branch, thereby being capable of accelerating the operation speed. The branch instruction usually has two paths of subsequent execution branches, when the corresponding branch prediction data is 'not token', the next JMP (jump instruction in computer assembly language, the instruction must specify the target address of the branch) instruction is skipped, and the execution is continued; and when the corresponding branch prediction data is 'taken', executing the JMP instruction, and jumping to another program memory for execution.
b. And performing performance analysis on the target simulation data based on the data type to obtain performance data.
Specifically, in this embodiment, taking the target test module as the CPU as an example, when the target simulation data is branch prediction data, the corresponding label is a "branch prediction instruction", and the target comparison data obtained by querying from a preset database based on the "branch prediction instruction" is a branch prediction result, and the type of the target simulation data is determined to be the second data type. When the target comparison data corresponding to the branch prediction instruction can be 'taken', if the target simulation data is 'taken', the CPU branch prediction is successful, and the obtained comparison result is 'prediction success'; if the target simulation data is 'nottkaten', the CPU branch prediction is failed, and the obtained corresponding comparison result is 'prediction failure'. Performance data such as a branch prediction failure rate or a branch prediction success rate of the corresponding CPU may be obtained based on the comparison result.
In another embodiment, taking the target test module as the CPU as an example, when the target simulation data has a response time of 10ms, the corresponding tag is "response time", the target simulation data can be queried from a preset database based on the "response time", and if there is no corresponding target comparison data, the target simulation data can be determined to be the first data type. At this time, performance data such as an average response time may be determined based on the above response time.
In an embodiment of the present application, a further possible implementation manner is provided, as shown in fig. 5, the performing performance analysis on the target simulation data based on the data type to obtain the performance data includes:
b1, when the data type is the first data type, clustering the numerical value of the target simulation data to generate performance data.
Specifically, in an embodiment, taking the target test module as the CPU as an example, when the target simulation data includes response times of 10ms, 8ms and 12ms, the corresponding tag is "response time", the target simulation data may be queried from a preset database based on the "response time", and if there is no corresponding target comparison data, it may be determined that the target simulation data is of the first data type. When the performance data is the average response time, the average value can be calculated based on the response time of the target simulation data of the same type, that is, the average value of 10ms, 8ms and 12ms is calculated to be 10ms, and the obtained performance data is the average response time of 10 ms.
b2, when the data type is the second data type, comparing the target simulation data with the target comparison data to obtain the discrimination information of the target simulation data, and performing cluster statistics on the discrimination information to generate the performance data.
Specifically, in an embodiment, taking the target test module as the CPU as an example, when the target simulation data is branch prediction data, a corresponding label is a "branch prediction instruction", and the target comparison data obtained by querying from a preset database based on the "branch prediction instruction" is a branch prediction result, and the type of the target simulation data is determined to be the second data type. When the target comparison data corresponding to the branch prediction instruction can be 'taken', if the target simulation data is 'taken', the CPU branch prediction is successful, and the obtained comparison result is 'prediction success'; if the target simulation data is 'nottkaten', the CPU branch prediction is failed, and the obtained corresponding comparison result is 'prediction failure'. When the performance data is the branch prediction failure rate, it may be determined that the corresponding comparison result is "prediction success" 4 times and "prediction failure" 1 time based on each target simulation data, and then the performance data may be obtained as the branch prediction failure rate of 20%.
(2) A test result of the target test module is determined based on the performance data.
In an embodiment of the present application, a further possible implementation manner is provided, where the determining a test result of the target test module based on the performance data includes:
a. acquiring a target threshold corresponding to target simulation data;
b. the test results are determined based on the target threshold and the performance data.
Specifically, the terminal or the server for chip prediction may query a target threshold corresponding to the target simulation data based on a preset database, and may determine the target threshold corresponding to the target simulation data based on a corresponding relationship between the simulation data and the threshold.
In an embodiment, taking the target test module as the CPU as an example, when the target simulation data includes response times of 10ms, 8ms and 12ms, the corresponding label is "response time", the target simulation data may be queried from a preset database based on the "response time", and if there is no corresponding target comparison data, the target simulation data may be determined to be the first data type. When the performance data is the average response time, the average value can be calculated based on the response time of the target simulation data of the same type, that is, the average value of 10ms, 8ms and 12ms is calculated to be 10ms, and the obtained performance data is the average response time of 10 ms. When the target threshold corresponding to the performance data is determined to be 15ms, and the average response time 10ms is smaller than 15ms, the test result can be obtained that the average response time of the CPU is normal.
In another embodiment, taking the target test module as the CPU as an example, when the target simulation data is branch prediction data, the corresponding tag is a "branch prediction instruction", and the target comparison data obtained by querying from a preset database based on the "branch prediction instruction" is a branch prediction result, and the type of the target simulation data is determined to be the second data type. When the target comparison data corresponding to the branch prediction instruction can be 'taken', if the target simulation data is 'taken', the CPU branch prediction is successful, and the obtained comparison result is 'prediction success'; if the target simulation data is 'nottkaten', the CPU branch prediction is failed, and the obtained corresponding comparison result is 'prediction failure'. When the performance data is the branch prediction failure rate, it may be determined that the corresponding comparison result is "prediction success" 4 times and "prediction failure" 1 time based on each target simulation data, and then the performance data may be obtained as the branch prediction failure rate of 20%. When the target threshold corresponding to the performance data is determined to be 10%, the branch prediction failure rate is 20% at the time and is greater than the target threshold, the prediction result can be obtained as that the CPU branch prediction failure rate is abnormal.
For better understanding of the above chip testing method, an example of the chip testing method of the present application is described in detail below with reference to fig. 6 and 7:
as shown in fig. 6, which is a schematic diagram of an architecture diagram of a chip testing system, the chip testing system may include a simulation module 601 and a data processing module 602, specifically, the simulation module 601 may first obtain a logic function code of a chip to be tested, and then simulate the logic function code, so as to generate original simulation data and input the original simulation data into the data processing module 602 for processing. The chip testing method comprises the following steps:
s701, the simulation module 601 simulates the chip to be tested based on a preset simulator to generate original simulation data.
Specifically, the logic function of the chip to be tested may be simulated based on a simulator. The simulation module 601 first compiles and links a source code of a chip to be tested, namely a Verilog HDL source code, based on a VCS simulator to generate an executable file, and a simulation waveform can be obtained through the executable file. The Verdi automatic debugging platform can be combined on the basis of the VCS to realize the visualization of waveforms, and original simulation data can be acquired through a UCLI interface.
S702, the data processing module 602 receives the indication information, and determines a target test module of the chip to be tested according to the indication information.
The indication information may be input by a user based on peripheral devices of the chip testing system such as a mouse, a keyboard, a touch screen, and the like, and is used for indicating the target testing module specified by the user.
S703, the data processing module 602 queries the original simulation data based on the label of the original simulation data, and determines the target simulation data corresponding to the target test module.
The label of the original simulation data can represent the test module corresponding to the data.
Specifically, the data processing module 602 may display the original simulation data and the interface element component corresponding to the icon or text identifier of the corresponding tag in the preset interactive interface in the form of the interface element component, and then query the original simulation data based on the input operation of the user for the interface element component to determine the target simulation data.
S704, the data processing module 602 determines the data type of the target simulation data; the data types include a first data type and a second data type.
In this embodiment, the data processing module 602 classifies the target simulation data and determines the data type thereof, so that subsequent data analysis and statistics work can be facilitated, and the performance data can have multidimensional data characteristics.
S705, when the data type is a first data type, performing cluster statistics on the numerical value of the target simulation data to generate performance data; wherein the performance data characterizes statistical characteristics of the target simulation data.
Specifically, in an embodiment, taking the target test module as the CPU as an example, when the target simulation data includes response times of 10ms, 8ms and 12ms, the corresponding tag is "response time", the target simulation data may be queried from a preset database based on the "response time", and if there is no corresponding target comparison data, it may be determined that the target simulation data is of the first data type. When the performance data is the average response time, the average value can be calculated based on the response time of the target simulation data of the same type, that is, the average value of 10ms, 8ms and 12ms is calculated to be 10ms, and the obtained performance data is the average response time of 10 ms.
And S706, comparing the target simulation data with the target comparison data to obtain the discrimination information of the target simulation data when the data type is the second data type, and performing cluster statistics on the discrimination information to generate performance data.
Specifically, in an embodiment, taking the target test module as the CPU as an example, when the target simulation data is branch prediction data, a corresponding label is a "branch prediction instruction", and the target comparison data obtained by querying from a preset database based on the "branch prediction instruction" is a branch prediction result, and the type of the target simulation data is determined to be the second data type. When the target comparison data corresponding to the branch prediction instruction can be 'taken', if the target simulation data is 'taken', the CPU branch prediction is successful, and the obtained comparison result is 'prediction success'; if the target simulation data is 'nottkaten', the CPU branch prediction is failed, and the obtained corresponding comparison result is 'prediction failure'. When the performance data is the branch prediction failure rate, it may be determined that the corresponding comparison result is "prediction success" 4 times and "prediction failure" 1 time based on each target simulation data, and then the performance data may be obtained as the branch prediction failure rate of 20%.
S707, the data processing module 602 obtains a target threshold corresponding to the target simulation data, and determines a test result based on the target threshold and the performance data.
Specifically, the data processing module 602 may query a target threshold corresponding to the target simulation data based on a preset database, and may determine a target threshold corresponding to the target simulation data based on a corresponding relationship between the simulation data and the threshold.
Compared with the technical scheme that the logic function and the test unit of the chip are developed and designed simultaneously based on the hardware design language in the prior art, the method and the device for testing the chip test data improve the flexibility and comprehensiveness of data analysis and improve the reliability of the chip test result by testing the simulation data in a post-processing mode; meanwhile, the test scheme provided by the embodiment of the application is independent of the logic function development of the chip, the consistency of the chip from design to release is ensured, and compared with the prior art that the code of the test unit and the logic function code of the chip need to be separated in the compiling and releasing stages of the chip, the test method provided by the application cannot cause the redundancy of the chip design code, the difficulty and the error rate of the chip development are reduced, and the development efficiency of the chip is effectively improved.
An embodiment of the present application provides a chip testing apparatus, and as shown in fig. 8, the chip testing apparatus 80 may include: a first determination module 801, a second determination module 802, and a test module 803; the first determining module 801 is configured to determine original simulation data of a chip to be tested and a target testing module of the chip to be tested;
a second determining module 802, configured to determine target simulation data corresponding to the target testing module in the original simulation data;
and the test module 803 is used for testing the target test module according to the target simulation data.
Compared with the technical scheme that the logic function and the test unit of the chip are developed and designed simultaneously based on the hardware design language in the prior art, the method and the device for testing the chip test data improve the flexibility and comprehensiveness of data analysis and improve the reliability of the chip test result by testing the simulation data in a post-processing mode; meanwhile, the test scheme provided by the embodiment of the application is independent of the logic function development of the chip, the consistency of the chip from design to release is ensured, and compared with the prior art that the code of the test unit and the logic function code of the chip need to be separated in the compiling and releasing stages of the chip, the test method provided by the application cannot cause the redundancy of the chip design code, the difficulty and the error rate of the chip development are reduced, and the development efficiency of the chip is effectively improved.
In an embodiment of the present application, a possible implementation manner is provided, where the first determining module 801 is configured to:
simulating a chip to be tested based on a preset simulator to generate original simulation data;
and receiving the indication information, and determining the target test module of the chip to be tested according to the indication information.
In an embodiment of the present application, a possible implementation manner is provided, where the second determining module 802 is configured to:
and inquiring the original simulation data based on the label of the original simulation data, and determining the target simulation data corresponding to the target test module.
In an embodiment of the present application, a possible implementation manner is provided, and the test module 803 includes:
the analysis unit is used for carrying out performance analysis processing on the target simulation data to obtain performance data; the performance data represents the statistical characteristics of the target simulation data;
and the determining unit is used for determining the test result of the target test module based on the performance data.
A possible implementation manner is provided in an embodiment of the present application, where the analysis unit includes:
the determining subunit is used for determining the data type of the target simulation data;
and the analysis subunit is used for performing performance analysis on the target simulation data based on the data type to obtain performance data.
In an embodiment of the present application, a possible implementation manner is provided, where the determining subunit is configured to:
judging whether the target simulation data has corresponding target comparison data;
when the target simulation data does not have corresponding target comparison data, determining that the data type of the target simulation data is a first data type;
and when the target simulation data has corresponding target comparison data, determining that the data type of the target simulation data is a second data type.
In an embodiment of the present application, a possible implementation manner is provided, and the analysis subunit is configured to:
when the data type is a first data type, carrying out cluster statistics on the numerical value of the target simulation data to generate performance data;
and when the data type is a second data type, comparing the target simulation data with the target comparison data to obtain the discrimination information of the target simulation data, and performing cluster statistics on the discrimination information to generate performance data.
In an embodiment of the present application, a possible implementation manner is provided, where the determining unit is configured to:
acquiring a target threshold corresponding to target simulation data;
the test results are determined based on the target threshold and the performance data.
The apparatus of the embodiment of the present application may execute the method provided by the embodiment of the present application, and the implementation principle is similar, the actions executed by the modules in the apparatus of the embodiments of the present application correspond to the steps in the method of the embodiments of the present application, and for the detailed functional description of the modules of the apparatus, reference may be specifically made to the description in the corresponding method shown in the foregoing, and details are not repeated here.
The embodiment of the application provides an electronic device, which comprises a memory, a processor and a computer program stored on the memory, wherein the processor executes the computer program to realize the steps of the chip testing method, and compared with the prior art, the method can realize the following steps: compared with the technical scheme that the logic function and the test unit of the chip are developed and designed simultaneously based on the hardware design language in the prior art, the method and the device for testing the chip test data improve the flexibility and comprehensiveness of data analysis and improve the reliability of the chip test result by testing the simulation data in a post-processing mode; meanwhile, the test scheme provided by the embodiment of the application is independent of the logic function development of the chip, the consistency of the chip from design to release is ensured, and compared with the prior art that the code of the test unit and the logic function code of the chip need to be separated in the compiling and releasing stages of the chip, the test method provided by the application cannot cause the redundancy of the chip design code, the difficulty and the error rate of the chip development are reduced, and the development efficiency of the chip is effectively improved.
In an alternative embodiment, an electronic device is provided, as shown in fig. 9, the electronic device 90 shown in fig. 9 comprising: a processor 901 and a memory 903. Wherein the processor 901 is coupled to the memory 903, such as via a bus 902. Optionally, the electronic device 90 may further include a transceiver 904, and the transceiver 904 may be used for data interaction between the electronic device and other electronic devices, such as transmission of data and/or reception of data. It should be noted that the transceiver 904 is not limited to one in practical applications, and the structure of the electronic device 90 is not limited to the embodiment of the present application.
The Processor 901 may be a CPU (Central Processing Unit), a general-purpose Processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other Programmable logic device, a transistor logic device, a hardware component, or any combination thereof. Which may implement or perform the various illustrative logical blocks, modules, and circuits described in connection with the disclosure. The processor 901 may also be a combination of computing functions, e.g., comprising one or more microprocessors, DSPs, and microprocessors, among others.
The Memory 903 may be a ROM (Read Only Memory) or other type of static storage device that can store static information and instructions, a RAM (Random Access Memory) or other type of dynamic storage device that can store information and instructions, an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact disk Read Only Memory) or other optical disk storage, optical disk storage (including Compact disk, laser disk, optical disk, digital versatile disk, blu-ray disk, etc.), a magnetic disk storage medium, other magnetic storage devices, or any other medium that can be used to carry or store a computer program and that can be Read by a computer, without limitation.
The memory 903 is used for storing computer programs for executing the embodiments of the present application, and the processor 901 controls the execution. The processor 901 is adapted to execute a computer program stored in the memory 903 to implement the steps shown in the aforementioned method embodiments.
Among them, electronic devices include but are not limited to: mobile terminals such as mobile phones, notebook computers, PADs, etc. and fixed terminals such as digital TVs, desktop computers, etc.
Embodiments of the present application provide a computer-readable storage medium, on which a computer program is stored, and when being executed by a processor, the computer program may implement the steps and corresponding contents of the foregoing method embodiments.
Embodiments of the present application provide a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device realizes the following when executed:
determining original simulation data of a chip to be tested and a target test module of the chip to be tested;
determining target simulation data corresponding to the target test module in the original simulation data;
and testing the target test module according to the target simulation data.
It should be understood that, although each operation step is indicated by an arrow in the flowchart of the embodiment of the present application, the implementation order of the steps is not limited to the order indicated by the arrow. In some implementation scenarios of the embodiments of the present application, the implementation steps in the flowcharts may be performed in other sequences as desired, unless explicitly stated otherwise herein. In addition, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on an actual implementation scenario. Some or all of these sub-steps or stages may be performed at the same time, or each of these sub-steps or stages may be performed at different times, respectively. In a scenario where execution times are different, an execution sequence of the sub-steps or the phases may be flexibly configured according to requirements, which is not limited in the embodiment of the present application.
The foregoing is only an optional implementation manner of a part of implementation scenarios in this application, and it should be noted that, for those skilled in the art, other similar implementation means based on the technical idea of this application are also within the protection scope of the embodiments of this application without departing from the technical idea of this application.
Claims (11)
1. A method for testing a chip, comprising:
determining original simulation data of a chip to be tested and a target test module of the chip to be tested;
determining target simulation data corresponding to the target test module in the original simulation data;
and testing the target test module according to the target simulation data.
2. The method for testing chips according to claim 1, wherein the determining the original simulation data of the chip to be tested and the target test module of the chip to be tested comprises:
simulating the chip to be tested based on a preset simulator to generate the original simulation data;
and receiving indication information, and determining a target test module of the chip to be tested according to the indication information.
3. The chip testing method according to claim 1, wherein the determining of the target simulation data corresponding to the target testing module in the original simulation data comprises:
and inquiring the original simulation data based on the label of the original simulation data, and determining target simulation data corresponding to the target test module.
4. The chip testing method according to claim 1, wherein the testing the target testing module according to the target simulation data comprises:
performing performance analysis processing on the target simulation data to obtain performance data; the performance data characterizes statistical characteristics of the target simulation data;
determining a test result of the target test module based on the performance data.
5. The chip testing method according to claim 4, wherein the performing performance analysis on the target simulation data to obtain performance data comprises:
determining the data type of the target simulation data;
and performing performance analysis on the target simulation data based on the data type to obtain performance data.
6. The chip testing method according to claim 5, wherein the determining the data type of the target simulation data comprises:
judging whether the target simulation data has corresponding target comparison data;
when the target simulation data does not have corresponding target comparison data, determining that the data type of the target simulation data is a first data type;
and when the target simulation data has corresponding target comparison data, determining that the data type of the target simulation data is a second data type.
7. The chip testing method according to claim 6, wherein the performing performance analysis on the target simulation data based on the data type to obtain performance data comprises:
when the data type is a first data type, performing cluster statistics on the numerical value of the target simulation data to generate the performance data;
and when the data type is a second data type, comparing the target simulation data with the target comparison data to obtain discrimination information of the target simulation data, and performing cluster statistics on the discrimination information to generate the performance data.
8. The chip testing method according to claim 4, wherein the determining the test result of the target test module based on the performance data comprises:
acquiring a target threshold corresponding to the target simulation data;
determining the test result based on the target threshold and the performance data.
9. A chip testing apparatus, comprising:
the device comprises a first determining module, a second determining module and a third determining module, wherein the first determining module is used for determining original simulation data of a chip to be tested and a target testing module of the chip to be tested;
the second determining module is used for determining target simulation data corresponding to the target testing module in the original simulation data;
and the test module is used for testing the target test module according to the target simulation data.
10. An electronic device comprising a memory, a processor and a computer program stored on the memory, characterized in that the processor executes the computer program to implement the steps of the method of any of claims 1 to 8.
11. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the chip testing method according to any one of claims 1 to 8.
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