CN106845004A - It is a kind of that system and method is built based on script for functional verification platform - Google Patents
It is a kind of that system and method is built based on script for functional verification platform Download PDFInfo
- Publication number
- CN106845004A CN106845004A CN201710081078.4A CN201710081078A CN106845004A CN 106845004 A CN106845004 A CN 106845004A CN 201710081078 A CN201710081078 A CN 201710081078A CN 106845004 A CN106845004 A CN 106845004A
- Authority
- CN
- China
- Prior art keywords
- script
- document
- verification platform
- information
- functional verification
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Logic Circuits (AREA)
Abstract
System and method is built based on script for functional verification platform the invention discloses a kind of, the system includes bus architecture information document module, internal register and ram modules, chip initiation control document module, automatized script module;By using automatized script, realization automatically completes building and running work for verification platform;By measured Avalon bus protocols design verification platform test order, the general readwrite tests of the design to being respectively based on Avalon buses is realized;The correct test for particular memory module is realized by using internal register and ram module informations document;The configuration to the initial authentication environment of different designs is realized by using chip initiation control document.The method is easy to implement, and flow is simple, efficient stable, can significantly shorten to the construction cycle that functional verification platform is built in the different designs based on Avalon buses, improves functional verification efficiency.
Description
Technical field
The present invention relates to IC design verifications field, specifically a kind of taking based on script for functional verification platform
Build system and method.
Background technology
At present, the exploitation based on FPGA is more and more, and the main FPGA suppliers of in the market are including Atera, Xilinx etc..
Avalon buses are the high-performance on-chip bus that Atera is provided.Because Avalon bus architectures are flexible, it is easy-to-use the advantages of, be based on
The design of Avalon buses is very more, and is that each design for being based on Avalon buses is required for one verification platform of exploitation to use
To carry out emulation testing to the register and ram modules inside design.
The content of the invention
Technical assignment of the invention is to provide a kind of builds system and method for functional verification platform based on script.
Technical assignment of the invention realizes in the following manner, and the system includes bus architecture information document module, interior
Portion's register and ram modules, chip initiation control document module, automatized script module;
Described bus architecture information document module completes to write according to the bus architecture based on Avalon buses;
Described internal register and the information document of ram modules completes to write according to the design based on Avalon buses;
Described chip initiation control document module completes to write according to the initial work flow based on Avalon buses;
Described automatized script module has various automatized scripts, and each automatized script generates pin comprising bus arbitration model
Sheet, test vector generation script, output information control script and Run Script.
Main equipment number that described bus architecture information document module contains comprising the used bus architecture of design, from
Equipment number, device id, the information of mode of operation.
Described internal register and ram modules is conducted interviews by using Avalon buses.
Described internal register and the information document of ram modules address, data comprising internal register and ram modules
Width, depth, reading/writing characteristics, read write command postpone and read and write the information of associated order.
Described automatized script uses perl/tcl/c-shell scripting languages.
Described bus arbitration model generation script generates the bus that checking needs by reading bus architecture information document
Arbitration model.
Described test vector generation script is generated for each by reading the information document of internal register and ram modules
The specific test vector of register and ram modules.
The described output information reserved control port of control script, carries out output letter according to actual needs in test process
The classification control of breath.
Described Run Script controls document to automatically generate for the design based on Avalon buses according to chip initiation
Initial environment configuration order and perform, perform test vector afterwards, complete test process and simultaneously generate test report.
The building method step based on script that this is used for functional verification platform is as follows:
1)Initial work process according to the design based on Avalon buses, including stable clock signal time, reset signals
Enable time, the information of internal each timely sequence of Special controlling signal list, design chips initialization control document;
2)Bus architecture information document is write according to the bus architecture type that design is used;
3)According to the design internal register based on Avalon buses and the address of ram modules, data width, depth, read-write spy
Levy, read write command postpones and read-write associated order information, writes information document;
4)Write automatized script, including bus arbitration model generation script, test vector generation script, output information control pin
Sheet and Run Script;The read write command ATL for meeting agreement timing requirements is write according to Avalon agreements simultaneously;
5)Script is generated using bus arbitration model generate the bus arbitration that checking needs by reading bus architecture information document
Model;
6)Using test vector generation script for the design internal register based on Avalon buses and the information text of ram modules
The test vector of shelves, the selected register to be tested of generation or ram modules;
7)The reserved control port of script is controlled using output information, setting current test needs output to the letter of log files
Breath classification;
8)The corresponding initialization command sequence of document structure tree is controlled according to the chip initiation of design using Run Script, is performed,
Testing results vector, generates test report afterwards, completes this test.
It is of the invention it is a kind of compared to the prior art system and method is built based on script for functional verification platform,
By using automatized script, realization automatically completes building and running work for verification platform;By measured
Avalon bus protocol design verification platform test orders, realize that the general read-write of the design to being respectively based on Avalon buses is surveyed
Examination;The correct test for particular memory module is realized by using internal register and ram module informations document;By using
Chip initiation control document realizes the configuration to the initial authentication environment of different designs.The method is easy to implement, and flow is simple,
Efficient stable, can significantly shorten to the construction cycle that functional verification platform is built in the different designs based on Avalon buses,
Improve functional verification efficiency.
Specific embodiment
Embodiment 1:
Configure this and system is built based on script for functional verification platform, the system includes bus architecture information document mould
Block, internal register and ram modules, chip initiation control document module, automatized script module;
Described bus architecture information document module completes to write according to the bus architecture based on Avalon buses;Described bus
Main equipment number, slave unit number, device id, work that Schema information document module contains comprising the used bus architecture of design
The information of operation mode.
Described internal register and the information document of ram modules completes to write according to the design based on Avalon buses;
Address of the described information document comprising internal register and ram modules, data width, depth, reading/writing characteristics, read write command prolong
Slow and read-write associated order information;Described internal register and ram modules is conducted interviews by using Avalon buses.
Described chip initiation control document module completes to compile according to the initial work flow based on Avalon buses
Write.
Described automatized script module has various automatized scripts, and each automatized script uses perl/tcl/c-shell
Scripting language, comprising bus arbitration model generation script, test vector generation script, output information control script and operation
Script;
Described bus arbitration model generation script generates the bus arbitration that checking needs by reading bus architecture information document
Model.
Described test vector generation script is generated for each by reading the information document of internal register and ram modules
The specific test vector of register and ram modules.
The described output information reserved control port of control script, carries out output letter according to actual needs in test process
The classification control of breath.
Described Run Script controls document to automatically generate for the design based on Avalon buses according to chip initiation
Initial environment configuration order and perform, perform test vector afterwards, complete test process and simultaneously generate test report.
The building method step based on script that this is used for functional verification platform is as follows:
1)Initial work process according to the design based on Avalon buses, including stable clock signal time, reset signals
Enable time, the information of internal each timely sequence of Special controlling signal list, design chips initialization control document;
2)Bus architecture information document is write according to the bus architecture type that design is used;
3)According to the design internal register based on Avalon buses and the address of ram modules, data width, depth, read-write spy
Levy, read write command postpones and read-write associated order information, writes information document;
4)Write automatized script, including bus arbitration model generation script, test vector generation script, output information control pin
Sheet and Run Script;The read write command ATL for meeting agreement timing requirements is write according to Avalon agreements simultaneously;It is above-mentioned automatic
It all can be to be multiplexed in design of the difference based on Avalon buses to change script and command module storehouse
5)Script is generated using bus arbitration model generate the bus arbitration that checking needs by reading bus architecture information document
Model;
6)Using test vector generation script for the design internal register based on Avalon buses and the information text of ram modules
The test vector of shelves, the selected register to be tested of generation or ram modules;
7)The reserved control port of script is controlled using output information, setting current test needs output to the letter of log files
Breath classification;
8)The corresponding initialization command sequence of document structure tree is controlled according to the chip initiation of design using Run Script, is performed,
Testing results vector, generates test report afterwards, completes this test.
By specific embodiment above, the those skilled in the art can readily realize the present invention.But should
Work as understanding, the present invention is not limited to above-mentioned several specific embodiments.On the basis of disclosed embodiment, the technology
The technical staff in field can be combined different technical characteristics, so as to realize different technical schemes.
Claims (10)
1. it is a kind of that system is built based on script for functional verification platform, it is characterised in that the system includes bus architecture
Information document module, internal register and ram modules, chip initiation control document module, automatized script module;
Described bus architecture information document module completes to write according to the bus architecture based on Avalon buses;
Described internal register and the information document of ram modules completes to write according to the design based on Avalon buses;
Described chip initiation control document module completes to write according to the initial work flow based on Avalon buses;
Described automatized script module has various automatized scripts, and each automatized script generates pin comprising bus arbitration model
Sheet, test vector generation script, output information control script and Run Script.
It is 2. according to claim 1 a kind of system to be built based on script for functional verification platform, it is characterised in that
Main equipment number, slave unit that described bus architecture information document module contains comprising the used bus architecture of design
Number, device id, the information of mode of operation.
It is 3. according to claim 1 a kind of system to be built based on script for functional verification platform, it is characterised in that
Described internal register and ram modules is conducted interviews by using Avalon buses.
It is 4. according to claim 1 a kind of system to be built based on script for functional verification platform, it is characterised in that
Described internal register and the information document of ram modules address, data width, depth comprising internal register and ram modules
Degree, reading/writing characteristics, read write command postpone and read and write the information of associated order.
It is 5. according to claim 1 a kind of system to be built based on script for functional verification platform, it is characterised in that
Described automatized script uses perl/tcl/c-shell scripting languages.
It is 6. according to claim 1 a kind of system to be built based on script for functional verification platform, it is characterised in that
Described bus arbitration model generation script generates the bus arbitration model that checking needs by reading bus architecture information document.
It is 7. according to claim 1 a kind of system to be built based on script for functional verification platform, it is characterised in that
Described test vector generation script generated for each register by reading the information document of internal register and ram modules and
The specific test vector of ram modules.
It is 8. according to claim 1 a kind of system to be built based on script for functional verification platform, it is characterised in that
The described output information reserved control port of control script, carries out the classification of output information according to actual needs in test process
Control.
It is 9. according to claim 1 a kind of system to be built based on script for functional verification platform, it is characterised in that
Described Run Script controls document to automatically generate the initial ring for the design based on Avalon buses according to chip initiation
Border configuration order is simultaneously performed, and test vector is performed afterwards, is completed test process and is generated test report.
10. a kind of building method based on script for functional verification platform, it is characterised in that the building method step is such as
Under:
1)Initial work process according to the design based on Avalon buses, including stable clock signal time, reset signals
Enable time, the information of internal each timely sequence of Special controlling signal list, design chips initialization control document;
2)Bus architecture information document is write according to the bus architecture type that design is used;
3)According to the design internal register based on Avalon buses and the address of ram modules, data width, depth, read-write spy
Levy, read write command postpones and read-write associated order information, writes information document;
4)Write automatized script, including bus arbitration model generation script, test vector generation script, output information control pin
Sheet and Run Script;The read write command ATL for meeting agreement timing requirements is write according to Avalon agreements simultaneously;
5)Script is generated using bus arbitration model generate the bus arbitration that checking needs by reading bus architecture information document
Model;
6)Using test vector generation script for the design internal register based on Avalon buses and the information text of ram modules
The test vector of shelves, the selected register to be tested of generation or ram modules;
7)The reserved control port of script is controlled using output information, setting current test needs output to the letter of log files
Breath classification;
8)The corresponding initialization command sequence of document structure tree is controlled according to the chip initiation of design using Run Script, is performed,
Testing results vector, generates test report afterwards, completes this test.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710081078.4A CN106845004A (en) | 2017-02-15 | 2017-02-15 | It is a kind of that system and method is built based on script for functional verification platform |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710081078.4A CN106845004A (en) | 2017-02-15 | 2017-02-15 | It is a kind of that system and method is built based on script for functional verification platform |
Publications (1)
Publication Number | Publication Date |
---|---|
CN106845004A true CN106845004A (en) | 2017-06-13 |
Family
ID=59129032
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710081078.4A Pending CN106845004A (en) | 2017-02-15 | 2017-02-15 | It is a kind of that system and method is built based on script for functional verification platform |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN106845004A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107491605A (en) * | 2017-08-16 | 2017-12-19 | 济南浪潮高新科技投资发展有限公司 | A kind of function verification method and platform for chip design |
CN107943644A (en) * | 2017-11-22 | 2018-04-20 | 济南浪潮高新科技投资发展有限公司 | A kind of building method of functional verification platform for the design based on LOCAL BUS buses |
CN110321341A (en) * | 2019-07-05 | 2019-10-11 | 四川长虹电器股份有限公司 | A kind of arrangement of IC layout data and verification method |
CN116224042A (en) * | 2023-04-28 | 2023-06-06 | 北京壁仞科技开发有限公司 | Method, system, apparatus and medium for generating test vector for testing device under test |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060156268A1 (en) * | 2005-01-13 | 2006-07-13 | Wen Kuei-Ann | Circuit design platform |
CN103218337A (en) * | 2013-03-13 | 2013-07-24 | 北京安拓思科技有限责任公司 | SoC (System on Chip) and method for realizing communication between master modules and between slave modules based on wishbone bus |
CN105069227A (en) * | 2015-08-03 | 2015-11-18 | 浪潮集团有限公司 | Method for building function verification platform based on WISHBONE bus design |
-
2017
- 2017-02-15 CN CN201710081078.4A patent/CN106845004A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060156268A1 (en) * | 2005-01-13 | 2006-07-13 | Wen Kuei-Ann | Circuit design platform |
CN103218337A (en) * | 2013-03-13 | 2013-07-24 | 北京安拓思科技有限责任公司 | SoC (System on Chip) and method for realizing communication between master modules and between slave modules based on wishbone bus |
CN105069227A (en) * | 2015-08-03 | 2015-11-18 | 浪潮集团有限公司 | Method for building function verification platform based on WISHBONE bus design |
Non-Patent Citations (1)
Title |
---|
李延聪: "SOC总线测试平台的设计与实现", 《中国优秀硕士学位论文全文数据库信息科技辑》 * |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107491605A (en) * | 2017-08-16 | 2017-12-19 | 济南浪潮高新科技投资发展有限公司 | A kind of function verification method and platform for chip design |
CN107943644A (en) * | 2017-11-22 | 2018-04-20 | 济南浪潮高新科技投资发展有限公司 | A kind of building method of functional verification platform for the design based on LOCAL BUS buses |
CN110321341A (en) * | 2019-07-05 | 2019-10-11 | 四川长虹电器股份有限公司 | A kind of arrangement of IC layout data and verification method |
CN116224042A (en) * | 2023-04-28 | 2023-06-06 | 北京壁仞科技开发有限公司 | Method, system, apparatus and medium for generating test vector for testing device under test |
CN116224042B (en) * | 2023-04-28 | 2023-08-29 | 北京壁仞科技开发有限公司 | Method, system, apparatus and medium for generating test vector for testing device under test |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN105302950B (en) | A kind of programmable logic device crosslinking emulation test method of soft and hardware collaboration | |
CN105205249B (en) | A kind of SOC debugging verification systems and its software-hardware synergism method | |
CN106845004A (en) | It is a kind of that system and method is built based on script for functional verification platform | |
CN106104698B (en) | Memory physical layer interface logic for generating Dynamic Random Access Memory (DRAM) commands with programmable delay | |
CN106940428A (en) | Chip verification method, apparatus and system | |
CN107168843A (en) | A kind of building method of the functional verification platform based on AXI buses | |
CN105975726A (en) | Verification method and platform based on SystemVerilog language | |
CN105069227A (en) | Method for building function verification platform based on WISHBONE bus design | |
CN102521444A (en) | Cooperative simulation/verification method and device for software and hardware | |
CN113297017A (en) | SOC verification system and method based on UVM | |
CN103838653A (en) | Register automatic authentication method based on VMM RAL | |
CN104268078A (en) | Automatic chip validation method based on parameterized IP test case set | |
US8532975B2 (en) | System and method implementing a simulation acceleration capture buffer | |
CN106294144B (en) | Generation method, system and the server of the test vector of serial communication protocol | |
CN106293625A (en) | A kind of method and apparatus of configuration register | |
CN107479918A (en) | A kind of FPGA models of the MCU burnings of restructural | |
CN111914501A (en) | Implementation method of FeRAM interface verification platform based on UVM verification methodology | |
CN105653409A (en) | Data type conversion-based hardware simulator validation data extraction system | |
CN102565683B (en) | Generation and verification method of test vector | |
CN105446859B (en) | The software condition monitoring of power consumption analysis and wave file automatic generation method | |
CN103530166B (en) | Verification platform and verification method for multi-channel chip based on virtual RAM | |
CN111176926A (en) | IP (Internet protocol) core simulation system and simulation method based on double-port SRAM (static random Access memory) | |
CN108197351A (en) | A kind of emulation verification method by monolithic processor controlled integrated circuit | |
CN202815170U (en) | Chip test system | |
CN107943644A (en) | A kind of building method of functional verification platform for the design based on LOCAL BUS buses |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170613 |