CN103530166B - Verification platform and verification method for multi-channel chip based on virtual RAM - Google Patents
Verification platform and verification method for multi-channel chip based on virtual RAM Download PDFInfo
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- CN103530166B CN103530166B CN201310446686.2A CN201310446686A CN103530166B CN 103530166 B CN103530166 B CN 103530166B CN 201310446686 A CN201310446686 A CN 201310446686A CN 103530166 B CN103530166 B CN 103530166B
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Abstract
The invention discloses a verification platform and a verification method for a multi-channel chip based on a virtual RAM. The verification platform comprises the virtual RAM and a real RAM, wherein the virtual RAM and the real RAM are defined through parameterization, the virtual RAM is provided with a virtual interface, and the virtual interface is connected with the real RAM and monitors the RAM. The verification method comprises the following steps that (1) data writing operations are carried out on the real RAM by design to be tested monitored by the verification platform, (2) data in the multi-channel chip are stored in the virtual RAM through the virtual interface, and (3) the verification platform directly reads data from the virtual RAM. When the verification platform needs to read data from the virtual RAM, the RAM data in the virtual RAM can be called directly. Due to the fact that simulation of the interface timing sequence of reading and writing is not needed in the calling method, simulation time cannot be occupied, and thus the simulation efficiency is improved.
Description
Technical field
It is the present invention relates to a kind of verification technique of multi-channel data business chip, more particularly to a kind of based on virtual RAM
Towards the verification platform and verification method of multi-channel chip, the verification platform can reduce simulation time, improve verification efficiency.
Background technology
Multi-channel service chip is widely used in communication field（Such as OTN, SDH, UART etc.）, in the checking of such chip
（Verification）During, commonly used approach is that CPU models come inside read-write chip used in verification platform
Configuration, alarm, data etc., are used as DUT（Design to be measured）The judgment basis of function accuracy.As shown in figure 1, this conventional
Method needs the read-write sequence for simulating CPU, can take substantial amounts of simulation time, when number of active lanes is more, as CPU cannot be right
Multiple passages are written and read simultaneously, thus the simulation CPU of verification platform can be caused to obtain in DUT in the simulation node of setting
Data, and be forced just be written and read and judge after being delayed to longer time.In this case data, alarm can be caused
Deng loss or mistake, simulation result is affected.
It is in order to solve problems, it is common practice to arrange data, the time of advent of alarm of each passage manually, this
Method needs to expend checking personnel's plenty of time to carry out the planning of simulation excitation, and when emulation sequential has certain change
When, test case just can not be reused.Therefore need to change general emulation mechanisms, reduce the CPU read-writes in generic validation method
Required simulation time, improves verification efficiency.
The content of the invention
It is an object of the invention to provide a kind of verification platform and authentication towards multi-channel chip based on virtual RAM
Method, the verification platform need not spend substantial amounts of energy to go to plan the excitation of each passage, but each passage are written and read in CPU
When, directly data are obtained from virtual RAM module, virtual, the parameterized RAM module is connected to same with the RAM of reality
Socket.The platform can alleviate the congestion for calling CPU models to produce, and reduce simulation time, improve simulation efficiency.
To reach object above, the present invention is employed the following technical solutions.
A kind of verification platform towards multi-channel chip based on virtual RAM, including the virtual RAM using Parametric Definition
With true RAM, there is in virtual RAM virtual interface, the virtual interface is connected with true RAM and monitors true RAM.
The virtual interface includes virtual address line and virtual data line, by the reserved parameter of virtual interface, making virtual
The width of address wire and virtual data line is realized by the parametrization of interface by virtual interface.
Virtual interface also includes dummy pilot signal.
The control signal includes reading to enable, writes the necessary control signals such as enable and ready handshake.This virtually connects
Mouth is connected in design to be measured on real RAM Interface, is realized the monitor in real time to true RAM read-writes, and is transferred data to
In virtual RAM in verification platform.
The virtual interface includes address width parameter, data width parameter, memory depth parameter and instantiation
Local bus virtual interfaces, virtual RAM are marked off with specified address width, data width and memorizer according to interface parameters
The RAM block of depth.
The present invention also provides a kind of verification method towards multi-channel chip based on virtual RAM, comprises the following steps：
1) design to be measured of verification platform monitoring carries out data write operation to true RAM；
2）Data in multi-channel chip are stored in virtual RAM by virtual interface；
3）Verification platform directly reads data from virtual RAM.
In the verification method, the main function pair chip selection signals of virtual RAM are detected, when piece is selected it is effective when detection read
Write signal and address signal, if write signal, then by the RAM of the data storage in bus to appropriate address, if
Read signal, is not operated.I.e. at that time read signal when be indifferent to, and do not carry out any operation.
The virtual RAM is realized by SystemVerilog language.
When the verification platform of the present invention needs to read data from virtual RAM, directly RAM data therein can be carried out
Call.Such call method is due to simulating the interface sequence of read-write, therefore will not take simulation time, so as to improve
Simulation efficiency.
When the data for needing to read in RAM are contrasted, verification platform can be without by cpu i/f, but directly
By direct access data in the virtual RAM of instantiation,
The present invention adopts the VCS of Synopsys companies as emulator, and is developed based on VMM verification methodologies.
Description of the drawings
Fig. 1 is traditional verification platform structural representation；
Fig. 2 is the structural representation of the verification platform towards multi-channel chip based on virtual RAM of the present invention.
Specific embodiment
Below the verification platform and verification method of the present invention are described further.
In the proof procedure of the present invention, each paths of multi-channel chip are required for the relevant position example in verification platform
Change such, there is true RAM relevant position in referring to design to be measured where, the holding wire of actual RAM will be connected to while connection
To virtual RAM, and bit wide, depth, interface width are specified, and virtual RAM is passed through into the interfaces of present invention design in fact
The interface position of border RAM, carries out data acquisition.Should be that each needs the in esse RAM of monitoring to be required for example in principle
Change a virtual RAM.
In simulation process, when DUT writes data in real RAM, virtual RAM also can be received by virtual interface
Same a data, and be conserved.
When verification platform needs to read Data Comparison from RAM, as virtual RAM can the direct quilt in emulation platform
Scoreboard, checker etc. are from comparison component call, it is not necessary to call cpu i/f, so as to eliminate simulation time.It is especially right
In the situation that multichannel is required for reading, during traditional method can be greatlyd save, directly RAM in DUT is read using cpu i/f
A large amount of simulation times shared by data.
The verification platform still remains the interface of CPU, it is also possible to using traditional method, call CPU checking assemblies from
Data are read in DUT.
The major programme of the present invention is realizing virtual RAM using SystemVerilog language.The present invention includes one
Localbus virtual interfaces, a virtual RAM and true RAM using Parametric Definition.Virtual interface in virtual RAM, institute
State virtual interface to be connected with true RAM and monitor true RAM.
The width of RAM, depth, all it is configurable.
Claims (5)
1. a kind of verification platform towards multi-channel chip based on virtual RAM, including the virtual RAM using Parametric Definition and
True RAM, has virtual interface in virtual RAM, the virtual interface is connected and monitors true RAM with true RAM, and its feature exists
In the virtual interface includes the local of address width parameter, data width parameter, memory depth parameter and instantiation
Bus virtual interfaces, virtual RAM are marked off with specified address width, data width and memory depth according to interface parameters
RAM block.
2. the verification platform towards multi-channel chip based on virtual RAM according to claim 1, it is characterised in that institute
Stating virtual interface includes virtual address line and virtual data line, by the reserved parameter of virtual interface, making virtual address line and void
The width for intending data wire is realized by the parametrization of interface by virtual interface.
3. the verification platform towards multi-channel chip based on virtual RAM according to claim 2, it is characterised in that empty
Intending interface also includes dummy pilot signal.
4. a kind of verification method towards multi-channel chip based on virtual RAM, comprises the following steps：
1) design to be measured of verification platform monitoring carries out data write operation to real RAM；
2) data in multi-channel chip are stored in virtual RAM by virtual interface；
3) verification platform directly reads data from virtual RAM；
In the verification method, the main function pair chip selection signals of virtual RAM are detected, when piece is selected it is effective when detection read-write letter
Number and address signal, if write signal, then by the RAM of the data storage in bus to appropriate address, if reading letter
Number, do not operated.
5. the verification method towards multi-channel chip based on virtual RAM according to claim 4, it is characterised in that institute
State virtual RAM to be realized by SystemVerilog language.
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| CN103530166B true CN103530166B (en) | 2017-04-26 |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105550445B (en) * | 2015-12-12 | 2018-08-21 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of virtual verification method based on codec chip |
| CN107797846B (en) * | 2017-09-26 | 2020-07-14 | 记忆科技(深圳)有限公司 | Soc chip verification method |
| CN111967209B (en) * | 2020-08-21 | 2024-06-14 | 广芯微电子（广州）股份有限公司 | SOC simulation verification method and device and storage medium |
| CN112363877B (en) * | 2020-11-10 | 2023-04-21 | 海光信息技术股份有限公司 | Chip verification method and platform |
| CN113176861A (en) * | 2021-05-25 | 2021-07-27 | 北京物芯科技有限责任公司 | Method and device for realizing memory access and memory |
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| US7016826B2 (en) * | 2000-12-21 | 2006-03-21 | Intel Corporation | Apparatus and method of developing software for a multi-processor chip |
| CN101996265A (en) * | 2009-08-25 | 2011-03-30 | 安凯(广州)微电子技术有限公司 | Verification system and method for memory controller |
| CN102096628A (en) * | 2009-12-15 | 2011-06-15 | 上海华虹集成电路有限责任公司 | Method for realizing microprogrammed control unit (MCU) verification platform based on verification methodology of verification methodology manual (VMM) |
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Patent Citations (3)
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| US7016826B2 (en) * | 2000-12-21 | 2006-03-21 | Intel Corporation | Apparatus and method of developing software for a multi-processor chip |
| CN101996265A (en) * | 2009-08-25 | 2011-03-30 | 安凯(广州)微电子技术有限公司 | Verification system and method for memory controller |
| CN102096628A (en) * | 2009-12-15 | 2011-06-15 | 上海华虹集成电路有限责任公司 | Method for realizing microprogrammed control unit (MCU) verification platform based on verification methodology of verification methodology manual (VMM) |
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