CN106293625A - A kind of method and apparatus of configuration register - Google Patents

A kind of method and apparatus of configuration register Download PDF

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Publication number
CN106293625A
CN106293625A CN201510313365.4A CN201510313365A CN106293625A CN 106293625 A CN106293625 A CN 106293625A CN 201510313365 A CN201510313365 A CN 201510313365A CN 106293625 A CN106293625 A CN 106293625A
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CN
China
Prior art keywords
depositor
module
control instruction
random number
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510313365.4A
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Chinese (zh)
Inventor
李军
甘甜
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ZTE Corp
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ZTE Corp
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Publication date
Application filed by ZTE Corp filed Critical ZTE Corp
Priority to CN201510313365.4A priority Critical patent/CN106293625A/en
Priority to PCT/CN2016/079934 priority patent/WO2016197711A1/en
Publication of CN106293625A publication Critical patent/CN106293625A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode

Abstract

The method and apparatus that the invention discloses a kind of configuration register, including: according to the generating random number of the corresponding relation pre-set and generation, depositor is write control instruction；Write in the random number write depositor that control instruction will generate according to generate.By the solution of the present invention, according to writing in the random number write depositor that control instruction will generate, it is ensured that the change at random of the value of write depositor.

Description

A kind of method and apparatus of configuration register
Technical field
Temporal logic of the present invention checking field, the method and apparatus of a kind of configuration register.
Background technology
Integrated circuit (ASIC, Application Specific Integrated Circuit) chip design and Scene can be compiled in logic gate array (FPGA, Field Programmable Gate Array) design, logic Engineers translates into Verilog code according to design instruction concrete demand, in translation process, Verilog code can be caused to there is functional mistake due to a variety of causes.In order to ensure design function Correctness, is positioned by logic checking and the mistake that corrects in design has become a kind of necessary means.
At the background of conventional authentication mode development, generic validation methodology (UVM, Universal Verification Methodology) appearance, have greatly help for promoting verification efficiency.It is base New one developed in open verification methodology (OVM, Open Verification Methodology) For verification methodology.UVM five steps card flow processs (i.e. formulate demonstration plan, exploitation verification platform, Encourage checking, the excitation checking that reduces the scope, particularly customized excitation checking on a large scale) in, exploitation checking is flat Platform is most basic requirement, but the most most extensive excitation Qualify Phases is to need mould to be verified Block (DUT, Design Under Test) inculcates substantial amounts of random data to ensure code coverage and merit Energy coverage rate, just includes the configuration to depositor in these excitations inculcated.UVM is at system On the basis of verilog, often make in verification platform having realized defined in the library file of UVM some The base class used, grand and block statement.These library files can directly invoke, and conveniently tests DUT Wrong localization during card.
Along with evolution and the development of verification technique (i.e. using UVM to verify) of optical communication network, And the compatibility that the library file of FPGA compiles with eda tool, asic chip checking and FPGA patrol Collect checking and trend towards unified.In this context, when the hardware logic of optical communication network is verified, data stream swashs Encourage random arrangement real-time with depositor, become critically important in verification platform, be also to ensure that logic function is covered The important way of lid rate.Usually, need add excited data and the depositor within DUT is entered Row changes in real time.In the logical design of DUT, the most all can use low speed bus, such as peripheral total Line (APB, Advanced Peripheral Bus), Serial Peripheral Interface (SPI, Serial Peripheral Interface) bus, internal integrated circuit (I2C, Inter-Integrated Circuit) bus etc., I The DUT of referred to as band configuration bus.What these low speed bus can be connected in DUT to be configured deposits Device, carrys out configuration register by low speed bus.
Wherein, the structure of Fig. 1 realizes the excitation of data stream device in being existing UVM forms schematic diagram. As shown in Figure 1, it is achieved the method for data stream excitation generally comprises:
Transaction (Transaction) module obtains the inclusion of each packet in target verification packet Structure information, and the pack arrangement information of each packet is transmitted to first with preset parameter type Sequence module；First ray (sequence) module is raw according to the pack arrangement information of each packet Become random number, and by all generating random number frame data corresponding for each packet；First sequencer (sequencer) module is by preset things level modeling (TLM, Transaction Level Modeling) Frame data are sent to the first driving (driver) module by port；Frame data are packed by the oneth driver module Become byte data stream, and be loaded in DUT；The input data of the oneth monitor module monitors DUT (packet in the i.e. the oneth driver module loading to DUT), and the input data of DUT are sent Give with reference to (Reference) module；Reference module completes and DUT according to the input data of DUT After identical function, the expected data information of output is sent to scoring board (scoreboard) module；The The detection data message of two monitoring (monitor) module detection DUT outputs, and it is sent to scoreboard Module；Detection data message and expected data information are compared by scoreboard module.Wherein, if Put the packet structure of transaction, then `uvm_do_on only need to be set at sequence apoplexy due to endogenous wind Class or the cycle-index of `uvm_do_on_with class, just can be simply completed the filling of high-volume random data Transmission function.
Wherein, pack arrangement information includes packet header, quiet lotus, load, overhead byte position and the constraint of packet Condition.
Wherein, during transaction module can directly derive from the library file of UVM The transaction class that uvm_sequence_item class obtains realizes, and a sequence module is permissible The sequence class that directly the uvm_sequence class in the library file of derivation UVM obtains is come real Existing, a sequencer module can directly derive from the uvm_sequencer class in the library file of UVM The sequencer class obtained realizes, and a driver module can directly derive from the library text of UVM The driver class that uvm_driver class in part obtains realizes, and Reference module can directly be sent The Reference class that uvm_Reference class in the library file of raw UVM obtains realizes, and first Monitor module can directly derive from first that the uvm_monitor class in the library file of UVM obtains Monitor class realizes, and the 2nd monitor module can directly derive from the library file of UVM The 2nd monitor class that uvm_monitor class obtains realizes, and scoreboard module can directly derive from The scoreboard class that uvm_scoreboard class in the library file of UVM obtains realizes.
During existing realization excitation, the method for configuration register generally comprises: user manually will write The value entering depositor is input in force statement, uses force statement to carry out quoting of stratification and changes The value of depositor.Such as, force a.b.c.d=1 represents under the c module under the b module under a module The value of d depositor changes 1 into.
In the method for existing configuration register, the value of write depositor needs to be manually entered, and in checking During, in order to ensure checking code coverage and function coverage, it is desirable to write depositor value with Machine changes, and the method for existing configuration register is it is difficult to ensure that write the change at random of the value of depositor.
Summary of the invention
In order to solve the problems referred to above, the present invention proposes the method and apparatus of a kind of configuration register, it is possible to Ensure the change at random of the value of write depositor.
In order to achieve the above object, the present invention proposes a kind of method of configuration register, pre-sets and posts Corresponding relation between storage and address, the method includes:
Generate random number, according to the generating random number of corresponding relation and generation, depositor is write control instruction；
According to writing in the random number write depositor that control instruction will generate.
Preferably, also include:
The reading control instruction to described depositor is generated according to described corresponding relation；
Described depositor is read according to described reading control instruction.
Preferably, described method and the method realizing the excitation of data stream are encapsulated in top layer platform file, and At top layer platform file described in case apoplexy due to endogenous wind instantiation.
The invention allows for the device of a kind of configuration register, at least include:
Module is set, for pre-setting the corresponding relation between depositor and address；
Generation module, is used for generating random number, according to the generating random number of corresponding relation and generation to depositing Device write control instruction；
Control module, for according to writing in the random number write depositor that control instruction will generate.
Preferably, described generation module is additionally operable to:
The reading control instruction to described depositor is generated according to described corresponding relation；
Described control module is additionally operable to:
Described depositor is read according to described reading control instruction.
Preferably, described device and the device realizing the excitation of data stream are encapsulated in top layer platform file, and At top layer platform file described in case apoplexy due to endogenous wind instantiation.
Compared with prior art, the present invention includes: generate random number, according to the corresponding relation pre-set With the generating random number generated, depositor is write control instruction；Random by generate according to writing control instruction In number write depositor.By the solution of the present invention, according to generate to write control instruction random by generate In number write depositor, it is ensured that the change at random of the value of write depositor.
Accompanying drawing explanation
Illustrating the accompanying drawing in the embodiment of the present invention below, the accompanying drawing in embodiment is for this Bright is further appreciated by, and is used for explaining the present invention, is not intended that and the present invention is protected model together with description The restriction enclosed.
Fig. 1 is the structure composition schematic diagram of the device realizing the excitation of data stream in existing UVM；
Fig. 2 is the flow chart of the method for configuration register of the present invention；
Fig. 3 is the structure composition schematic diagram of the device of configuration register of the present invention；
Fig. 4 is the structure composition schematic diagram of the device of embodiment of the present invention configuration register.
Detailed description of the invention
For the ease of the understanding of those skilled in the art, below in conjunction with the accompanying drawings the present invention is further retouched State, can not be used for limiting the scope of the invention.It should be noted that in the case of not conflicting, Embodiment in the application and the various modes in embodiment can be mutually combined.
Seeing Fig. 2, the present invention proposes a kind of method of configuration register, pre-sets depositor and ground Corresponding relation between location.
Wherein, the depositor during the depositor in corresponding relation is DUT.
Depositor can use the mark of depositor to represent, such as, and the title etc. of depositor.
The method includes:
Step 200, generate random number, according to the generating random number of corresponding relation and generation to depositor Write control instruction.
In this step, write control instruction includes the depositor of write operation to be carried out and the address of correspondence thereof, The random number generated.
In this step, random number can be generated during data stream encourages.
In this step, though only a few can the most repeatedly be generated.
In this step, random number generation function can be used to generate random number, implement and belong to ability The known technology of field technique personnel, the protection domain being not intended to limit the present invention, repeat no more here.
Step 201, basis are write in the random number write depositor that control instruction will generate.
The method also includes:
The reading control instruction to depositor is generated according to corresponding relation；Depositor is read according to reading control instruction.
By the solution of the present invention, write, according to generate, the random number write depositor that control instruction will generate In, it is ensured that the change at random of the value of write depositor.
In the method for the present invention, can be by the method for configuration register and the method envelope realizing the excitation of data stream Install in top layer platform file, at case apoplexy due to endogenous wind instantiation top layer platform file.
Wherein it is possible to derive case class on the basis of whole verification platform.
See Fig. 3, the invention allows for the device of a kind of configuration register, at least include:
Module is set, for pre-setting the corresponding relation between depositor and address；
Generation module, is used for generating random number, according to the generating random number of corresponding relation and generation to depositing Device write control instruction；
Control module, for according to writing in the random number write depositor that control instruction will generate.
In assembly of the invention, generation module is additionally operable to:
The reading control instruction to depositor is generated according to corresponding relation；
Control module is additionally operable to:
Depositor is read according to reading control instruction.
Wherein, the device of configuration register and the device realizing the excitation of data stream are encapsulated into top layer platform file In, and at case apoplexy due to endogenous wind instantiation top layer platform file.
The method describing the present invention in detail below by specific embodiment.
Fig. 4 is the structure composition schematic diagram of the device of configuration register.As shown in Figure 4, configuration register Method include:
The correspondence being previously provided with between depositor and address in register model (Reg_model) module Relation.
2nd sequence module generates random number, according to the generating random number of corresponding relation and generation to posting Storage write control instruction, by generate control instruction of writing be sent to the first adaptation (adapter) module； Oneth adapter module is converted into, by writing control instruction, the form that the 2nd sequencer module is capable of identify that； Control instruction of writing after conversion is sent to the 2nd driver module by the 2nd sequencer module；2nd driver Module controls in the random number write depositor that DUT will generate according to the control instruction of writing after conversion.
2nd sequence module generates the reading control instruction to depositor according to corresponding relation, by generate Read control instruction and be sent to an adapter module；Reading control instruction is converted into by the oneth adapter module The form that 2nd sequencer module is capable of identify that；Reading after conversion is controlled by the 2nd sequencer module Instruction is sent to the 2nd driver module；2nd driver module controls according to the reading control instruction after conversion DUT reads depositor；3rd monitor module detection DUT reads the output data of depositor； Output data are sent to the 2nd adapter module by predictor module；2nd adapter module will output It is sent to after the form that data are converted into reg_model module or scoreboard module is capable of identify that Reg_model module or scoreboard module.
Wherein, the 2nd sequencer module, the 2nd driver module and the 3rd monitor module simulation The function of APB bus.
Wherein it is possible to it is real to use the Virtual sequence class of the sequence class being derived from UVM Exampleization the 2nd sequence module and a sequence module.
Wherein it is possible to by all modules in the device of configuration register and the device realizing the excitation of data stream In all modules be encapsulated in top layer platform file, and instantiation Virtual in top layer platform file Sequencer, uses the case apoplexy due to endogenous wind instantiation top layer platform derived from the basis of whole verification platform File.
Wherein, instantiation the oneth sequence class, a sequencer while of in Virtual sequencer Class, the 2nd sequence class, the 2nd sequencer class realize the excitation of data stream and register configuration Synchronize.
The configuration of depositor can also be realized by the form that script calls.
Wherein, the uvm_reg_model during reg_model module can directly derive from the library file of UVM The reg_model class that class obtains realizes, and the 2nd sequence module can directly derive from the storehouse of UVM The 2nd sequence class that uvm_sequence class in file obtains realizes, an adapter module Can directly derive from the adapter class reality that the uvm_adapter class in the library file of UVM obtains Existing, the 2nd sequencer module can directly derive from the uvm_sequencer in the library file of UVM The 2nd sequencer class obtained realizes, and the 2nd driver module can directly derive from the library text of UVM The 2nd driver class that uvm_driver class in part obtains realizes, and the 3rd monitor module can be straight The 3rd monitor class that obtains of uvm_monitor class connect in the library file deriving from UVM realizes, Predictor module can directly derive from what the uvm_predictor class in the library file of UVM obtained Predictor class realizes, and the 2nd adapter module can directly derive from the library file of UVM The 2nd adapter class that uvm_adapter class obtains realizes.
Understand it should be noted that embodiment described above is for only for ease of those skilled in the art , it is not limited to protection scope of the present invention, in the premise of the inventive concept without departing from the present invention Under, any obvious replacement that the present invention is made by those skilled in the art and improvement etc. are all at this Within the protection domain of invention.

Claims (6)

1. the method for a configuration register, it is characterised in that pre-set between depositor and address Corresponding relation, the method includes:
Generate random number, according to the generating random number of corresponding relation and generation, depositor is write control instruction；
According to writing in the random number write depositor that control instruction will generate.
Method the most according to claim 1, it is characterised in that also include:
The reading control instruction to described depositor is generated according to described corresponding relation；
Described depositor is read according to described reading control instruction.
Method the most according to claim 1, it is characterised in that described method swashs with realizing data stream The method encouraged is encapsulated in top layer platform file, and at top layer platform file described in case apoplexy due to endogenous wind instantiation.
4. the device of a configuration register, it is characterised in that at least include:
Module is set, for pre-setting the corresponding relation between depositor and address；
Generation module, is used for generating random number, according to the generating random number of corresponding relation and generation to depositing Device write control instruction；
Control module, for according to writing in the random number write depositor that control instruction will generate.
Device the most according to claim 4, it is characterised in that described generation module is additionally operable to:
The reading control instruction to described depositor is generated according to described corresponding relation；
Described control module is additionally operable to:
Described depositor is read according to described reading control instruction.
Device the most according to claim 4, it is characterised in that described device swashs with realizing data stream The device encouraged is encapsulated in top layer platform file, and at top layer platform file described in case apoplexy due to endogenous wind instantiation.
CN201510313365.4A 2015-06-09 2015-06-09 A kind of method and apparatus of configuration register Pending CN106293625A (en)

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PCT/CN2016/079934 WO2016197711A1 (en) 2015-06-09 2016-04-21 Method and apparatus for configuring register

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CN112527723A (en) * 2020-12-16 2021-03-19 广州昂瑞微电子技术有限公司 UVM-based SPI verification platform and verification method
CN113705161A (en) * 2021-08-10 2021-11-26 博流智能科技（南京）有限公司 UVM register model rapid generation method and system, and chip verification method and system

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CN111523284A (en) * 2020-03-30 2020-08-11 眸芯科技（上海）有限公司 Method and device for converting EDA (electronic design automation) simulation configuration of chip and application
CN111523284B (en) * 2020-03-30 2023-05-26 眸芯科技（上海）有限公司 Method, device and application for converting chip EDA simulation configuration
CN112527723A (en) * 2020-12-16 2021-03-19 广州昂瑞微电子技术有限公司 UVM-based SPI verification platform and verification method
CN113705161A (en) * 2021-08-10 2021-11-26 博流智能科技（南京）有限公司 UVM register model rapid generation method and system, and chip verification method and system
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Application publication date: 20170104