CN104765671A - Method for verifying uart module by using reusable layered verification platform - Google Patents
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Abstract
The invention discloses a method for verifying a uart module by using a reusable layered verification platform. A test platform established by uvm is used by the method, the validity of the uart module written by a verilog language is tested, reusing of the platform is achieved by using a callback function so that one test platform can be used for testing different functions of one module, or the same platform is reused by similar modules to carry out testing. Functions of data reading and data writing of the uart test module are achieved by using the callback function on the same layered verification platform, the verification efficiency is improved, repeat platform establishing is not required, or big changes for platforms are not required.
Description
Technical field
The present invention relates to uart module verification technical field field, be specifically related to a kind of method that reusability Layered Verification Platform carries out uart module verification.
Background technology
Along with the develop rapidly of integrated circuit, checking becomes task the most numerous and diverse with time-consuming in chip design. because the checking of traditional orientation meets the checking demand of VLSI (very large scale integrated circuit), new verification methodology arises at the historic moment, generic validation methodology (Universal VerificationMethodology, UVM) open verification methodology (Open Verification Methodology has been merged, and verification methodology handbook (Verification Methodology Manual OVM), VMM) advantage, become industry the 1st general, open verification methodology, UVM adopts the Tiered verification structure of standard, solve verification platform reusability and standardized problem, improve verification efficiency.
The feature of the checking structure of having levels of uvm verification methodology, the exploitation of UVM verification environment is based on System Verilog language.Because adopt this OO programming language, so each assembly in UVM is all by the form individualism of class (Class), its performance history and C++ very similar. by calling multiple assembly independent of each other, the verification environment of difference in functionality just can be obtained.Like this, each assembly in verification environment can as checking ip module (Verification Intellectual Property, VIP), multiplexing by other verification platforms individually, substantially increase the reusability of assembly, accelerate checking progress, thus save plenty of time and resource.
Universal asynchronous receiving-transmitting transmitter (Universal Asynchronous Receiver/Transmitter), so-called UART is a kind of asynchronous receiving-transmitting transmitter, realizes data serial communications and parallel communications intercropping and transmits and change.
Summary of the invention
The technical problem to be solved in the present invention is: the invention provides a kind of method that reusability Layered Verification Platform carries out uart module verification, the test platform built with uvm, the test correctness of the uart module of verilog language compilation.
The technical solution adopted in the present invention is:
A kind of reusability Layered Verification Platform carries out the method for uart module verification, the test platform that described method uvm builds, the test correctness of the uart module of verilog language compilation, reusing platform is realized with callback function, enable a test platform be used for the difference in functionality of a test module, or the same platform of some similar module reuse is tested.
Described method step is as follows:
1) with the Layered Verification Platform that uvm builds, comprise parts as follows: driver, monitor, scoreboard, reference model, sequencer, In_agent and Out_agent, define separately by the form of class;
2) the class A that definition one is new, callback function is as a member function of category-A, a class is derived from and by the example from category-A, then the callback function as member function is wherein redefined, again the class of category-A and new derivative is added the array apool [] of a category-A, then uses the foreach(apool of verilog [i]) call callback function in each a class and derived class thereof;
3) uart data are that 8bit data add 1bit start bit, and during Uart module read data, each clock receives 1bit data, then converts parallel data to, the data be subject to and error information data packing are exported; Receive the 64bit parallel data of packing when writing data, convert serial data to and export;
4) before the driver of verification platform sends data, call the data of callback function to transaction class to modify, read data just sends 1bit data, writes 64 Bit datas that data just send packing; Then the process of callback function is also called during reference model process data; In the process of process data, repeat 9 clocks during read data, the uart data receiving complete 9bit, being bundled into a transaction, being exported to scoreboard contrast and are used; The data of a collection clock are only needed when writing data.
Described Uart module verilog code is write, and realizes reading serial data, converts parallel data to and exports, and reads parallel data and converts serial data output to; Whether the rub-out signal collected from other modules has the error messages such as data from overflow to judge whether to need to send the function of look-at-me in conjunction with self fifo.
A kind of reusability Layered Verification Platform, described verification platform uvm builds, and comprises parts as follows:
Driver, is used for different excitations to be applied to DUT;
Monitor, is used for monitoring the output of DUT;
Scoreboard, compares the output of the DUT that expectation value and monitor monitor;
Reference model, its input is just the same with DUT, and scoreboard is given in its output, for comparing with the output of DUT;
Sequencer, for generation of data, a sequencer, by startup sequence, obtains data from sequence, and these data is handed to driver;
In_agent and Out_agent, they are the agent in UVM, and so-called agent is just simply packaged together driver, monitor in fact;
Env, is the equal of an especially big container, comprises all classes above;
The form of class is all used to define separately with upper-part.
Beneficial effect of the present invention is: the same Layered Verification Platform of the present invention achieves uart test module read data by using callback function, and writes the function of data, improves verification efficiency.Need not repeat to set for this platform, or large variation is compared to platform.
Accompanying drawing explanation
Fig. 1 is the structural representation of uvm test platform of the present invention.
Embodiment
Below by Figure of description, in conjunction with embodiment, the present invention is further described:
Embodiment 1:
A kind of reusability Layered Verification Platform carries out the method for uart module verification, the test platform that described method uvm builds, the test correctness of the uart module of verilog language compilation, reusing platform is realized with callback function, enable a test platform be used for the difference in functionality of a test module, or the same platform of some similar module reuse is tested.
Embodiment 2:
On the basis of embodiment 1, described in the present embodiment, method step is as follows:
1) with the Layered Verification Platform that uvm builds, comprise parts as follows: driver, monitor, scoreboard, reference model, sequencer, In_agent and Out_agent, define separately by the form of class;
2) the class A that definition one is new, callback function is as a member function of category-A, a class is derived from and by the example from category-A, then the callback function as member function is wherein redefined, again the class of category-A and new derivative is added the array apool [] of a category-A, then uses the foreach(apool of verilog [i]) call callback function in each a class and derived class thereof;
Callback function in Transaction and reference all wants this mode to realize;
Change the data of the packet that transaction class generates with callback function, and change reference model to the processing procedure of data with callback function, realize read data, write the function of data;
3) uart data are that 8bit data add 1bit start bit, and during Uart module read data, each clock receives 1bit data, then converts parallel data to, the data be subject to and error information data packing are exported; Receive the 64bit parallel data of packing when writing data, convert serial data to and export;
4) before the driver of verification platform sends data, call the data of callback function to transaction class to modify, read data just sends 1bit data, writes 64 Bit datas that data just send packing; Then the process of callback function is also called during reference model process data; In the process of process data, repeat 9 clocks during read data, the uart data receiving complete 9bit, being bundled into a transaction, being exported to scoreboard contrast and are used; The data of a collection clock are only needed when writing data.
Embodiment 3:
On the basis of embodiment 2, described in the present embodiment, Uart module verilog code is write, and realizes reading serial data, converts parallel data to and exports, and reads parallel data and converts serial data output to; Whether the rub-out signal collected from other modules has the error messages such as data from overflow to judge whether to need to send the function of look-at-me in conjunction with self fifo.
Embodiment 4:
As shown in Figure 1, a kind of reusability Layered Verification Platform, described verification platform UVM builds, and comprises parts as follows:
Driver, is used for different excitations to be applied to DUT;
Monitor, is used for monitoring the output of DUT;
Scoreboard, compares the output of the DUT that expectation value and monitor monitor;
Reference model, its input is just the same with DUT, and scoreboard is given in its output, for comparing with the output of DUT;
Sequencer, for generation of data, a sequencer, by startup sequence, obtains data from sequence, and these data is handed to driver;
In_agent and Out_agent, they are the agent in UVM, and so-called agent is just simply packaged together driver, monitor in fact;
Env, is the equal of an especially big container, comprises all classes above;
The form of class is all used to define separately with upper-part.
Above embodiment is only for illustration of the present invention; and be not limitation of the present invention; the those of ordinary skill of relevant technical field; without departing from the spirit and scope of the present invention; can also make a variety of changes and modification; therefore all equivalent technical schemes also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (4)
1. one kind is carried out the method for uart module verification with reusability Layered Verification Platform, it is characterized in that: the test platform that described method uvm builds, the test correctness of the uart module of verilog language compilation, reusing platform is realized with callback function, enable a test platform be used for the difference in functionality of a test module, or the same platform of some similar module reuse is tested.
2. a kind of reusability Layered Verification Platform according to claim 1 carries out the method for uart module verification, and it is characterized in that, described method step is as follows:
1) with the Layered Verification Platform that uvm builds, comprise parts as follows: driver, monitor, scoreboard, reference model, sequencer, In_agent and Out_agent, define separately by the form of class;
2) the class A that definition one is new, callback function is as a member function of category-A, a class is derived from and by the example from category-A, then the callback function as member function is wherein redefined, again the class of category-A and new derivative is added the array apool [] of a category-A, then uses the foreach(apool of verilog [i]) call callback function in each a class and derived class thereof;
3) during Uart module read data, each clock receives 1bit data, then converts parallel data to, the data be subject to and error information data packing is exported; Receive the 64bit parallel data of packing when writing data, convert serial data to and export;
4) before the driver of verification platform sends data, call the data of callback function to transaction class to modify, read data just sends 1bit data, writes 64 Bit datas that data just send packing; Then the process of callback function is also called during reference model process data; In the process of process data, repeat 9 clocks during read data, the uart data receiving complete 9bit, being bundled into a transaction, being exported to scoreboard contrast and are used; The data of a collection clock are only needed when writing data.
3. a kind of reusability Layered Verification Platform according to claim 2 carries out the method for uart module verification, it is characterized in that: described Uart module verilog code is write, serial data is read in realization, converts parallel data to and exports, and reads parallel data and converts serial data output to; The rub-out signal collected from other modules judges whether to need to send the function of look-at-me in conjunction with self the whether wrong information of fifo.
4. a reusability Layered Verification Platform, is characterized in that: described verification platform uvm builds, and comprises parts as follows:
Driver, is used for different excitations to be applied to DUT;
Monitor, is used for monitoring the output of DUT;
Scoreboard, compares the output of the DUT that expectation value and monitor monitor;
Reference model, its input is just the same with DUT, and scoreboard is given in its output, for comparing with the output of DUT;
Sequencer, for generation of data, a sequencer, by startup sequence, obtains data from sequence, and these data is handed to driver;
In_agent and Out_agent, they are the agent in UVM;
Env, is the equal of an especially big container, comprises all classes above;
The form of class is all used to define separately with upper-part.
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Cited By (6)
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| CN105718344A (en) * | 2016-01-19 | 2016-06-29 | 中国电子科技集团公司第三十八研究所 | Verification method of FPGA universal configurable UART protocol based on UVM |
| CN106940428A (en) * | 2016-01-04 | 2017-07-11 | 中兴通讯股份有限公司 | Chip verification method, apparatus and system |
| CN109918312A (en) * | 2019-03-22 | 2019-06-21 | 威海优微科技有限公司 | A kind of verification method of the embedded FLASH programming module based on RISC_V |
| CN110837449A (en) * | 2019-11-04 | 2020-02-25 | 深圳航天东方红海特卫星有限公司 | UVM-based onewire communication special verification platform and method |
| CN111143144A (en) * | 2019-12-26 | 2020-05-12 | 山东方寸微电子科技有限公司 | Chip verification method and verification platform with error injection and portability |
| CN112069756A (en) * | 2020-09-02 | 2020-12-11 | 中国航空工业集团公司西安飞行自动控制研究所 | Programmable logic verification architecture and implementation method thereof |
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2015
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106940428A (en) * | 2016-01-04 | 2017-07-11 | 中兴通讯股份有限公司 | Chip verification method, apparatus and system |
| CN105718344A (en) * | 2016-01-19 | 2016-06-29 | 中国电子科技集团公司第三十八研究所 | Verification method of FPGA universal configurable UART protocol based on UVM |
| CN109918312A (en) * | 2019-03-22 | 2019-06-21 | 威海优微科技有限公司 | A kind of verification method of the embedded FLASH programming module based on RISC_V |
| CN109918312B (en) * | 2019-03-22 | 2022-07-12 | 威海优微科技有限公司 | RISC _ V based embedded FLASH programming module verification method |
| CN110837449A (en) * | 2019-11-04 | 2020-02-25 | 深圳航天东方红海特卫星有限公司 | UVM-based onewire communication special verification platform and method |
| CN110837449B (en) * | 2019-11-04 | 2024-03-26 | 深圳航天东方红海特卫星有限公司 | UVM-based onewire communication special verification platform and method |
| CN111143144A (en) * | 2019-12-26 | 2020-05-12 | 山东方寸微电子科技有限公司 | Chip verification method and verification platform with error injection and portability |
| CN112069756A (en) * | 2020-09-02 | 2020-12-11 | 中国航空工业集团公司西安飞行自动控制研究所 | Programmable logic verification architecture and implementation method thereof |
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