CN115858336A - Test vector generation method and device, computing equipment and storage medium - Google Patents
Test vector generation method and device, computing equipment and storage medium Download PDFInfo
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Abstract
The embodiment of the application relates to the technical field of simulation verification, and relates to a test vector generation method and device, computing equipment and a storage medium. The method comprises the following specific scheme: reading in a form for editing a test vector; acquiring test vector directory information, test vector file names, parameter names for testing, parameter configuration modes and parameter configuration values from the form; according to the test vector directory information and the test vector file name, a test vector directory and a test vector file are created in a verification environment; and storing the parameter name, the parameter configuration mode and the parameter configuration value into a test vector file. According to the embodiment of the application, the relevant information of the test vector can be directly obtained from the form, and the test vector is generated according to the obtained information. The verification personnel can automatically generate the test vector only by maintaining the form, so that the coding amount and the labor time input can be reduced. The verification environment can not be modified in the project iteration process, the reusability is strong, and the verification efficiency is effectively improved.
Description
Technical Field
The invention relates to the technical field of simulation verification, in particular to a test vector generation method and device, computing equipment and a storage medium.
Background
At present, the test vectors generated in the chip verification environment are mainly generated by means of code writing. The defects of the mode mainly include the following items:
1) The amount of code to be written is large. In order to ensure the completeness and completeness of verification, different configurations are often required to be combined and covered, and for a large-scale chip, a combination scene is very complicated, which needs a large amount of codes to be covered.
2) And the later maintenance is complicated. In general, the code design of RTL (Register Transfer Level) is modified with some iteration. As the project advances, which may be accompanied by some configuration modifications, the corresponding test cases also need to be adjusted, and the combination scenarios of this configuration may be relatively numerous. This situation introduces a significant amount of workload to the extensive test case modification, and the correctness of the modification is difficult to guarantee.
For the above problems, it is currently possible to adopt the following means:
1) Specialized configuration components are written based on UVM (Universal Verification Methodology) or other Verification methodologies. This approach may solve some of the problems, but the configuration component still requires code writing and is optimized only from the code style, and the above problems still remain.
2) A random authentication approach is used. The method needs to be used in cooperation with functional coverage, and the collected results of the coverage still need to be used as a supplement to the oriented use case, and the problems still exist.
Disclosure of Invention
In view of the above problems in the prior art, embodiments of the present application provide a method and an apparatus for generating a test vector, a computing device, and a storage medium, which can directly obtain relevant information of the test vector from a form, and generate the test vector according to the obtained information. The verification personnel can automatically generate the test vector only by maintaining the form, so that the coding amount and the labor time input can be reduced. The verification environment can not be modified in the project iteration process, the reusability is strong, and the verification efficiency is effectively improved.
To achieve the above object, a first aspect of the present application provides a test vector generation method, including:
reading in a form for editing test vectors;
acquiring test vector directory information, test vector file names, parameter names for testing, parameter configuration modes and parameter configuration values from the form;
creating a test vector directory and a test vector file in a verification environment according to the test vector directory information and the test vector file name;
storing the parameter name, the parameter configuration mode, and the parameter configuration value into the test vector file.
As a possible implementation manner of the first aspect, the method further includes:
obtaining regression case information from the form;
generating a regression case list according to the test vector; the regression case list comprises classification information for classifying the regression cases based on the test vectors.
As a possible implementation manner of the first aspect, after the storing the parameter name, the parameter configuration mode, and the parameter configuration value in the test vector file, the method further includes:
and generating version marking information of the test vector file corresponding to the form.
As a possible implementation manner of the first aspect, the format of the test vector file includes a text format or a comma separated value file format.
A second aspect of the present application provides a test vector generation apparatus, including:
the reading unit is used for reading a form for editing the test vector;
the acquisition unit is used for acquiring test vector directory information, test vector file names, parameter names for testing, parameter configuration modes and parameter configuration values from the form;
the creating unit is used for creating a test vector directory and a test vector file in a verification environment according to the test vector directory information and the test vector file name;
a storage unit, configured to store the parameter name, the parameter configuration mode, and the parameter configuration value in the test vector file.
As a possible implementation manner of the second aspect, the obtaining unit is further configured to: obtaining regression case information from the form;
the apparatus further includes a first generating unit configured to: generating a regression case list according to the test vector; wherein the regression case list includes classification information for classifying the regression case based on the test vector.
As a possible implementation manner of the second aspect, the apparatus further includes a second generating unit, configured to: and after the parameter name, the parameter configuration mode and the parameter configuration value are stored in the test vector file, generating version marking information of the test vector file corresponding to the form.
As a possible implementation manner of the second aspect, the format of the test vector file includes a text format or a comma separated value file format.
A third aspect of the present application provides a computing device comprising:
a communication interface;
at least one processor coupled with the communication interface; and
at least one memory coupled to the processor and storing program instructions that, when executed by the at least one processor, cause the at least one processor to perform the method of any of the first aspects.
A fourth aspect of the present application provides a computer readable storage medium having stored thereon program instructions which, when executed by a computer, cause the computer to perform the method of any of the first aspects described above.
According to the application embodiment, the relevant information of the test vector can be directly obtained from the form, and the test vector is generated according to the obtained information. The testing vector can be automatically generated only by maintaining the form by the verification personnel, so that the coding amount and the labor time input can be reduced. The verification environment can not be modified in the project iteration process, the reusability is high, and the verification efficiency is effectively improved.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiment(s) described hereinafter.
Drawings
The various features and the connections between the various features of the present invention are further described below with reference to the attached figures. The figures are exemplary, some features are not shown to scale, and some of the figures may omit features that are conventional in the art to which the application relates and are not essential to the application, or show additional features that are not essential to the application, and the combination of features shown in the figures is not intended to limit the application. In addition, the same reference numerals are used throughout the specification to designate the same components. The specific drawings are illustrated as follows:
fig. 1 is a schematic diagram of an embodiment of a test vector generation method according to an embodiment of the present disclosure;
fig. 2A and fig. 2B are schematic table diagrams of an embodiment of a test vector generation method according to an embodiment of the present application;
fig. 3 is a schematic diagram of a test vector directory structure according to an embodiment of the test vector generation method provided in the present application;
fig. 4 is a schematic diagram of a test vector file format according to an embodiment of the test vector generation method provided in the present application;
fig. 5 is a schematic flowchart of an embodiment of a test vector generation method according to the present application;
fig. 6 is a flowchart illustrating an embodiment of a test vector generation method according to an embodiment of the present disclosure;
fig. 7 is a flowchart illustrating an embodiment of a test vector generation method according to an embodiment of the present disclosure;
fig. 8 is a flowchart illustrating an embodiment of a test vector generation method according to an embodiment of the present disclosure;
FIG. 9 is a diagram illustrating an embodiment of a test vector generation apparatus according to the present disclosure;
FIG. 10 is a diagram illustrating an embodiment of a test vector generation apparatus according to the present application;
fig. 11 is a schematic diagram of a computing device provided in an embodiment of the present application.
Detailed Description
The terms "first, second, third and the like" or "module a, module B, module C and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order, it being understood that specific orders or sequences may be interchanged where permissible to effect embodiments of the present application in other than those illustrated or described herein.
In the following description, reference numerals indicating steps such as S110, S120 \ 8230 \8230 \ 8230, etc. do not necessarily indicate that the steps are performed, and the order of the front and rear steps may be interchanged or performed simultaneously, where the case allows.
The term "comprising" as used in the specification and claims should not be construed as being limited to the contents listed thereafter; it does not exclude other elements or steps. It should therefore be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, and groups thereof. Thus, the expression "an apparatus comprising the devices a and B" should not be limited to an apparatus consisting of only the components a and B.
Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments, as would be apparent to one of ordinary skill in the art from this disclosure.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. In the case of inconsistency, the meaning described in the present specification or the meaning derived from the content described in the present specification shall control. In addition, the terminology used herein is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the present application. To accurately describe the technical content in the present application and to accurately understand the present invention, terms used in the present specification are given the following explanation or definition before describing the specific embodiments:
1) RTL (Register Transfer Level, also called Register Transfer Level): in integrated circuit design, RTL is an abstraction level used to describe the operation of synchronous digital circuits. At the RTL level, an IC (Integrated Circuit) is composed of a set of registers and logic operations between the registers. This is so because most circuits can be viewed as storing binary data by registers, and processing data by logical operations between registers, and the flow of data processing is controlled by a sequential state machine, and these processes and controls can be described by a hardware description language.
2) UVM (Universal Verification Methodology ): the System is a verification platform development framework taking a System Verilog class library as a main body. The verification engineer may build a functional verification environment with standardized hierarchies and interfaces using its reusable components.
3) Verilog: generally referred to as Verilog HDL (Hardware Description Language). Verilog HDL is a hardware description language that describes the structure and behavior of digital system hardware in textual form. The method can be used for representing logic circuit diagrams, logic expressions and logic functions completed by a digital logic system.
The prior art method is described first, and then the technical solution of the present application is described in detail.
At present, the test vectors generated in the chip verification environment are mainly generated by means of code writing. The defects of the mode mainly include the following items:
1) The amount of code to be written is large. In order to ensure the completeness and completeness of verification, different configurations are often required to be combined and covered, and for a large-scale chip, a combination scene is very complicated, which needs a large amount of codes to be covered.
2) And the later maintenance is complicated. In general, the code design of RTL (Register Transfer Level) is modified with some iteration. As the project advances may entail some configuration modifications, the corresponding test cases may also need to be adjusted, and the combination scenarios for this configuration may be relatively numerous. This situation introduces a significant amount of workload to the extensive test case modification, and the correctness of the modification is difficult to guarantee.
For the above problems, it is currently possible to adopt the following means:
1) Specialized configuration components are written based on UVM (Universal Verification Methodology) or other Verification methodologies. This approach may solve some of the problems, but the configuration component still requires code writing and is optimized only from the code style, and the above problems still remain.
2) A random authentication approach is used. The method needs to be used in cooperation with functional coverage, and the collected results of the coverage still need to be used as a supplement to the oriented use case, and the problems still exist.
In summary, the prior art has the following disadvantages: the code writing amount is large, the labor time investment is large, the maintenance is complicated, and the verification efficiency is low.
Based on the technical problems in the prior art, the application provides a test vector generation method and device, a computing device and a storage medium, which can directly obtain relevant information of a test vector from a form and generate the test vector according to the obtained information. The verification personnel can automatically generate the test vectors only by maintaining the form, so that the coding amount and the labor time investment can be reduced, and the technical problems of large code writing amount and large labor time investment in the prior art are solved. The verification environment can not be modified in the project iteration process, the reusability is high, the verification efficiency is effectively improved, and therefore the technical problems of complex maintenance and low verification efficiency in the prior art are solved.
Fig. 1 is a schematic diagram of an embodiment of a test vector generation method according to an embodiment of the present application. As shown in fig. 1, the method may include:
step S110, reading a form for editing a test vector;
step S120, obtaining test vector directory information, test vector file names, parameter names for testing, parameter configuration modes and parameter configuration values from the form;
step S130, creating a test vector directory and a test vector file in a verification environment according to the test vector directory information and the test vector file name;
step S140, storing the parameter name, the parameter configuration mode, and the parameter configuration value in the test vector file.
The test vector (pattern) is a set of data used to test the correctness of the circuit, and may include both input data for the circuit and correct output data for comparison with the circuit output values. The pattern may also represent the timing characteristics of the chip to be tested. The pattern may be a test tool that is interpreted and implemented by a machine for testing and satisfies timing and driving states of a certain function of the IC. A plurality of test functions can be realized through the pattern, and the test cost is reduced.
The test vector generation method provided by the embodiment of the application can be applied to a simulation verification software management platform and is used for automatically generating the test vector of the simulation environment in the front-end simulation verification of the chip. By adopting the method, the verifier can automatically complete the conversion from the form to the test vector (pattern) by filling and maintaining the form.
Wherein forms for editing test vectors can be filled in and maintained using easily operated process software. For example, a form for editing test vectors may be an excel form or a word form. Taking an excel form as an example, referring to fig. 2A and fig. 2B, in an example of a form for editing a test vector, a cell A1 is a test vector file name. In the example of fig. 2A, the configuration file name in pattern is "env _ para.cfg"; in the example of FIG. 2B, the contents of cell A1 include a test vector file path and a test vector file name. Cell A2 and cell A3 are test vector directory information. In fig. 2A and 2B, cell A2 and cell A3 represent two-level directories. Here, the cell A2 is "pat _ dir _0", and the cell A3 is "pat _ dir _1". In the first row of the excel form, except for the cell A1, the cell B1, the cell C1, and the cell D1 are test case (case) names, indicating that the test vector is used in the corresponding test case. Cell A4 in fig. 2A: cell a15, cell A4 in fig. 2B: a10 is the parameter name used for the test. Cell B4 in fig. 2A: c15, cell B4 in fig. 2B: e10 is the parameter value corresponding to the parameter name. In addition, the other cells of the excel form are filled with parameter configuration patterns, which are not shown in fig. 2A and 2B.
See fig. 2B, where different sheets may be categorized by function, etc. The verifier can maintain the excel form as required and carry out review, modification and other operations. In the subsequent processing flow, the test vector generation method provided by the embodiment of the application can be operated in an automatic converter, and the data in the excel form is converted into a pattern file and a directory.
In step S110, a form for editing the test vector, which is filled in advance by the verifier, is read in. Referring to fig. 2A and 2B, according to the filling specifications, the verifier fills a test vector file name in the cell A1, fills two-level directories (test vector directory information) in the cell A2 and the cell A3, fills a test case name in the first row except for the cell A1, fills a parameter name in the other a-column cells, and fills parameter values and parameter configuration patterns in the other specified cells in advance. Then in step S120, the automatic converter obtains the test vector directory information, the test vector file name, and the parameter name, the parameter configuration mode, and the parameter configuration value for the test in each of the specified cells of the form according to the filling specification.
In step S130, a test vector directory is created in the verification environment according to the test vector directory information obtained in step S120; according to the test vector file name acquired in step S120, a test vector file is created under the test vector directory. In step S140, the parameter name, the parameter configuration mode, and the parameter configuration value acquired in step S120 are stored in the test vector file created in step S130.
By adopting the method, the test vector can be automatically generated based on the information of the form of the edited test vector. When the simulation test is started in the verification environment, a test vector (pattern) is obtained in a test vector file for a specified test case (test _ case), and a binary file simv generated by a VCS (vertical component Simulator) tool is run to run the simulation.
According to the embodiment of the application, the relevant information of the test vector can be directly obtained from the form, and the test vector is generated according to the obtained information. In comparison, the filling and maintenance of the form is less than the workload of writing the code, and the operation is simple and easy to master. The verification personnel can automatically generate the test vector only by maintaining the form, so that the coding amount and the labor time input can be reduced. The verification environment does not need to be modified in the project iteration process, the reusability is high, and the verification efficiency is effectively improved.
Fig. 3 is a schematic diagram of a test vector directory structure according to an embodiment of the test vector generation method provided in the present application. The pattern directory may store an environment configuration file and a register configuration file. The same test _ case, can emulate different patterns. According to the embodiment of the application, the test vectors are automatically generated by filling and maintaining the excel form aiming at the pattern directory and the files in the directory. As shown in fig. 3, the path of the test vector file is port _ rand port _ num1_ rate _ rand. The directories pcs and pcs/, mps _ env _ para.cfg are configuration files of each module of the chip respectively. When the simulation test is started in the verification environment, a test vector (pattern) can be acquired in the test vector file under the corresponding path aiming at a specified test case (test _ case), and the binary file simv is run to run the simulation.
Fig. 4 is a schematic diagram of a test vector file format according to an embodiment of the test vector generation method provided in the embodiment of the present application. As shown in fig. 4, the test vector file name is mps _ env _ para. In the second line example, "qsgmii _ en _ u" is a parameter name, "0" is a parameter arrangement mode, and "7" h7f "is a parameter arrangement value.
Typically, the number of patterns will increase as the project progresses, and may involve content modification. Maintenance can be cumbersome if done by conventional manual writing. For example, for an existing pattern file, if the second line in the above file example needs to be deleted, the files under the corresponding directories need to be operated one by one. By adopting the test vector generation method provided by the embodiment of the application, the core is filling and maintaining of the excel form, the conversion from the form to the pattern is automatically completed through the automatic converter, and the files under the corresponding directories do not need to be operated one by one. By adopting the method, the test vector can be generated quickly, the compiling time is reduced, and the code development amount is reduced.
As shown in fig. 5, in an example, implementing the test vector generation method provided in the embodiment of the present application may include the following steps:
step S1: reading an excel form;
step S2: analyzing the excel form;
and step S3: and converting and outputting the pattern file.
As shown in fig. 6, wherein step S2: the process of analyzing an excel form may include the steps of: the method comprises the steps of obtaining pattern directory information, obtaining a pattern file name, obtaining a parameter configuration mode, obtaining a parameter configuration value, obtaining case information and storing the obtained information in a system memory. And judging whether the next piece of information exists in the form or not. If the next piece of information exists, returning to the step of acquiring the pattern directory information, and sequentially executing the steps to acquire various pieces of information. If the next piece of information does not exist, the analysis ends.
As shown in fig. 7, wherein step S3: the process of converting the output pattern file may include the following steps:
1) And judging whether the test vector directory obtained from the form exists or not. If yes, deleting the original directory, and recreating the test vector directory; if not, directly creating a test vector directory. Here, the original verification environment needs to be deleted, and the verification environment is regenerated for the simulation test.
2) And judging whether the test vector file obtained from the form exists or not. If yes, deleting the original file, and recreating the test vector file; and if not, directly creating a test vector file.
3) And printing the parameter information acquired from the form into a newly created test vector file. The parameter information comprises parameter names, parameter configuration modes and parameter configuration values.
4) And judging whether the next piece of information exists in the form or not. If the next piece of information exists, returning to the step of judging whether the test vector directory obtained from the form exists, and sequentially executing the steps to print the parameter information obtained from the form into the newly created test vector file. If the next piece of information does not exist, a regression list (regression use case list) and a version log (version label information) are generated, and the output is ended.
In one embodiment, the method further comprises:
obtaining regression case information from the form;
generating a regression case list according to the test vector; wherein the regression case list includes classification information for classifying the regression case based on the test vector.
Referring to fig. 2A and 2B, in the first row of the excel form, except for the cell A1, the cell B1, the cell C1, and the cell D1 are names of test cases (cases), which indicates that the test vector is used in the corresponding test case. Referring to fig. 6 and 7, case information may be obtained from the form and stored in the system memory. After generating the test vectors, the regression cases may be classified based on the test vectors (pattern). In one example, 100 use cases are used for simulation verification of a certain module, and after the use cases are classified, the 100 use cases are split into 5 list parts.
In one embodiment, after storing the parameter name, the parameter configuration pattern, and the parameter configuration value in the test vector file, the method further comprises:
and generating version marking information of the test vector file corresponding to the form.
In one example, regression list and SVN (version control System) version management logs may be deposited under the specified path of the pattern deposit path. Based on the version mark information, the files can be uniformly managed and maintained in the simulation verification software management platform, so that the files can be conveniently reused in the project iteration process, and the verification efficiency is improved.
In one embodiment, the format of the test vector file comprises a text format or a comma separated value file format. The file extensions for the text format and comma separated value file format are txt and csv, respectively.
Fig. 8 is a flowchart illustrating an embodiment of a test vector generation method according to an embodiment of the present disclosure. As shown in fig. 8, the specific implementation steps are as follows:
a) And writing a verification environment. It may be necessary to support obtaining register configurations and environment configurations from a file based on verification methodologies such as UVM.
B) And debugging the test case. And compiling the code of the basic use case to complete the coding, compiling and debugging of the use case.
C) The operation automation converter can be a script program based on languages such as Perl, python, VBA and the like, and provides a user interface. And filling required information including register configuration parameters and environment configuration parameters which are well defined in the verification environment, and filling corresponding configuration values according to the test scene.
D) A test vector is generated. And generating test vectors of different test scenes according to the filled text. The vector exists in text form, and can be in the form of. Txt,. Csv, and the like.
E) And (6) executing simulation. Different test vectors are specified through the test cases, and simulation verification is executed.
In summary, the embodiments of the present application have the following beneficial technical effects:
(1) And (4) automatic generation. For the combination of different configurations, the test vector and the use case can be automatically generated, and the coding amount and the labor time input are reduced.
(2) And the verification efficiency is improved. Simulation can be directly performed without repeated compilation.
(3) And the maintenance is easy. The combination conditions of different configurations can be comprehensively inspected, so that the modification is convenient, and the correctness can be ensured.
(4) The reusability is strong. In the project iteration process, the verification environment can not be modified, and the reusability is strong.
As shown in fig. 9, the present application further provides an embodiment of a corresponding test vector generation apparatus. For the beneficial effects or the technical problems to be solved by the apparatus, reference may be made to the description of the method corresponding to each apparatus, or to the description in the summary of the invention, which is not repeated herein.
In an embodiment of the test vector generation apparatus, the apparatus comprises:
a reading unit 100 for reading a form for editing a test vector;
an obtaining unit 200, configured to obtain test vector directory information, a test vector file name, and a parameter name, a parameter configuration mode, and a parameter configuration value for testing from the form;
a creating unit 300, configured to create a test vector directory and a test vector file in a verification environment according to the test vector directory information and the test vector file name;
a storage unit 400, configured to store the parameter name, the parameter configuration mode, and the parameter configuration value in the test vector file.
As shown in fig. 10, in an embodiment, the obtaining unit 200 is further configured to: obtaining regression case information from the form;
the apparatus further comprises a first generating unit 500, the first generating unit 500 being configured to: generating a regression case list according to the test vector; wherein the regression case list includes classification information for classifying the regression case based on the test vector.
In an embodiment, the apparatus further comprises a second generating unit 600, the second generating unit 600 is configured to: and after the parameter name, the parameter configuration mode and the parameter configuration value are stored in the test vector file, generating version marking information of the test vector file corresponding to the form.
In one embodiment, the format of the test vector file comprises a text format or a comma separated value file format.
Fig. 11 is a schematic structural diagram of a computing device 900 provided in an embodiment of the present application. The computing device 900 includes: a processor 910, a memory 920, and a communication interface 930.
It is to be appreciated that the communication interface 930 in the computing device 900 shown in FIG. 11 may be used to communicate with other devices.
The processor 910 may be connected to the memory 920. The memory 920 may be used to store the program codes and data. Therefore, the memory 920 may be a storage unit inside the processor 910, an external storage unit independent of the processor 910, or a component including a storage unit inside the processor 910 and an external storage unit independent of the processor 910.
Optionally, computing device 900 may also include a bus. The memory 920 and the communication interface 930 may be connected to the processor 910 through a bus. The bus may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc.
It should be understood that, in the embodiment of the present application, the processor 910 may employ a Central Processing Unit (CPU). The processor may also be other general purpose processors, digital Signal Processors (DSPs), application Specific Integrated Circuits (ASICs), field Programmable Gate Arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. Or the processor 910 may employ one or more integrated circuits for executing related programs to implement the technical solutions provided in the embodiments of the present application.
The memory 920 may include a read-only memory and a random access memory, and provides instructions and data to the processor 910. A portion of the processor 910 may also include non-volatile random access memory. For example, the processor 910 may also store information of the device type.
When the computing device 900 is running, the processor 910 executes the computer-executable instructions in the memory 920 to perform the operational steps of the above-described method.
It should be understood that the computing device 900 according to the embodiment of the present application may correspond to a corresponding main body for executing the method according to the embodiments of the present application, and the above and other operations and/or functions of each module in the computing device 900 are respectively for implementing corresponding flows of each method of the embodiment, and are not described herein again for brevity.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one type of logical functional division, and other divisions may be realized in practice, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The functions may be stored in a computer-readable storage medium if they are implemented in the form of software functional units and sold or used as separate products. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The present embodiments also provide a computer-readable storage medium, on which a computer program is stored, the program being used for executing a diversification problem generation method when executed by a processor, the method including at least one of the solutions described in the above embodiments.
The computer storage media of the embodiments of the present application may take any combination of one or more computer-readable media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations for aspects of the present application may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, smalltalk, C + +, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).
It should be noted that the foregoing is only illustrative of the preferred embodiments of the present application and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements and substitutions will now be apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present application has been described in more detail with reference to the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention.
Claims (10)
1. A method for generating a test vector, comprising:
reading in a form for editing test vectors;
acquiring test vector directory information, test vector file names, parameter names for testing, parameter configuration modes and parameter configuration values from the form;
creating a test vector directory and a test vector file in a verification environment according to the test vector directory information and the test vector file name;
storing the parameter name, the parameter configuration mode, and the parameter configuration value into the test vector file.
2. The method of claim 1, further comprising:
obtaining regression case information from the form;
generating a regression case list according to the test vector; wherein the regression case list includes classification information for classifying the regression case based on the test vector.
3. The method of claim 1, wherein after storing the parameter name, the parameter configuration pattern, and the parameter configuration value in the test vector file, the method further comprises:
and generating version marking information of the test vector file corresponding to the form.
4. The method of any of claims 1 to 3, wherein the format of the test vector file comprises a text format or a comma separated values file format.
5. A test vector generation apparatus, comprising:
the reading unit is used for reading a form for editing the test vector;
the acquisition unit is used for acquiring test vector directory information, test vector file names, parameter names for testing, parameter configuration modes and parameter configuration values from the form;
the creating unit is used for creating a test vector directory and a test vector file in a verification environment according to the test vector directory information and the test vector file name;
a storage unit, configured to store the parameter name, the parameter configuration mode, and the parameter configuration value in the test vector file.
6. The apparatus of claim 5, wherein the obtaining unit is further configured to: obtaining regression case information from the form;
the apparatus further includes a first generating unit configured to: generating a regression case list according to the test vector; wherein the regression case list includes classification information for classifying the regression case based on the test vector.
7. The apparatus of claim 5, further comprising a second generating unit configured to: and after the parameter name, the parameter configuration mode and the parameter configuration value are stored in the test vector file, generating version marking information of the test vector file corresponding to the form.
8. The apparatus of any of claims 5 to 7, wherein the format of the test vector file comprises a text format or a comma separated values file format.
9. A computing device, comprising:
a communication interface;
at least one processor coupled with the communication interface; and
at least one memory coupled to the processor and storing program instructions that, when executed by the at least one processor, cause the at least one processor to perform the method of any of claims 1-4.
10. A computer-readable storage medium having stored thereon program instructions, which, when executed by a computer, cause the computer to perform the method of any of claims 1-4.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116090380A (en) * | 2023-04-07 | 2023-05-09 | 无锡麟聚半导体科技有限公司 | Automatic method and device for verifying digital integrated circuit, storage medium and terminal |
| CN116932412A (en) * | 2023-09-12 | 2023-10-24 | 厦门优迅高速芯片有限公司 | Sharing platform and method capable of generating test excitation files with different formats |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116090380A (en) * | 2023-04-07 | 2023-05-09 | 无锡麟聚半导体科技有限公司 | Automatic method and device for verifying digital integrated circuit, storage medium and terminal |
| CN116932412A (en) * | 2023-09-12 | 2023-10-24 | 厦门优迅高速芯片有限公司 | Sharing platform and method capable of generating test excitation files with different formats |
| CN116932412B (en) * | 2023-09-12 | 2024-01-23 | 厦门优迅高速芯片有限公司 | Sharing platform and method capable of generating test excitation files with different formats |
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