CN109918312B - RISC _ V based embedded FLASH programming module verification method - Google Patents

RISC _ V based embedded FLASH programming module verification method Download PDF

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CN109918312B
CN109918312B CN201910224306.8A CN201910224306A CN109918312B CN 109918312 B CN109918312 B CN 109918312B CN 201910224306 A CN201910224306 A CN 201910224306A CN 109918312 B CN109918312 B CN 109918312B
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uart
module
flash
sequence
sends
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CN109918312A (en
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付冲
饶勇
吴海龙
孔宪青
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Weihai Uwe Technology Co ltd
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Weihai Uwe Technology Co ltd
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Abstract

The invention relates to the field of software verification methods, in particular to a verification method of an embedded FLASH programming module based on RISC _ V. The verification method of the embedded FLASH programming module based on RISC _ V constructs a chip verification platform, concentrates the sequence function of commonality in the corresponding sequence through Virtual _ sequence layering, concentrates testcase which often needs to be modified and referenceModule which is strongly coupled with commands of different FLASH in different files of a UART verification module, and completes various FLASH programming verifications by calling taskuart _ FLASH _ command which consists of various sequences, and has the advantages that: the chip verification platform of the chip function module for programming the embedded FLASH through the UART is reusable and high in expansibility, and brings great convenience to normal upgrading and use of software of a user.

Description

RISC _ V based embedded FLASH programming module verification method
Technical Field
The invention relates to the field of software verification methods, in particular to a verification method of an embedded FLASH programming module based on RISC _ V.
Background
In the prior art, the commonly used RISV _ V-based SOC chip uses an embedded FLASH, and for the SOC chip containing the embedded FLASH, the FLASH is usually existed as a storage device of software IMAGE; then the FLASH inside the SOC needs to be programmed during production of the product, and further when the system software needs to be updated, the secondary programming of FLASH is also needed, the verification scheme of the embedded FLASH programming by the UART realized by the traditional UART verification module is strongly coupled by the FLASH-referenceModule module of the UART and the programming instruction supported by the FLASH, when the chip uses the embedded FLASH of different manufacturers for the programming of the embedded FLASH, the FLASH of the manufacturers supports different programming instructions, and at the moment, the FLASH _ referenceModule module of the UART verification module needs to be greatly modified, if several UART interface verification modules with different functions are needed in one chip, the existing UART verification modules are used to write several groups of codes of different UART verification modules and store the codes in different directories, if there is a general function modification, the codes in several directories need to be changed at the same time, so that the maintenance of the codes is inconvenient.
The verification method for the chip function module which has reusability and strong expansibility and can program the embedded FLASH through the UART is an urgent need in the prior art.
Disclosure of Invention
The invention aims to provide a verification method of an embedded FLASH programming module based on RISC _ V, and the technical scheme adopted by the invention is as follows: constructing and implementing a chip verification platform, concentrating the sequence function of commonality in the corresponding sequence through a Virtual _ sequence hierarchy, concentrating testcase which needs to be modified frequently and FLASH _ Reference Module which is strongly coupled with commands of different FLASH in different files of a UART verification module, and completing various FLASH programming verifications by calling taskuart _ FLASH _ command which consists of various sequences;
the chip verification platform comprises the following modules:
module 1- -test _ case;
module 2-design to be tested USB _ PD _ DUT;
module 3 — Virtual _ sequence, Virtual sequencer;
module 4 — FLASH _ ENV;
module 5 — FLASH _ ReferenceModule of FLASH _ ENV;
module 6- -Scoreboard of FLASH _ ENV;
module 7- -UART _ ENV;
module 8- -UART _ ENV send agent;
module 9- -UART _ ENV sends sequence of agentt;
module 10-UART _ ENV sends UART _ drive of agent;
module 11 — receive agent of UART _ ENV;
module 12 — monitoring module UART _ monitor of receive agent of UART _ ENV;
module 13 — Sequence library;
the verification steps are as follows:
step 1, test _ case selects sequence needed by the test from a sequence library to form a virtual _ sequence and sends the virtual _ sequence to a virtual _ sequence;
step 2, the vrital _ sequence sends the sequences to the UART _ sequence according to the relevant sequence, and then the UART _ sequence sends the received sequences to the connected UART _ drive;
step 3, the UART _ drive generates excitation conforming to the UART protocol and sends data to the DUT;
step 4, the UART _ drive sends the data to the DUT and simultaneously sends the same data to the FLASH _ ReferenceModule;
step 5, after receiving the data sent by the UART _ drive, the FLASH _ ReferenceModule generates expected feedback values according to the FLASH instruction definition, and sends the feedback values to the FLASH _ Scoreboard;
step 6, the DUT generates a feedback value according to FLASH instruction definition after receiving the instruction and data sent by the UART _ drive;
step 7, the DUT sends a feedback value to the UART _ monitor through the UART interface;
and 8, the UART _ monitor sends the feedback value received from the DUT to the FLASH _ Scoreboard module to compare the last expected data with the actual data.
Specifically, the embedded FLASH programming function verification of the implementation chip can randomly and automatically generate data meeting the FLASH instruction definition and UART protocol requirements and apply the data to the chip;
specifically, the embedded FLASH programming function verification of the chip implemented by the method can automatically generate correct chip feedback expected data.
The invention has the beneficial effects that: the chip verification platform of the chip function module for programming the embedded FLASH through the UART is reusable and high in expansibility, and brings great convenience to normal upgrading and use of software of a user.
Drawings
FIG. 1 is a block diagram of the system architecture of the present invention;
the method comprises the following steps of 1, testing a case layer test; module 2-design to be tested USB _ PD _ DUT; module 3-Virtual _ sequence; module 4-FLASH _ ENV; module 5-FLASH _ ReferenceModule; module 6-FLASH _ Scoreboard, module 7-UART _ ENV; module 9-UART _ Sequence, module 10-UART _ drive, module 12-UART _ monitor, and module 13-Sequence library.
Detailed Description
The invention will be further described with reference to the following figures and examples.
The invention relates to a verification method of an embedded FLASH programming module based on RISC _ V, which comprises the steps of constructing a chip verification platform, centralizing sequence functions of commonality in corresponding sequence by Virtual _ sequence layering, centralizing testcase which needs to be modified frequently and FLASH _ referenceModule which is strongly coupled with commands of different FLASH in different files of a UART verification module, and completing various FLASH programming verifications by calling task _ FLASH _ command which consists of various sequences;
the chip verification platform comprises the following modules:
module 1- -test _ case;
module 2-design to be tested USB _ PD _ DUT;
module 3 — Virtual _ sequence, Virtual sequencer;
module 4 — FLASH _ ENV;
module 5 — FLASH _ ReferenceModule of FLASH _ ENV;
module 6- -Scoreboard of FLASH _ ENV;
module 7 — UART _ ENV;
module 8- -UART _ ENV send agent;
module 9- -UART _ ENV sends the sequence of agentt;
module 10-UART _ ENV sends UART _ drive of agent;
module 11 — receive agent of UART _ ENV;
module 12 — monitoring module UART _ monitor of receive agent of UART _ ENV;
module 13- -Sequence library;
the verification steps are as follows:
step 1, test _ case selects sequence needed by the test from a sequence library to form a virtual _ sequence and sends the virtual _ sequence to a virtual _ sequence;
step 2, the vrital _ sequence sends the sequences to the UART _ sequence according to the relevant sequence, and then the UART _ sequence sends the received sequences to the connected UART _ drive;
step 3, the UART _ drive generates excitation conforming to the UART protocol and sends data to the DUT;
step 4, the UART _ drive sends the same data to the FLASH _ ReferenceModule while sending the data to the DUT;
step 5, after receiving the data sent by the UART _ drive, the FLASH _ ReferenceModule generates expected feedback values according to the FLASH instruction definition, and sends the feedback values to the FLASH _ Scoreboard;
step 6, the DUT generates a feedback value according to FLASH instruction definition after receiving the instruction and data sent by the UART _ drive;
step 7, the DUT sends a feedback value to the UART _ monitor through the UART interface;
and 8, the UART _ monitor sends the feedback value received from the DUT to the FLASH _ Scoreboard module to compare the last expected data with the actual data.
Specifically, the embedded FLASH programming function verification of the implementation chip can randomly and automatically generate data meeting the requirements of FLASH instruction definition and UART protocol and apply the data to the chip;
specifically, the method can automatically generate correct feedback expected data of the chip by verifying the embedded FLASH programming function of the chip.
The following provides a brief description of embodiments of the present invention with reference to the accompanying drawings.
The invention provides a verification method of an embedded FLASH programming module based on RISC _ V.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention.
The chip verification platform of the invention is shown as the attached figure 1, and mainly comprises: module 1-test case layer test; module 3-Virtual _ sequence; module 4-FLASH _ ENV; module 5-FLASH _ ReferenceModule; module 6-FLASH _ Scoreboard; module 7-UART _ ENV; module 9-UART _ sequence; module 10-UART _ DRIVE; module 12-UART _ monitor; module 13-Sequence library.
The module 1-Test _ case layer is a Test case layer, and each Test _ case instantiates different verification environments env and virtual sequence according to actual requirements. Different tests can configure different parameters to the DUT and the verification environment by modifying the config file, different tests can select a sequence suitable for the current use case from the sequence lib to form a virtual sequence, and different test cases can be very simply and flexibly constructed by using the verification platform;
the module 4-FLASH _ ENV comprises a module 6-FLASH _ Scoreboard and a module FLASH _ Reference Module, wherein the module 5-FLASH _ Reference Module is responsible for generating expected data according to the instruction definition of the corresponding FLASH and the instruction received from the UART _ Drive and sending the expected data to the FLASH _ Scoreboard;
the module 7-UART _ ENV comprises a module 8-UART _ tx _ agent and a module 11-UART _ rx _ agent, wherein the module 7 is mainly responsible for receiving a sequence, converting data in the sequence into UART interface signals to be sent to a DUT, receiving UART signal data of the DUT and sending the data to FLASH _ Scoreboard;
the module 8-UART _ tx _ agent comprises a module 9-UART _ tx _ sequence and a module 10-UART _ tx _ drive, and the module 8-UART _ tx _ agent is used for receiving a sequence and converting data in the sequence into UART interface signals to be sent to a DUT (device under test); the module 9-UART _ tx _ sequence is responsible for receiving the sequence from the virtual _ sequence and sending the sequence to the connected UART _ drive;
the module 10, UART _ tx _ drive, is responsible for generating stimuli conforming to the UART protocol to send data to the DUT.
The module 11-UART _ rx _ agent is responsible for receiving UART signal data of a DUT and sending the data to FLASH _ Scoreboard; the module 12-UART _ monitor is responsible for receiving UART signal data of the DUT and sending the data to FLASH _ Scoreboard;
the module 3-virtual sequence is used for centrally managing all the sequence r and the virtual sequence in the platform, and the centralized management has the advantages that different virtual sequences can be executed in sequence in the same function body, so that the confusion of the execution sequence of a plurality of virtual sequences caused by complex use cases is avoided, and the verification personnel can conveniently manage the sequence between different virtual sequences.
The working process of the chip verification platform is explained below according to the dashed line in fig. 1:
step 1, test _ case selects the sequence needed by this test from the sequence library to form a virtual _ sequence and sends it to the virtual _ sequence
And step 2, the vrital _ sequence sends the sequences to the UART _ sequence according to the relevant sequence, and then the UART _ sequence sends the received sequences to the connected UART _ drive.
And 3, generating excitation conforming to the UART protocol by the UART _ drive and sending the data to the DUT.
And 4, transmitting the same data to the FLASH _ ReferenceModule by the UART _ drive while transmitting the data to the DUT.
And 5, after receiving the data sent by the UART _ drive, the FLASH _ Reference Module generates expected feedback values according to the FLASH instruction definition and sends the feedback values to the FLASH _ Scorebroard
And 6, generating a feedback value according to FLASH instruction definition after the DUT receives the instruction and the data sent by the UART _ drive.
Step 7, the DUT sends a feedback value to the UART _ monitor through the UART interface
And 8, the UART _ monitor sends the feedback value received from the DUT to the FLASH _ Scoreboard module to compare the last expected data with the actual data.
The embedded FLASH programming function verification of the implementation chip of the method can automatically acquire various data sent by the chip and automatically compare the various data with correct expected data generated by a verification environment.
The present invention is not limited to the above embodiments, and any technical solutions similar or identical to the present invention, which are made in the light of the present invention, should fall within the protection scope of the present invention.
The techniques, shapes, and configurations not described in detail in the present invention are all known techniques.

Claims (3)

1. A verification method of an embedded FLASH programming module based on RISC _ V is characterized in that: constructing a chip verification implementation platform, centralizing the sequence function of commonality in the corresponding sequence through a Virtual _ sequence hierarchy, centralizing testcase which needs to be modified frequently and FLASH _ referenceModule which is strongly coupled with commands of different FLASH in different files of a UART verification module, and completing various FLASH programming verifications by calling taskuart _ FLASH _ command which consists of various sequences;
the chip verification platform comprises the following modules:
module 1- -test _ case;
module 2- -design to be tested USB _ PD _ DUT;
module 3 — Virtual _ sequence, Virtual sequencer;
module 4 — FLASH _ ENV;
module 5 — FLASH _ ReferenceModule of FLASH _ ENV;
module 6- -Scoreboard of FLASH _ ENV;
module 7- -UART _ ENV;
module 8- -UART _ ENV send agent;
module 9- -UART _ ENV sends sequence of agentt;
module 10-UART _ ENV sends the drive of agentt;
module 11 — receive agent of UART _ ENV;
module 12 — monitoring module UART _ monitor of receive agent of UART _ ENV;
module 13- -Sequence library;
the verification steps are as follows:
step 1, test _ case selects sequence needed by the test from a sequence library to form a virtual _ sequence and sends the virtual _ sequence to a virtual _ sequence;
step 2, the vrital _ sequence sends the sequences to the UART _ sequence according to the relevant sequence, and then the UART _ sequence sends the received sequences to the connected UART _ drive;
step 3, the UART _ drive generates excitation conforming to the UART protocol and sends data to the DUT;
step 4, the UART _ drive sends the same data to the FLASH _ ReferenceModule while sending the data to the DUT;
step 5, after receiving the data sent by the UART _ drive, the FLASH _ ReferenceModule generates expected feedback values according to the FLASH instruction definition, and sends the feedback values to the FLASH _ Scoreboard;
step 6, the DUT generates a feedback value according to FLASH instruction definition after receiving the instruction and data sent by the UART _ drive;
step 7, the DUT sends a feedback value to the UART _ monitor through the UART interface;
and 8, the UART _ monitor sends the feedback value received from the DUT to the FLASH _ Scoreboard module to compare the last expected data with the actual data.
2. The method of claim 1, wherein the method for verifying the RISC _ V based embedded FLASH programming module comprises: the embedded FLASH programming function verification of the implementation chip can randomly and automatically generate data which accords with the FLASH instruction definition and the UART protocol requirement and apply the data to the chip.
3. The method for verifying the embedded FLASH programming module based on RISC _ V as claimed in claim 1, wherein: the embedded FLASH programming function verification of the chip implemented by the method can automatically generate correct chip feedback expected data.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104765671A (en) * 2015-04-17 2015-07-08 浪潮电子信息产业股份有限公司 Method for verifying uart module by using reusable hierarchical verification platform
WO2016197768A1 (en) * 2016-01-04 2016-12-15 中兴通讯股份有限公司 Chip verification method, device, and system
CN107704351A (en) * 2017-10-18 2018-02-16 盛科网络(苏州)有限公司 The verification method and device of a kind of chip
CN108763743A (en) * 2018-05-28 2018-11-06 天津芯海创科技有限公司 Verification platform, method and electronic equipment

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8914569B2 (en) * 2011-02-24 2014-12-16 Winbond Electronics Corp. Flash memory apparatus with serial interface and reset method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104765671A (en) * 2015-04-17 2015-07-08 浪潮电子信息产业股份有限公司 Method for verifying uart module by using reusable hierarchical verification platform
WO2016197768A1 (en) * 2016-01-04 2016-12-15 中兴通讯股份有限公司 Chip verification method, device, and system
CN107704351A (en) * 2017-10-18 2018-02-16 盛科网络(苏州)有限公司 The verification method and device of a kind of chip
CN108763743A (en) * 2018-05-28 2018-11-06 天津芯海创科技有限公司 Verification platform, method and electronic equipment

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