CN110717305A - Method, system, device and medium suitable for verifying and confirming FPGA - Google Patents
Method, system, device and medium suitable for verifying and confirming FPGA Download PDFInfo
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Abstract
The invention discloses a method, a system, equipment and a medium suitable for verifying and confirming an FPGA (field programmable gate array), wherein the method comprises the following steps: s1Executing the task of the concept phase; s2Executing the task in the demand stage; s3Executing the task in the design stage; s4Executing the task of the implementation stage; s5Executing the task of the test stage; step S3The tasks in (1) include: designing a programmable logic simulation test platform and a programmable logic hardware test environment; step S4The tasks in (1) include: evaluating the programmable logic synthesis layout wiring results and performing programmable logic hardware testing. By evaluating the FPGA requirements and design documents, the invention can find errors by means of verification and confirmation before the FPGA is not coded. The invention can be full ofThe method has the advantages that the method has performability for the verification index requirements of the FPGA of the control core of the distributed control system in the field of high safety requirements, can standardize the verification life cycle of the FPGA, and further can improve the correctness and consistency of the functions of the FPGA.
Description
Technical Field
The present invention relates to the Field of verification and validation of DCS (distributed control systems) with high safety requirements, and in particular, to a method, a system, a device, and a medium suitable for verification and validation of a Field-Programmable Gate Array (FPGA).
Background
With the wide application of the DCS in the industrial control field with high safety requirements such as nuclear power, chemical industry, aerospace, military industry and the like, the verification of the core control chip of the DCS becomes a key link for ensuring the safety of the DCS product, and is one of the difficulties in the verification of the whole DCS system.
Most of the common DCS system chips adopt software programming to implement the functions required by the user, such as C language. For such software verification, corresponding index requirements and mode methods are given in the regulatory standards. For example, IEEE 1012-.
However, with the development of semi-custom integrated circuit technology, more and more DCS, especially in the field of high security requirements, adopt the FPGA technology as the control core of DCS. Although semi-custom technology chips such as the FPGA have the characteristics of high reliability, high flexibility and the like, the FPGA is used as hardware for realizing functions by software programming and has a special development design flow, so that the simple software verification and hardware verification process is not completely suitable for the verification of the FPGA. In the field of nuclear power, some standards provide that verification work needs to be carried out in the development process of an FPGA, and the requirements of verification are provided, including requirements and verification indexes of a verification plan, requirement design verification, a verification platform, verification coverage rate and the like, but the existing standards do not provide methods and flows for completing the verification indexes, and the operability is poor.
In addition, in the prior art, the verification work aiming at the whole life cycle of the FPGA development flow is carried out as a part of the development, and mainly relates to a verification means aiming at FPGA codes and chips, including the establishment of a test platform, the compiling of test cases, the simulation after layout and wiring, the judgment of test results and the like. This may cause some problems in the entire life cycle of the FPGA development process in the DCS to be unable to be found, that is, the problems existing before the FPGA is not coded cannot be found in advance and further solved, so that it is finally difficult to meet the index requirements in the industrial control field of high safety requirements such as nuclear power, chemical industry, aerospace, military industry, and the like.
Disclosure of Invention
The technical problem to be solved by the invention is to overcome the defects that the flow operability of the verification and confirmation of the FPGA serving as the DCS control core with high safety requirement in the prior art is poor and the existing problems cannot be found before the FPGA is not coded, and provide a method, a system, equipment and a medium which have performability, can standardize the verification life cycle of the FPGA and further can improve the correctness and consistency of the functions of the FPGA serving as the DCS control core and are suitable for the verification and confirmation of the FPGA.
The invention solves the technical problems through the following technical scheme:
the embodiment of the invention provides a verification and confirmation method suitable for an FPGA (field programmable gate array), which comprises the following steps of:
S1executing the task of the concept phase;
S2executing the task in the demand stage;
S3executing the task in the design stage;
S4executing the task of the implementation stage;
S5executing the task of the test stage;
it is characterized in that the main body of the utility model,
said step S3The task in (1) includes: designing a programmable logic simulation test platform and a programmable logic hardware test environment;
the design programmable logic simulation test platform comprises a description file for generating the technical scheme of the FPGA simulation platform;
the designing of the programmable logic hardware test environment comprises generating a design scheme of a test environment of the FPGA hardware test used in the test stage;
said step S4The tasks in (1) include: evaluating the result of the programmable logic comprehensive layout and wiring and executing a programmable logic hardware test;
the evaluating of the programmable logic comprehensive layout and wiring result comprises verifying the correctness of design input and output of FPGA comprehensive and layout and wiring;
the executing the programmable logic hardware test comprises confirming the functional consistency of the FPGA in the conversion of the software code form into the hardware form.
In the scheme, the designed programmable logic simulation test platform builds a software simulation test platform for the programmable logic of the FPGA to be tested, the simulation test platform is realized in a programming mode, and the realization mode can be a common VHDL (Very-High-Speed Integrated Circuit Hardware Description Language) or Verilog (a Hardware Description Language) direct test platform. For complex logic, a UVM (Universal Verification Methodology) constrained random test platform and the like can be used, and the test platform can play a role in sending test stimuli, comparing and recording test results in programmable logic simulation tests, comprehensive post-layout and wiring tests and FPGA chip-level tests.
In the scheme, the designing of the programmable logic hardware test environment includes designing a test software tool and a hardware PCB (Printed Circuit Board) Board required for FPGA chip-level test, and transmitting an excitation and comparing a test result.
In the scheme, the evaluation of the comprehensive layout and wiring result of the programmable logic refers to that after the FPGA programmable logic completes the comprehensive layout and wiring, the report and the constraint file generated by the tool are examined and analyzed, and whether the programmable logic has hidden troubles such as interface and time sequence problems during the comprehensive layout and wiring is determined.
Preferably, the step S3The task of (1) further comprises: generating a programmable logic simulation test plan;
the generating of the programmable logic simulation test plan comprises a scheme for generating a programmable logic level simulation test, a simulation scheme after FPGA comprehensive layout and wiring and an FPGA chip level test scheme which is loaded in an FPGA chip under programmable logic.
Preferably, the step S1The tasks included in (1) include:
evaluating a concept document;
analyzing the criticality of the concept phase;
analyzing the system demand distribution in the concept phase;
the concept phase can be tracked and analyzed;
analyzing damage in a concept stage;
risk analysis in concept stage;
analyzing information security in a concept phase;
said step S2The tasks included in (1) include:
analyzing programmable logic requirements;
critical analysis in a demand phase;
analyzing a programmable logic demand interface;
the demand stage can be tracked and analyzed;
analyzing the hazard in the demand stage;
risk analysis in a demand phase;
information security analysis in a demand phase;
generating a programmable logic system test plan;
and generating a programmable logic acceptance test plan.
Preferably, the step S3The task of (1) further comprises:
programmable logic design analysis;
performing critical analysis in a design stage;
analyzing a programmable logic design interface;
the design stage can be tracked and analyzed;
analyzing the hazards in the design stage;
risk analysis in the design stage;
information security analysis in a design stage;
designing a programmable logic system test;
designing a programmable logic acceptance test;
said step S4The task of (1) further comprises:
evaluating the programmable logic code;
implementing a phase criticality analysis;
programmable logic implements interface analysis;
the implementation stage can track and analyze;
stage hazard analysis is realized;
implementing stage risk analysis;
stage information security analysis is realized;
generating a programmable logic simulation test case;
generating a programmable logic simulation test procedure;
executing a programmable logic simulation test;
generating a programmable logic system test case;
generating a programmable logic system test procedure;
generating a programmable logic acceptance test case;
generating a programmable logic acceptance test procedure;
said step S5The tasks in (1) include:
the implementation stage can track and analyze;
stage hazard analysis is realized;
implementing stage risk analysis;
stage information security analysis is realized;
executing a programmable logic system test;
and executing a programmable logic acceptance test.
In this embodiment, the step S1And step S2The method aims at the examination and analysis of the functional architecture and the requirement design file of the FPGA so as to ensure the correctness, consistency, integrity, readability and testability of the requirement and the functional design file of the FPGA. Said step S3The method focuses on the specific comprehensive steps of the FPGA, and realizes verification and confirmation of the FPGA comprehensive input file and strategy. Said step S4And step S5The method comprises a specific test mode of the FPGA, including simulation before synthesis, simulation after layout and wiring, hardware simulation, and verification and confirmation of a comprehensive layout and wiring report. Most tasks in each step can obtain corresponding summary reports, and the summary reports are used for recording methods, processes and results of executing the tasks; the test task outputs test reports and data.
Another embodiment of the present invention provides a system for verification and validation suitable for an FPGA, including:
the first-stage execution module is used for executing tasks in the concept stage;
the second-stage execution module is used for executing the tasks in the demand stage;
the third-stage execution module is used for executing tasks in the design stage;
the fourth stage execution module is used for executing the tasks of the implementation stage;
the fifth stage execution module is used for executing the task of the test stage;
it is characterized in that the main body of the utility model,
the tasks in the third-stage execution module comprise: designing a programmable logic simulation test platform and a programmable logic hardware test environment;
the design programmable logic simulation test platform comprises a description file for generating the technical scheme of the FPGA simulation platform;
the designing of the programmable logic hardware test environment comprises generating a design scheme of a test environment of the FPGA hardware test used in the test stage;
the task in the fourth stage execution module comprises: evaluating the result of the programmable logic comprehensive layout and wiring and executing a programmable logic hardware test;
the evaluating of the programmable logic comprehensive layout and wiring result comprises verifying the correctness of design input and output of FPGA comprehensive and layout and wiring;
the executing the programmable logic hardware test comprises confirming the functional consistency of the FPGA in the conversion of the software code form into the hardware form.
Preferably, the tasks in the third-stage execution module further include: generating a programmable logic simulation test plan;
the generating of the programmable logic simulation test plan comprises a scheme for generating a programmable logic level simulation test, a simulation scheme after FPGA comprehensive layout and wiring and an FPGA chip level test scheme which is loaded in an FPGA chip under programmable logic.
Preferably, the tasks included in the first-stage execution module include:
evaluating a concept document;
analyzing the criticality of the concept phase;
analyzing the system demand distribution in the concept phase;
the concept phase can be tracked and analyzed;
analyzing damage in a concept stage;
risk analysis in concept stage;
analyzing information security in a concept phase;
the tasks included in the second-stage execution module include:
analyzing programmable logic requirements;
critical analysis in a demand phase;
analyzing a programmable logic demand interface;
the demand stage can be tracked and analyzed;
analyzing the hazard in the demand stage;
risk analysis in a demand phase;
information security analysis in a demand phase;
generating a programmable logic system test plan;
and generating a programmable logic acceptance test plan.
Preferably, the tasks in the third-stage execution module further include:
programmable logic design analysis;
performing critical analysis in a design stage;
analyzing a programmable logic design interface;
the design stage can be tracked and analyzed;
analyzing the hazards in the design stage;
risk analysis in the design stage;
information security analysis in a design stage;
designing a programmable logic system test;
designing a programmable logic acceptance test;
the task in the fourth stage execution module further comprises:
evaluating the programmable logic code;
implementing a phase criticality analysis;
programmable logic implements interface analysis;
the implementation stage can track and analyze;
stage hazard analysis is realized;
implementing stage risk analysis;
stage information security analysis is realized;
generating a programmable logic simulation test case;
generating a programmable logic simulation test procedure;
executing a programmable logic simulation test;
generating a programmable logic system test case;
generating a programmable logic system test procedure;
generating a programmable logic acceptance test case;
generating a programmable logic acceptance test procedure;
the tasks in the fifth stage execution module include:
the implementation stage can track and analyze;
stage hazard analysis is realized;
implementing stage risk analysis;
stage information security analysis is realized;
executing a programmable logic system test;
and executing a programmable logic acceptance test.
Another embodiment of the present invention provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and is characterized in that the processor implements the method for verifying and confirming the FPGA provided in the foregoing embodiments when executing the computer program.
Another embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored, wherein the computer program, when being executed by a processor, implements the steps of the method for verifying and validating an FPGA provided in the foregoing embodiments.
The positive progress effects of the invention are as follows: the invention combines the special development flow and characteristics of the FPGA, and can find errors by means of verification and confirmation before the FPGA is not coded by evaluating the FPGA requirements and design documents. The FPGA verification method and the FPGA verification system can meet the verification index requirements of the FPGA of the control core of the distributed control system in the field with high safety requirements, have performability, can standardize the verification life cycle of the FPGA, and further can improve the correctness and consistency of the functions of the FPGA.
Drawings
Fig. 1 is a flowchart of a verification and validation method suitable for an FPGA according to embodiment 1 of the present invention.
Fig. 2 is a schematic block diagram of a system for verifying and confirming an FPGA according to embodiment 2 of the present invention.
Fig. 3 is a schematic structural diagram of an electronic device according to embodiment 3 of the present invention.
Detailed Description
The invention is further illustrated by the following examples, which are not intended to limit the scope of the invention.
Example 1
As shown in fig. 1, the present embodiment provides a method for verifying and confirming an FPGA, which includes the following steps:
102, executing a task in a demand stage;
103, executing a task in a design stage;
and step 105, executing the task of the testing stage.
In this embodiment, the tasks included in the concept phase in step 101 include: evaluating a concept document; analyzing the criticality of the concept phase; analyzing the system demand distribution in the concept phase; the concept phase can be tracked and analyzed; analyzing damage in a concept stage; risk analysis in concept stage; and (4) analyzing the information security of the concept phase.
In this embodiment, the tasks included in the demand phase in step 102 include: analyzing programmable logic requirements; critical analysis in a demand phase; analyzing a programmable logic demand interface; the demand stage can be tracked and analyzed; analyzing the hazard in the demand stage; risk analysis in a demand phase; information security analysis in a demand phase; generating a programmable logic system test plan; and generating a programmable logic acceptance test plan.
In this embodiment, the tasks included in the design stage in step 103 include: programmable logic design analysis; performing critical analysis in a design stage; analyzing a programmable logic design interface; the design stage can be tracked and analyzed; analyzing the hazards in the design stage; risk analysis in the design stage; information security analysis in a design stage; designing a programmable logic system test; and designing a programmable logic acceptance test.
In this embodiment, the tasks included in the implementation stage in step 104 include: evaluating the programmable logic code; implementing a phase criticality analysis; programmable logic implements interface analysis; the implementation stage can track and analyze; stage hazard analysis is realized; implementing stage risk analysis; stage information security analysis is realized; generating a programmable logic simulation test case; generating a programmable logic simulation test procedure; executing a programmable logic simulation test; generating a programmable logic system test case; generating a programmable logic system test procedure; generating a programmable logic acceptance test case; and generating a programmable logic acceptance test procedure.
In this embodiment, the tasks included in the testing stage in step 105 include: the implementation stage can track and analyze; stage hazard analysis is realized; implementing stage risk analysis; stage information security analysis is realized; executing a programmable logic system test; and executing a programmable logic acceptance test.
In this embodiment, the task in step 103 further includes: generating a programmable logic simulation test plan, designing a programmable logic simulation test platform and designing a programmable logic hardware test environment. The generating of the programmable logic simulation test plan comprises a scheme for generating a programmable logic level simulation test, a simulation scheme after FPGA comprehensive layout and wiring and an FPGA chip level test scheme of programmable logic downloading and loading into an FPGA chip. Designing a programmable logic simulation test platform comprises generating a description file of the technical scheme of the FPGA simulation platform. The method comprises the steps of designing a programmable logic simulation test platform, and establishing a software simulation test platform aiming at the programmable logic of the FPGA to be tested, wherein the simulation test platform is realized in a programming mode, and the realization mode can be realized by using a common VHDL or Verilog direct test platform. Aiming at complex logic, a UVM constraint random test platform and the like can be used, and the test platform can play a role in sending test excitation, comparing and recording test results in programmable logic simulation test, comprehensive layout and wiring test and FPGA chip-level test. Designing a programmable logic hardware test environment comprises generating a design scheme of a test environment of an FPGA hardware test used in a subsequent test stage, and specifically comprises designing a test software tool and a hardware PCB required by an FPGA chip-level test, and a scheme of sending an excitation and comparing test results.
In this embodiment, the tasks in step 104 include: evaluating the programmable logic synthesis layout wiring results and performing programmable logic hardware testing. The method comprises the steps of evaluating the comprehensive layout and wiring results of the programmable logic, including verifying the correctness of design input and output of FPGA comprehensive and layout and wiring, specifically, after the FPGA programmable logic completes the comprehensive and layout and wiring, checking and analyzing reports and constraint files generated by a tool, and confirming whether the programmable logic has hidden troubles of problems such as interfaces, time sequences and the like during the comprehensive layout and wiring. Performing the programmable logic hardware test includes confirming functional consistency of the FPGA in the software code form to the hardware form.
In this embodiment, when the task in step 104 is executed, the evaluation of the comprehensive layout and routing result of the programmable logic means that after the FPGA programmable logic completes the comprehensive layout and routing, the report and the constraint file generated by the tool are examined and analyzed, and whether the programmable logic has hidden troubles such as an interface and a timing sequence during the comprehensive layout and routing is determined. Generating simulation test cases and procedures of the programmable logic, compiling the test cases and executing step descriptions of the test according to the requirements of the programmable logic, and considering whether the test cases cover all the functional requirements of the programmable logic.
In this embodiment, most tasks output documents, and test tasks output test reports and data. After all tasks of each stage are completed, a summary report of the stage is output to summarize the tasks of the stage and provide optimization suggestions.
In the embodiment, a mode of programming a programmable logic verification and confirmation outline may be adopted in specific implementation, where the outline is used to describe a concept stage, a requirement stage, a design stage, and V & V (verification and confirmation) of a realization stage and a test stage that need to be developed for an FPGA product, and to specify specific tasks and requirements that need to be developed in the five stages. The 5V & V processes involved in this embodiment are suitable for being applied to FPGA V & V. The specific tasks and requirements are embodied in each stage, most of the requirements of the tasks can be found in IEEE 1012-: the design stage is based on IEEE 1012-2004, and has two more tasks of designing a programmable logic simulation test platform and designing a programmable logic hardware test environment, wherein the two tasks are added aiming at a special verification method of the FPGA, the designing and programmable logic simulation test platform is a technical scheme description file of the FPGA simulation platform, and the designing and programmable logic hardware test environment task is a design scheme of a test environment of FPGA hardware test in a subsequent test stage. The realization stage is based on IEEE 1012-2004, and adds special evaluation programmable logic comprehensive layout and wiring result of FPGA and execution programmable logic hardware test, and the comprehensive layout and wiring evaluation is mainly to verify the correctness of design input and output of two links of FPGA synthesis and layout and wiring. The task of executing the programmable logic hardware test is mainly to confirm the functional consistency of the FPGA in the conversion from the software code form to the hardware form.
In the embodiment, after all five steps are completed, the FPGA V & V summary report is also required to be completed, the task of the whole FPGA V & V test life cycle is summarized, and the correctness, consistency and integrity of the FPGA product and whether the user requirement is met are finally evaluated.
In this embodiment, the concept stage and the requirement stage mainly aim at the functional architecture of the FPGA and the examination and analysis of the requirement design file, and ensure the correctness, consistency, integrity, readability and testability of the requirement of the FPGA and the functional design file. In the design stage, the implementation stage and the test stage of the FPGA, due to the special development flow and characteristics of the FPGA, the contents of the flow and the task are different from those of the software V & V. The design stage is mainly focused on the specific comprehensive steps of the FPGA, the FPGA comprehensive input file and the strategy are verified and confirmed, and the realization stage and the test stage are mainly different from the specific test mode of the FPGA, namely simulation before comprehensive, simulation after layout and wiring, hardware simulation and verification and confirmation of a comprehensive layout and wiring report, wherein the development of an FPGA test platform is the most important.
The verification and confirmation method provided by the embodiment aims at the fact that the verification of the FPGA runs through the whole FPGA development life cycle, the FPGA requirement and the design document are evaluated, and some errors are solved in a V & V mode before the FPGA is not coded. And after the FPGA is integrated into the system, a related V & V means is also provided. Meanwhile, tasks required to be executed in all verification stages are combed, so that the verification tasks provided by the embodiment are more specific, quantitative and operable.
The verification and confirmation method provided by the embodiment provides a set of executable verification flow suitable for the FPGA, and the FPGA verification life cycle is standardized. The invention relates to an FPGA V & V process and a V & V result file and data thereof, and provides a mode method and a basis for proving the functional correctness and consistency of the FPGA, especially in the high-safety requirement fields of nuclear power, aviation, military industry and the like.
The invention combines the special development flow and characteristics of the FPGA, and can find errors by means of verification and confirmation before the FPGA is not coded by evaluating the FPGA requirements and design documents. The FPGA verification method and the FPGA verification system can meet the verification index requirements of the FPGA of the control core of the distributed control system in the field with high safety requirements, have performability, can standardize the verification life cycle of the FPGA, and further can improve the correctness and consistency of the functions of the FPGA.
Example 2
As shown in fig. 2, the present embodiment provides a system for verification and validation of an FPGA, where the system includes: a first stage execution module 1, a second stage execution module 2, a third stage execution module 3, a fourth stage execution module 4, and a fifth stage execution module 5.
The first-stage execution module 1 is configured to execute tasks in concept stages, where the tasks in the concept stages include: evaluating a concept document; analyzing the criticality of the concept phase; analyzing the system demand distribution in the concept phase; the concept phase can be tracked and analyzed; analyzing damage in a concept stage; risk analysis in concept stage; and (4) analyzing the information security of the concept phase.
The second stage execution module 2 is used for executing tasks in a demand stage, and the tasks in the demand stage include: analyzing programmable logic requirements; critical analysis in a demand phase; analyzing a programmable logic demand interface; the demand stage can be tracked and analyzed; analyzing the hazard in the demand stage; risk analysis in a demand phase; information security analysis in a demand phase; generating a programmable logic system test plan; and generating a programmable logic acceptance test plan.
The third stage execution module 3 is used for executing the tasks of the design stage, and the tasks of the design stage include: programmable logic design analysis; performing critical analysis in a design stage; analyzing a programmable logic design interface; the design stage can be tracked and analyzed; analyzing the hazards in the design stage; risk analysis in the design stage; information security analysis in a design stage; designing a programmable logic system test; and designing a programmable logic acceptance test.
The fourth stage execution module 4 is configured to execute tasks of the implementation stage, where the tasks of the implementation stage include: evaluating the programmable logic code; implementing a phase criticality analysis; programmable logic implements interface analysis; the implementation stage can track and analyze; stage hazard analysis is realized; implementing stage risk analysis; stage information security analysis is realized; generating a programmable logic simulation test case; generating a programmable logic simulation test procedure; executing a programmable logic simulation test; generating a programmable logic system test case; generating a programmable logic system test procedure; generating a programmable logic acceptance test case; and generating a programmable logic acceptance test procedure.
The fifth stage execution module 5 is configured to execute the tasks of the test stage, where the tasks of the test stage include: the implementation stage can track and analyze; stage hazard analysis is realized; implementing stage risk analysis; stage information security analysis is realized; executing a programmable logic system test; and executing a programmable logic acceptance test.
In this embodiment, the tasks in the third-stage execution module 3 further include: generating a programmable logic simulation test plan, designing a programmable logic simulation test platform and designing a programmable logic hardware test environment. The generating of the programmable logic simulation test plan comprises a scheme for generating a programmable logic level simulation test, a simulation scheme after FPGA comprehensive layout and wiring and an FPGA chip level test scheme of programmable logic downloading and loading into an FPGA chip. Designing a programmable logic simulation test platform comprises generating a description file of the technical scheme of the FPGA simulation platform. Designing a programmable logic hardware test environment includes generating a design of a test environment for the FPGA hardware tests used in the test phase.
In this embodiment, the task in the fourth stage execution module 4 further includes: evaluating the programmable logic synthesis layout wiring results and performing programmable logic hardware testing. The method comprises the following steps of evaluating the result of the programmable logic comprehensive layout and wiring, wherein the step of verifying the correctness of design input and output of FPGA comprehensive layout and wiring is included. Performing the programmable logic hardware test includes confirming functional consistency of the FPGA in the software code form to the hardware form.
The verification and confirmation system provided by the embodiment aims at the verification of the FPGA through the whole FPGA development life cycle, including the evaluation of FPGA requirements and design documents, and aims to solve some errors in a V & V mode before the FPGA is not coded. And after the FPGA is integrated into the system, a related V & V means is also provided. Meanwhile, tasks required to be executed in all verification stages are combed, so that the verification tasks provided by the embodiment are more specific, quantitative and operable.
The verification and confirmation system provided by the embodiment provides a set of executable verification system suitable for FPGA, and the FPGA verification life cycle is standardized. The invention relates to an FPGA V & V process and a V & V result file and data thereof, and provides a mode method and a basis for proving the functional correctness and consistency of the FPGA, especially in the high-safety requirement fields of nuclear power, aviation, military industry and the like.
It should be understood by those skilled in the art that in the implementation, a variety of products can be realized based on the technical concept of the present invention, for example, in the implementation, a network platform can be generated, the network platform can streamline the V & V life cycle, similar to a financial reimbursement system, the tasks in each stage can be executed sequentially according to the configuration, or can be executed in parallel, the task executor is responsible for uploading the task input to the platform, or outputting the task input from the platform, and the auditor can perform audits on the platform and confirm whether the condition for entering the next stage is satisfied, etc. Based on the network platform, the FPGA V & V work can be completed by workers unfamiliar with the V & V process by means of the platform.
The invention combines the special development flow and characteristics of the FPGA, and can find errors by means of verification and confirmation before the FPGA is not coded by evaluating the FPGA requirements and design documents. The FPGA verification method and the FPGA verification system can meet the verification index requirements of the FPGA of the control core of the distributed control system in the field with high safety requirements, have performability, can standardize the verification life cycle of the FPGA, and further can improve the correctness and consistency of the functions of the FPGA.
Example 3
Fig. 3 is a schematic structural diagram of an electronic device according to embodiment 3 of the present invention. The electronic device comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor executes the program to realize the method for verifying and confirming the FPGA of the embodiment 1. The electronic device 30 shown in fig. 3 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiment of the present invention.
As shown in fig. 3, the electronic device 30 may be embodied in the form of a general purpose computing device, which may be, for example, a server device. The components of the electronic device 30 may include, but are not limited to: the at least one processor 31, the at least one memory 32, and a bus 33 connecting the various system components (including the memory 32 and the processor 31).
The bus 33 includes a data bus, an address bus, and a control bus.
The memory 32 may include volatile memory, such as Random Access Memory (RAM)321 and/or cache memory 322, and may further include Read Only Memory (ROM) 323.
The processor 31 executes computer programs stored in the memory 32 to execute various functional applications and data processing, such as the method for verifying and confirming the FPGA provided in embodiment 1 of the present invention.
The electronic device 30 may also communicate with one or more external devices 34 (e.g., keyboard, pointing device, etc.). Such communication may be through input/output (I/O) interfaces 35. Also, model-generating device 30 may also communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network, such as the Internet) via network adapter 36. As shown, network adapter 36 communicates with the other modules of model-generating device 30 via bus 33. It should be understood that although not shown in the figures, other hardware and/or software modules may be used in conjunction with the model-generating device 30, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID (disk array) systems, tape drives, and data backup storage systems, etc.
It should be noted that although in the above detailed description several units/modules or sub-units/modules of the electronic device are mentioned, such a division is merely exemplary and not mandatory. Indeed, the features and functionality of two or more of the units/modules described above may be embodied in one unit/module according to embodiments of the invention. Conversely, the features and functions of one unit/module described above may be further divided into embodiments by a plurality of units/modules.
Example 4
The present embodiment provides a computer-readable storage medium, on which a computer program is stored, which when executed by a processor implements the steps of the method for verification and validation for an FPGA provided in embodiment 1.
More specific examples, among others, that the readable storage medium may employ may include, but are not limited to: a portable disk, a hard disk, random access memory, read only memory, erasable programmable read only memory, optical storage device, magnetic storage device, or any suitable combination of the foregoing.
In a possible implementation manner, the present invention can also be implemented in the form of a program product, which includes program code for causing a terminal device to execute the steps of the method for verifying and confirming an FPGA described in embodiment 1 when the program product runs on the terminal device.
Where program code for carrying out the invention is written in any combination of one or more programming languages, the program code may be executed entirely on the user device, partly on the user device, as a stand-alone software package, partly on the user device and partly on a remote device or entirely on the remote device.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.
Claims (10)
1. A verification and confirmation method suitable for an FPGA comprises the following steps:
S1executing the task of the concept phase;
S2executing the task in the demand stage;
S3executing the task in the design stage;
S4executing the task of the implementation stage;
S5executing the task of the test stage;
it is characterized in that the preparation method is characterized in that,
said step S3The tasks in (1) include: designing a programmable logic simulation test platform and a programmable logic hardware test environment;
the design programmable logic simulation test platform comprises a description file for generating the technical scheme of the FPGA simulation platform;
the designing of the programmable logic hardware test environment comprises generating a design scheme of a test environment of the FPGA hardware test used in the test stage;
said step S4The tasks in (1) include: evaluating programmable logic synthesisLaying out the wiring result and executing a programmable logic hardware test;
the evaluating of the programmable logic comprehensive layout and wiring result comprises verifying the correctness of design input and output of FPGA comprehensive and layout and wiring;
the executing the programmable logic hardware test comprises confirming the functional consistency of the FPGA in the conversion of the software code form into the hardware form.
2. The method for verification and validation of an FPGA of claim 1,
said step S3The task of (1) further comprises: generating a programmable logic simulation test plan;
the generating of the programmable logic simulation test plan comprises a scheme for generating a programmable logic level simulation test, a simulation scheme after FPGA comprehensive layout and wiring and an FPGA chip level test scheme which is loaded in an FPGA chip under programmable logic.
3. The method for verification and validation of an FPGA of claim 1,
said step S1The tasks included in (1) include:
evaluating a concept document;
analyzing the criticality of the concept phase;
analyzing the system demand distribution in the concept phase;
the concept phase can be tracked and analyzed;
analyzing damage in a concept stage;
risk analysis in concept stage;
analyzing information security in a concept phase;
said step S2The tasks included in (1) include:
analyzing programmable logic requirements;
critical analysis in a demand phase;
analyzing a programmable logic demand interface;
the demand stage can be tracked and analyzed;
analyzing the hazard in the demand stage;
risk analysis in a demand phase;
information security analysis in a demand phase;
generating a programmable logic system test plan;
and generating a programmable logic acceptance test plan.
4. Method for verification and validation of an FPGA according to one of claims 1 to 3,
said step S3The task of (1) further comprises:
programmable logic design analysis;
performing critical analysis in a design stage;
analyzing a programmable logic design interface;
the design stage can be tracked and analyzed;
analyzing the hazards in the design stage;
risk analysis in the design stage;
information security analysis in a design stage;
designing a programmable logic system test;
designing a programmable logic acceptance test;
said step S4The task of (1) further comprises:
evaluating the programmable logic code;
implementing a phase criticality analysis;
programmable logic implements interface analysis;
the implementation stage can track and analyze;
stage hazard analysis is realized;
implementing stage risk analysis;
stage information security analysis is realized;
generating a programmable logic simulation test case;
generating a programmable logic simulation test procedure;
executing a programmable logic simulation test;
generating a programmable logic system test case;
generating a programmable logic system test procedure;
generating a programmable logic acceptance test case;
generating a programmable logic acceptance test procedure;
said step S5The tasks in (1) include:
the implementation stage can track and analyze;
stage hazard analysis is realized;
implementing stage risk analysis;
stage information security analysis is realized;
executing a programmable logic system test;
and executing a programmable logic acceptance test.
5. A system for verification and validation of an FPGA, the system comprising:
the first-stage execution module is used for executing tasks in the concept stage;
the second-stage execution module is used for executing the tasks in the demand stage;
the third-stage execution module is used for executing tasks in the design stage;
the fourth stage execution module is used for executing the tasks of the implementation stage;
the fifth stage execution module is used for executing the task of the test stage;
it is characterized in that the preparation method is characterized in that,
the tasks in the third-stage execution module comprise: designing a programmable logic simulation test platform and a programmable logic hardware test environment;
the design programmable logic simulation test platform comprises a description file for generating the technical scheme of the FPGA simulation platform;
the designing of the programmable logic hardware test environment comprises generating a design scheme of a test environment of the FPGA hardware test used in the test stage;
the task in the fourth stage execution module comprises: evaluating the result of the programmable logic comprehensive layout and wiring and executing a programmable logic hardware test;
the evaluating of the programmable logic comprehensive layout and wiring result comprises verifying the correctness of design input and output of FPGA comprehensive and layout and wiring;
the executing the programmable logic hardware test comprises confirming the functional consistency of the FPGA in the conversion of the software code form into the hardware form.
6. The system for verification and validation of an FPGA of claim 5,
the tasks in the third-stage execution module further include: generating a programmable logic simulation test plan;
the generating of the programmable logic simulation test plan comprises a scheme for generating a programmable logic level simulation test, a simulation scheme after FPGA comprehensive layout and wiring and an FPGA chip level test scheme which is loaded in an FPGA chip under programmable logic.
7. The system for verification and validation of an FPGA of claim 5,
the tasks included in the first-stage execution module include:
evaluating a concept document;
analyzing the criticality of the concept phase;
analyzing the system demand distribution in the concept phase;
the concept phase can be tracked and analyzed;
analyzing damage in a concept stage;
risk analysis in concept stage;
analyzing information security in a concept phase;
the tasks included in the second-stage execution module include:
analyzing programmable logic requirements;
critical analysis in a demand phase;
analyzing a programmable logic demand interface;
the demand stage can be tracked and analyzed;
analyzing the hazard in the demand stage;
risk analysis in a demand phase;
information security analysis in a demand phase;
generating a programmable logic system test plan;
and generating a programmable logic acceptance test plan.
8. System for verification and validation of FPGAs according to any of claims 5 to 7,
the tasks in the third-stage execution module further include:
programmable logic design analysis;
performing critical analysis in a design stage;
analyzing a programmable logic design interface;
the design stage can be tracked and analyzed;
analyzing the hazards in the design stage;
risk analysis in the design stage;
information security analysis in a design stage;
designing a programmable logic system test;
designing a programmable logic acceptance test;
the task in the fourth stage execution module further comprises:
evaluating the programmable logic code;
implementing a phase criticality analysis;
programmable logic implements interface analysis;
the implementation stage can track and analyze;
stage hazard analysis is realized;
implementing stage risk analysis;
stage information security analysis is realized;
generating a programmable logic simulation test case;
generating a programmable logic simulation test procedure;
executing a programmable logic simulation test;
generating a programmable logic system test case;
generating a programmable logic system test procedure;
generating a programmable logic acceptance test case;
generating a programmable logic acceptance test procedure;
the tasks in the fifth stage execution module include:
the implementation stage can track and analyze;
stage hazard analysis is realized;
implementing stage risk analysis;
stage information security analysis is realized;
executing a programmable logic system test;
and executing a programmable logic acceptance test.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the method for FPGA validation and validation of any one of claims 1 to 4 when executing the computer program.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method for authentication and validation of an FPGA of any one of claims 1 to 4.
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