CN110347542A - A kind of port connection method, system and medium improving verification environment reusability - Google Patents
A kind of port connection method, system and medium improving verification environment reusability Download PDFInfo
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- CN110347542A CN110347542A CN201910467210.4A CN201910467210A CN110347542A CN 110347542 A CN110347542 A CN 110347542A CN 201910467210 A CN201910467210 A CN 201910467210A CN 110347542 A CN110347542 A CN 110347542A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
Abstract
The invention discloses a kind of port connection method, system and media for improving verification environment reusability, definition connects for connecting DUT port signal with the port of verification environment macro, the connection direction of signal is determined according to the level of verification environment, when the level of verification environment is module level, with the port signal of checking assembly driving DUT；When the level of verification environment is subsystem irrespective of size, with the port signal of checking assembly sampling DUT；Macro be attached is connect using port with the signal that subsystem level verification can reuse to module level verification.The present invention determines the connection direction of signal, can effectively solve the problem that reuse problem, save verifying workload according to the level of verification environment, avoids reconnect signal and is artificially introduced mistake, improves verification efficiency.
Description
Technical field
The present invention relates to chip checking, especially a kind of port connection method for improving verification environment reusability, system and
Medium.
Background technique
Verifying is in chip product exploitation link to prove whether design function is realized and correctly realize one must not
The process that can lack, and in order to preferably complete to verify, the personnel that verify need often to build appropriateness around design, efficiently verify ring
Border.As chip-scale and complexity are continuously improved, chip checking technology is fast-developing, and having built for verification environment is various each
The method of sample.In the industry cycle more commonly used at present is reusable Layered Verification Platform, as shown in Figure 1, from low to high, being divided into
Signals layer, layer order, functional layer, scene layer and test layer.Wherein verification environment includes generator, agency, driver, monitoring
It device, detector, scoreboard and asserts.
Signals layer includes DUT (Design Under Test, design to be verified) and interface.
Layer order passes downwardly through signal layer interface and is connected with design to be measured on signals layer, logical upwardly through transaction-level
Road is communicated with functional layer, is generally comprised driver (Driver), monitor (Monitor) and is asserted (Assertion).Driver
The excitation of signal grade is converted by the affairs from upper layer and inputs to DUT, and monitor is used to monitor variation and the conversion of interface signal
The detector on upper layer is passed to for affairs.It asserts for indicating and verifying expected result.
Functional layer is located on layer order, is the abstract of high level operation, passes through transaction-level tunneling traffic between each other.This
It includes agency (Agent), detector (Checker) and scoreboard (Scoreboard) that one layer main.Act on behalf of (not shown)
Effect be to receive the high-rise affairs that transmit of upper layer, and these high-rise affairs are converted into individually ordering to driver and are mentioned
For.Driver will generate corresponding excited data after receiving the order that agency issues.Scoreboard sets for dynamic prediction
The response of meter is applied to the excitation of DUT while being applied to scoreboard, and the transfer function in scoreboard all turns the excitation of input
It changes the form finally responded into, and is stored in data structure, to pass to detector, scoreboard also carries out all affairs
Record and statistics record the affairs number of execution, the affairs number that success fails, if a certain affairs are missed.Detector
It is compared to judge by the predicated response stored in the data and scoreboard that transmit monitor whether correct to brake.
Scene (Scenario) layer is primarily used to generate the sequence of the random affairs with certain relationship on functional layer
Column.
Top layer is test layer, it is used to configure different test cases, defines different constraint condition.
The verifying level of chip be divided into chip system grade (chip level), subsystem irrespective of size (sub-system level),
Module level (block level).Each level verifying emphasis is different.
In the verification environment of module level, need to drive the input port of DUT.
In the verification environment of subsystem irrespective of size, the input port of module is driven by up-stream module.
As shown in Fig. 2, design to be verified is modules A, modules A is in module level verification environment, module level verification ring
Border drives the input port of modules A, should be that module level verification environment arrow is directed toward modules A in figure；And in subsystem
In the verification environment of irrespective of size, up-stream module is increased, then the input port of modules A is driven by up-stream module；The verifying of module
Environment only needs to sample the port when being reused subsystem, i.e., only enables the sampling functions module of input port
Monitor。
The port signal quantity of DUT is hundreds of thousands of easily, and connection so multi signal, workload is huge, different levels verifying
The signal connection work of environment will be done one time from newly, be bound to cause waste, and be easy error, reduced verification efficiency.
Module level verification (BT, BlockTest) if environment can quilt whole-system verification/integrated verification (IT,
IntegrationTest it) reuses, then efficiency can be improved, but due to shown in Fig. 2, reuse the drive for needing to change port
The port of dynamic direction, DUT and verification environment is connected to different verifying levels because sense difference needs to develop respectively, therefore nothing
Method reuses.
Summary of the invention
Goal of the invention: in view of the above-mentioned drawbacks of the prior art, the present invention is intended to provide a kind of raising verification environment weight
With port connection method, system and the medium of property, to realize that the port of module level connects code in high-level verification environment
It reuses.
A kind of technical solution: port connection method improving verification environment reusability, comprising:
(1) it defines and connects for connecting DUT port signal with the port of verification environment macro, the port connection macroradical is according to testing
The level for demonstrate,proving environment determines the connection direction of signal:
When the level of verification environment is module level, with the port signal of checking assembly driving DUT；
When the level of verification environment is subsystem irrespective of size, with the port signal of checking assembly sampling DUT；
(2) signal that module level verification and subsystem level verification can reuse is connected using port defined in step (1)
Connect it is macro be attached, establish the connection relationship of DUT and verification environment.
Further, further includes: according to the level of DUT and verification environment, respectively in the verifying of module level and subsystem irrespective of size
Actual DUT port signal path and actual verification environment interface signal path are defined in environment.
Further, in step (1) further include: using DUT port signal path and verification environment interface signal path as
The input parameter of port connection macrodefinition.
Further, the connection macroradical of port described in step (1) determines the connection direction of signal according to the level of verification environment
Further include: the level instruction that definition is used to indicate verification environment level is macro, indicates the macro connection direction for determining signal according to level.
Further, it is described define be used to indicate verification environment level level instruction it is macro, macro decision is indicated according to level
The specific method in the connection direction of signal is:
In the verification environment of subsystem irrespective of size definition be used to indicate non-module level verification environment non-module level instruction it is macro,
It is macro that the non-module level instruction cannot be defined in the verification environment of module level；
When there is non-module level instruction macro, with the port signal of checking assembly sampling DUT；
Otherwise, with the port signal of checking assembly driving DUT.
Further, the step (1) further include: newly-built port threaded file uses port in the threaded file of port
Macro connection signal is connected, port threaded file is stored under all visible public directory of verification environments at different levels.
Further, the step (1) further include: port threaded file is covered into current file in preprocessing process
In.
A kind of verifying system improving verification environment reusability, including DUT and verification environment, the verification environment include life
Enable layer and functional layer；
Layer order includes driver and monitor, and driver and monitor are checking assembly, layer order for downwards with
DUT is connected, communicates upwards with functional layer；
Functional layer includes agency, and agency is transmitted to driver for being converted into individually ordering by high-rise affairs；
Driver is used for the order that Receiving Agent issues, and generates corresponding excited data, is input to DUT, works as verification environment
Level be module level when, drive the port signal of DUT；
Monitor is used to sample the port signal of DUT when the level of verification environment is subsystem irrespective of size.
It further, further include port link block, macro for defining and being connected using port, the port connects macro use
In connection DUT port signal and verification environment.
A kind of computer readable storage medium, the computer readable storage medium is for storing program code, the journey
Sequence code is for executing above-mentioned method.
The utility model has the advantages that the present invention proposes a kind of novel port connection method, according to the level of verification environment, signal is determined
Connection direction, when the level of verification environment be subsystem irrespective of size when, with checking assembly sampling DUT port signal, can be effective
It solves the problems, such as reuse, saves verifying workload, avoid reconnect signal and be artificially introduced mistake, improve verification efficiency.
Detailed description of the invention
Fig. 1 is verifying system schematic；
Fig. 2 is verifying connection schematic diagram；
Fig. 3 is the flow diagram of method.
Specific embodiment
The technical program is described in detail below by a most preferred embodiment and in conjunction with attached drawing.
A kind of verifying system improving verification environment reusability, can refer to Fig. 1 prior art, including DUT and verification environment,
The verification environment includes layer order and functional layer, set gradually from bottom to top signals layer, layer order, functional layer, scene layer and
Test layer, wherein verification environment includes generator, agency, driver, monitor, detector, scoreboard and asserts.Occur
It device, driver, monitor, detector, scoreboard and asserts, each is checking assembly.
The present embodiment stresses signals layer, layer order and functional layer；
Signals layer includes DUT and interface；
Layer order is on signals layer, for being connected with DUT downwards, by signal layer interface upwardly through transaction-level channel
It is communicated with functional layer；Layer order includes driver and monitor, and for indicating and verifying asserting for expected result.
Functional layer is located on layer order, is the abstract of high level operation, passes through transaction-level tunneling traffic between each other.Packet
It includes and acts on behalf of (not shown), detector and scoreboard, act on behalf of the high-rise affairs transmitted for receiving upper layer, high-rise affairs are turned
It changes individually order into and is transmitted to driver；
Driver is used for the order that Receiving Agent issues, and generates corresponding excited data, is input to DUT, works as verification environment
Level be module level when, drive the port signal of DUT；
Monitor is used to sample the port signal of DUT when the level of verification environment is subsystem irrespective of size.
Scoreboard is used to the response of dynamic prediction design, is applied to the excitation of DUT while being applied to scoreboard, in scoreboard
Transfer function the excitation of input is wholly converted into the form finally responded, and be stored in data structure, to pass to inspection
Device is looked into, scoreboard is also recorded and counted to all affairs, records the affairs number of execution, the affairs that success fails
Number, if a certain affairs are missed.
Detector by the predicated response stored in the data and scoreboard that transmit monitor be compared to judge to
Whether brake is correct.
Scene layer is primarily used to generate the sequence of the random affairs with certain relationship on functional layer.
Top layer is test layer, it is used to configure different test cases, defines different constraint condition.
In addition, verifying system further includes port link block (not shown), it is macro and use for defining port connection
Port connects the macro connection relationship for establishing DUT and verification environment, and the port connection is macro for connecting DUT port signal and verifying
Environment.
As shown in Figure 3.The port connection method for the raising verification environment reusability that the system uses, comprising:
(1) it defines and connects for connecting DUT port signal with the port of verification environment macro, port has been created in the present embodiment
The code of threaded file, port connection is placed in individual file, to use in the verification environment of multiple levels, in port
Macro connection signal is connected using port in threaded file, it is all visible public that port threaded file is stored in verification environments at different levels
Under catalogue, to be used in verification environments at different levels.
Such as in the individual files of entitled dut_interface_connnet.sv, using defined in step 1
Interface_connect macro (i.e. port connection is macro), to connect DUT and verification environment, code sample is as follows:
`interface_connect(`BT_DUT_IF.signal_a,`BT_ENV_IF.signal_a)
`interface_connect(`BT_DUT_IF.signal_b,`BT_ENV_IF.signal_b)
`interface_connect(`BT_DUT_IF.signal_c,`BT_ENV_IF.signal_c)
…
The macrodefinition has input parameter, and DUT port signal path and verification environment interface interface signal path are made
The input parameter of macrodefinition is connected for port, port connects the connection direction that macroradical determines signal according to the level of verification environment:
When the level of verification environment is module level, the port signal of DUT, checking assembly herein are driven with checking assembly
It is understood that referring to this checking assembly of driver；
When the level of verification environment is subsystem irrespective of size, the validation group of the port signal of DUT herein is sampled with checking assembly
Part is it is understood that refer to this checking assembly of monitor；
The level of verification environment is the concrete implementation method in the present embodiment by artificially distinguishing herein are as follows:
After the level for artificially having distinguished verification environment, the level that definition is used to indicate verification environment level indicates macro, root
The macro connection direction for determining signal is indicated according to level.Such as:
In the verification environment of subsystem irrespective of size definition be used to indicate non-module level verification environment non-module level instruction it is macro,
It is macro that the non-module level instruction cannot be defined in the verification environment of module level；Such as it is macro using FOR_IT, to indicate non-module level
Verification environment.It is macro that this cannot be defined in the verification environment of module level.
When there is non-module level instruction macro, with the port signal of checking assembly sampling DUT；
Otherwise, with the port signal of checking assembly driving DUT.
Such as the level of verification environment is distinguished in following Examples with FOR_IT, it is only fixed in non-module level verification environment
Justice, assignment statement left side of the equal sign are verification environments, and the right is DUT；
Contrary in module level verification environment, i.e., assignment statement left side of the equal sign is DUT, and the right is verification environment.
In order to use the port threaded file, port threaded file need to be covered into current file in preprocessing process
In.The port include threaded file in top layer, include are emulated in the DUT of module level and subsystem irrespective of size respectively in the present embodiment
It is comprising header file order, for specified header file to be embedded in source file, example is as follows:
(2) signal that module level verification and subsystem level verification can reuse is connected using port defined in step (1)
Connect it is macro be attached, establish the connection relationship of DUT and verification environment.
Incoming port connects the example path that macro parameter is signal, the signal example path in different levels verification environment
It is different.
Therefore, the present embodiment further comprises the steps of: the level according to DUT and verification environment, respectively in module level and subsystem
Actual DUT port signal path and actual verification environment interface signal path are defined in the verification environment of grade.The step can
With before step (1), within, later or step (2) after.
Such as in Makefile, module level compiles option and increases
+ define+BT_DUT_IF=testbench.BT, and subsystem irrespective of size compiling option increases
+ define+BT_DUT_IF=testbench.IT.BT
A kind of computer readable storage medium, the computer readable storage medium is for storing program code, the journey
Sequence code is for executing above-mentioned method.
The above is only the preferred embodiment of the present invention, for those skilled in the art, are not taking off
Under the premise of from the principle of the invention, several improvements and modifications can also be made, these improvements and modifications also should be regarded as of the invention
Protection scope.
Claims (10)
1. a kind of port connection method for improving verification environment reusability characterized by comprising
(1) it defines and connects for connecting DUT port signal with the port of verification environment macro, the port connection macroradical is according to verifying ring
The level in border determines the connection direction of signal:
When the level of verification environment is module level, with the port signal of checking assembly driving DUT；
When the level of verification environment is subsystem irrespective of size, with the port signal of checking assembly sampling DUT；
(2) signal that can be reused to module level verification and subsystem level verification is connect macro using port defined in step (1)
It is attached, establishes the connection relationship of DUT and verification environment.
2. a kind of port connection method for improving verification environment reusability according to claim 1, which is characterized in that also wrap
It includes: according to the level of DUT and verification environment, defining the end actual DUT in the verification environment of module level and subsystem irrespective of size respectively
Mouth signal path and actual verification environment interface signal path.
3. a kind of port connection method for improving verification environment reusability according to claim 1, which is characterized in that step
(1) in further include: DUT port signal path is connected to the input ginseng of macrodefinition with verification environment interface signal path as port
Number.
4. a kind of port connection method for improving verification environment reusability according to claim 1, which is characterized in that step
(1) port described in connects the connection direction that macroradical determines signal according to the level of verification environment further include: definition, which is used to indicate, tests
The level instruction for demonstrate,proving environment levels is macro, indicates the macro connection direction for determining signal according to level.
5. a kind of port connection method for improving verification environment reusability according to claim 4, which is characterized in that described
The level instruction that definition is used to indicate verification environment level is macro, and the specific side in the macro connection direction for determining signal is indicated according to level
Method is:
In the verification environment of subsystem irrespective of size definition be used to indicate non-module level verification environment non-module level instruction it is macro, in module
It is macro that the non-module level instruction cannot be defined in the verification environment of grade；
When there is non-module level instruction macro, with the port signal of checking assembly sampling DUT；
Otherwise, with the port signal of checking assembly driving DUT.
6. a kind of port connection method for improving verification environment reusability according to claim 1, which is characterized in that described
Step (1) further include: newly-built port threaded file connects macro connection signal using port in the threaded file of port, by port
Threaded file is stored under all visible public directory of verification environments at different levels.
7. a kind of port connection method for improving verification environment reusability according to claim 6, which is characterized in that described
Step (1) further include: cover port threaded file in current file in preprocessing process.
8. a kind of verifying system for improving verification environment reusability, which is characterized in that including DUT and verification environment, the verifying
Environment includes layer order and functional layer；
Layer order includes driver and monitor, and driver and monitor are checking assembly, for be connected with DUT downwards, to
It is upper to be communicated with functional layer；
Functional layer includes agency, and agency is transmitted to driver for being converted into individually ordering by high-rise affairs；
Driver is used for the order that Receiving Agent issues, and generates corresponding excited data, is input to DUT, when the layer of verification environment
When grade is module level, the port signal of DUT is driven；
Monitor is used to sample the port signal of DUT when the level of verification environment is subsystem irrespective of size.
9. a kind of verifying system for improving verification environment reusability according to claim 8, which is characterized in that further include end
Mouth link block, macro for defining and being connected using port, the port connection is macro for connecting DUT port signal and verifying ring
Border.
10. a kind of computer readable storage medium, which is characterized in that the computer readable storage medium is for storing program generation
Code, said program code require 1 to 7 described in any item methods for perform claim.
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