CN111858306B - Chip verification method and device, chip and storage medium - Google Patents
Chip verification method and device, chip and storage medium Download PDFInfo
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- CN111858306B CN111858306B CN202010540313.1A CN202010540313A CN111858306B CN 111858306 B CN111858306 B CN 111858306B CN 202010540313 A CN202010540313 A CN 202010540313A CN 111858306 B CN111858306 B CN 111858306B
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- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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Abstract
The application provides a chip verification method, a device, a chip and a storage medium, wherein the chip comprises a verification system, the verification system comprises a verification environment of a subsystem level and a verification environment of an IP core level, the verification environment of the subsystem level and the verification environment of the IP core level comprise corresponding test scene layers, the test scene layers of the subsystem level and the test scene layers of the IP core layer multiplex the core environment layers, and the method is applied to the chip and comprises the following steps: acquiring parameter information of a test case to be tested through a test scene layer of an IP core layer and a test scene layer of a subsystem layer; acquiring a plurality of operation execution information corresponding to the test case to be tested according to the parameter information; determining, by the core environment layer, a plurality of target verification components from a plurality of verification components encapsulated in the core environment layer according to the plurality of operation execution information; and distributing each operation execution information to a corresponding target verification component through the core environment layer so as to verify the test case to be tested.
Description
Technical Field
The present application relates to the field of chip verification, and in particular, to a chip verification method, device, chip and storage medium.
Background
There are multiple protocols or modules of the same class in a System on Chip (SoC) to form subsystems facing the same kind of functions, such as PCI-E (peripheral component interconnect express), SATA (Serial ATA), universal serial bus (Universal Serial Bus, USB) and other IP core protocols all serve the data transmission function, and for these IP core protocols with the same kind of functions, there is multiplexing of the verification components under different verification environments.
The existing multiplexing verification components are instantiated into different verification environments, and the configuration is required to be carried out on each environment top layer (as shown in fig. 1), that is, when chip verification is carried out, related verification components (such as a subsystem test layer and an IP core environment test layer in fig. 1) are required to be called from the environment top layer for multiple times, so that the problems of repeated work and verification mismatch caused by different configuration between environments are increased to a certain extent.
Disclosure of Invention
The embodiment of the application aims to provide a chip verification method, a device, a chip and a storage medium, which are used for solving the problems of repeated work and verification mismatch caused by the fact that the prior reusable verification component needs to be configured and invoked for many times by each environment top layer during chip verification.
In a first aspect, an embodiment provides a chip verification method, where the chip includes a verification system, where the verification system includes a verification environment at a subsystem level and a verification environment at an IP core level, where the verification environment at the subsystem level includes a test scene layer at the subsystem level, and the verification environment at the IP core level includes a test scene layer at the IP core layer, where the test scene layer at the subsystem level and the test scene layer at the IP core layer multiplex a core environment layer, where the method is applied to the chip, where the method includes: acquiring a test case to be tested through a test scene layer of the IP core layer and a test scene layer of a subsystem layer, wherein the test case to be tested carries parameter information applied to different layers of verification environments and different IP cores; acquiring a plurality of operation execution information corresponding to the test case to be tested according to the parameter information; transmitting the operation execution information to the core environment layer through the test scene layer of the IP core layer and the test scene layer of the subsystem layer; determining, by the core environment layer, a plurality of target verification components from a plurality of verification components encapsulated in the core environment layer according to the plurality of operation execution information; and distributing each operation execution information to a corresponding target verification component through the core environment layer so that the plurality of target verification components verify the test cases to be tested.
In the chip verification method, the test scene layer of the IP core layer and the test scene layer of the subsystem layer are used for acquiring the test cases to be tested, a plurality of operation execution information is acquired according to the acquired parameter information of the test cases to be tested, then a plurality of target verification components are determined from a plurality of verification components packaged in the core environment layer according to the operation execution information, and further verification is carried out on the test cases to be tested according to the determined operation execution information of the target verification components and the operation execution information of each target verification component.
In an optional implementation manner of the first aspect, the plurality of operation execution information includes a plurality of operation execution instructions, and determining, by the core environment layer, a plurality of target verification components from a plurality of verification components encapsulated in the core environment layer according to the plurality of operation execution information includes: calling an internal storage method of the core environment layer through the core environment layer according to each operation execution instruction to translate each operation execution information into configuration information of a corresponding target verification component; determining, by the core environment layer, a corresponding target verification component from a plurality of verification components encapsulated in the core environment layer according to configuration information of each target verification component; distributing, by the core environment layer, the each operation execution information to a corresponding target verification component, including: and distributing the configuration information translated by each operation execution information to the corresponding target verification component.
In an optional implementation manner of the first aspect, the parameter information includes an IP core protocol type identifier of the test case, the verification environment of the IP core level further includes a general method library, a plurality of operation execution information corresponding to test cases of different IP cores with protocol functions are encapsulated in the general method library, the plurality of operation execution information includes a plurality of common operation execution information corresponding to test cases of different IP cores with protocol functions for a common portion thereof, and a plurality of difference operation execution information corresponding to different portions thereof, and the obtaining a plurality of operation execution information corresponding to the test case according to the parameter information includes: searching the common operation execution information in the general method library, searching the corresponding differential operation execution information in the general method library according to the protocol type identifier of the IP core, and carrying out method reloading on the differential operation execution information.
In the embodiment of the design, the common operation execution information and the differential operation execution information corresponding to the test cases with similar functions but different IP core types are split and then packaged in the general method library, and special reconstruction is carried out in a method reloading mode during verification, so that the problem that development and maintenance of independent verification functions of each test case are not facilitated due to the fact that the differential part of each test case with the same type of functions is completely embedded in the common part in the same-level verification environment is solved, and verification development efficiency of each test case in the same level is improved.
In a second aspect, an embodiment provides a chip verification apparatus, where the verification system includes a subsystem-level verification environment and an IP core-level verification environment, the subsystem-level verification environment includes a subsystem-level test scene layer, the IP core-level verification environment includes an IP core-level test scene layer, and the subsystem-level test scene layer and the IP core-level test scene layer multiplex a core environment layer, where the apparatus is applied to the chip, and where the apparatus includes: the acquisition module is used for acquiring a test case to be tested through the test scene layer of the IP core layer and the test scene layer of the subsystem layer, wherein the test case to be tested carries parameter information applied to different layers of verification environments and different IP cores; acquiring a plurality of operation execution information corresponding to the test case to be tested according to the parameter information; the sending module is used for transmitting the operation execution information to the core environment layer through the test scene layer of the IP core layer and the test scene layer of the subsystem layer; a determining module, configured to determine, by the core environment layer, a plurality of target verification components from a plurality of verification components encapsulated in the core environment layer according to the plurality of operation execution information; the distribution module is used for distributing each operation execution information to the corresponding target verification component through the core environment layer so that the plurality of target verification components verify the test cases to be tested.
In the chip verification device designed above, multiple operation execution information is obtained by the test scene layer according to the obtained parameter information of the test case to be tested, multiple target verification components are determined from multiple verification components packaged in the core environment layer according to the multiple operation execution information, and then the test case to be tested is verified according to the determined multiple target verification components and the operation execution information corresponding to each target verification component.
In an optional implementation manner of the second aspect, the plurality of operation execution information includes a plurality of operation execution instructions, and the determining module is specifically configured to invoke, by the core environment layer, the internal storage method of the core environment layer according to each operation execution instruction to translate each operation execution information into configuration information of a corresponding target verification component; determining, by the core environment layer, a corresponding target verification component from a plurality of verification components encapsulated in the core environment layer according to configuration information of each target verification component; the allocation module is specifically configured to allocate the configuration information translated from each operation execution information to the corresponding target verification component.
In an optional implementation manner of the second aspect, the parameter information of the test case includes an IP core type identifier of the test case, the verification environment of the test case further includes a general method library, and a plurality of common operation execution information corresponding to test cases with different IP core types and having similar functions and a plurality of differential operation execution information corresponding to test cases with each IP core type are packaged in the general method library, and the obtaining, according to the parameter information of the test case, a plurality of operation execution information corresponding to the test case includes: searching the common operation execution information in the general method library, searching the corresponding differential operation execution information in the general method library according to the protocol type identifier of the IP core, and realizing the reloading of the differential operation execution methods according to the specific requirements of a test scene.
In a third aspect, an embodiment provides a chip, the chip includes a verification system, the verification system includes a verification environment of a subsystem level and a verification environment of an IP core level, the verification environment of the subsystem level includes a test scene layer of the subsystem level, the verification environment of the IP core level includes a test scene layer of the IP core level, the test scene layer of the subsystem level and the test scene layer of the IP core level multiplex a core environment layer, the test scene layer of the subsystem level and the test scene layer of the IP core layer are in communication connection with the core environment layer, a plurality of verification components are packaged in the core environment layer, and the verification components are obtained through transmission of the test scene layer of the subsystem level and the test scene layer of the IP core layer.
According to the chip designed in the design, the verification components of the test scene layers of the verification environment and the verification environment of the IP core layer are packaged in the core environment layer of the test case, and are uniformly controlled and configured by the core environment layer, so that the problems of repeated operation increase and verification mismatch caused by the fact that the related verification components are required to be called from the environment top layer for many times when the conventional reusable verification components are configured by the environment top layer during chip verification are solved, the trouble and risk that the configuration of the verification components is required to be synchronized in a cross-layer environment are avoided, the chip verification development efficiency is improved, and the verification environment maintenance cost of subsequent item iteration is reduced.
In an optional implementation manner of the third aspect, common operation execution information corresponding to a plurality of different IP core types with similar functions and differentiated operation execution information corresponding to each IP core type are distributed in the test scene layer of the subsystem level and the test scene layer of the IP core level.
In an optional implementation manner of the third aspect, the verification environment of the IP core level further includes a general method library, where the general method library communicates with the test scenario layer of the subsystem level, the test scenario layer of the IP core level, and the core environment layer, and multiple common operation execution information corresponding to test cases of different IP core types with similar functions and multiple differential operation execution information corresponding to test cases of each IP core type are encapsulated in the general method library.
In a fourth aspect, embodiments provide a non-transitory readable storage medium having stored thereon a computer program which, when executed by a processor, performs the method of any of the alternative implementations of the first aspect.
In a fifth aspect, embodiments provide a computer program product which, when run on a computer, causes the computer to perform the method of any of the alternative implementations of the first aspect.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and should not be considered as limiting the scope, and other related drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a prior cross-level verification environment;
FIG. 2 is a schematic diagram of a first configuration of a verification system according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a second structure of a verification system according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a model of a comparative, same-level verification environment;
FIG. 5 is a schematic diagram of a general method library according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a third configuration of a verification system according to an embodiment of the present application;
FIG. 7 is a first flowchart of a chip verification method according to an embodiment of the present application;
FIG. 8 is a second flowchart of a chip verification method according to an embodiment of the present application;
FIG. 9 is a third flowchart of a chip verification method according to an embodiment of the present application;
fig. 10 is a schematic structural diagram of a chip verification device according to an embodiment of the present application.
Icon: 1-a verification system; 10-verification environment at subsystem level; 101-a test scene layer of a subsystem hierarchy; a 20-IP core level verification environment; 201-a test scene layer of an IP core layer; 202-a core environment layer; 2021-authentication component; 203-a general method library; 300-an acquisition module; 302-a transmitting module; 304-a determination module; 306-an allocation module; 308-a lookup module.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.
The embodiment of the application is mainly characterized in that related verification components originally in each environment test layer are packaged into the core environment layer of the test case, and the verification components are uniformly controlled and configured by the core environment layer so as to achieve the effect of improving the verification development efficiency.
First embodiment
As shown in fig. 2, an embodiment of the present application provides a chip, where the chip includes a verification system 1, where the verification system 1 includes a subsystem-level verification environment 10 and an IP core-level verification environment 20, where the IP core-level verification environment 20 includes an IP core-level test scene layer 201 and a core environment layer 202, where the subsystem-level verification environment 10 includes the subsystem-level test scene layer 101, where the subsystem-level verification environment 10 and the IP core-level verification environment 20 multiplex the core environment layer 202, where the subsystem-level test scene layer 101 and the IP core-level test scene layer 201 are communicatively connected to the core environment layer 202, and where the core environment layer 202 encapsulates a plurality of verification components 2021, where the plurality of verification components 2021 are used to verify a test case.
The IP (Intellectual Property) core described above can be interpreted as an intellectual property core, in the field of integrated circuit design, refers to a functional module that meets specific specifications and can be reused in the design, and the test case can represent an IP core protocol to be verified, for example, the aforementioned IP protocols with data transmission functions such as PCI-E, SATA, USB; the verification environment 20 at the IP core level represents a verification environment of test cases having the same kind of function, that is, a verification environment of one IP core level is multiplexed together with test cases having the same function, for example, the aforementioned multiple IP protocols having the same kind of function of data transmission multiplex the verification environment of the same IP core level. The communication connection between the test scene layer 101 of the subsystem level and the test scene layer 201 of the IP core level and the core environment layer 202 may perform data transmission communication through multiple interfaces between the test scene layer and the core environment layer, and the multiple verification components 2021 may be all verification components required for verification of similar functional test cases, for example, all UVC components related to multiple IP protocols with data transmission functions, such as the aforementioned PCI-E, SATA, USB; the validation component can generally include, for example, drivers, monitors, assertions, agents, checkers, scoreboards, and the like.
In the conventional manner, the plurality of verification components 2021 are distributed in the test scenario layer 201 at the IP core level and the test scenario layer 101 at the subsystem level, and when performing test case verification, it is necessary to continuously call the verification components related to the test case that are configured in the test scenario layer 201 at the IP core level and the test scenario layer 101 at the subsystem level, so as to perform verification of the test case. In contrast, in the solution of the present application, the plurality of verification components 2021 are transferred to the core environment layer 202 through the test scenario layer 101 at the subsystem level and the test scenario layer 201 at the IP core level, so that the plurality of verification components 2021 are encapsulated in the core environment layer 202 and are uniformly controlled by the core environment layer 202, so that when verifying the test case, only the core environment layer 202 is required to uniformly configure related verification components, and no continuous call of the test layer is required.
According to the designed chip, the test case to be tested is obtained through the test scene layer of the IP core layer and the test scene layer of the subsystem layer, a plurality of operation execution information is obtained according to the obtained parameter information of the test case to be tested, a plurality of target verification components are determined from a plurality of verification components packaged in the chip through the core environment layer according to the operation execution information, and then the test case to be tested is verified according to the determined operation execution information of the target verification components and the operation execution information corresponding to each target verification component.
In an alternative implementation manner of this embodiment, as shown in fig. 3, the verification environment 20 at the IP core level further includes a general method library 203, where the general method library 203 may be in communication with the test scenario layer 201 and the core environment layer 202 at the IP core level, and multiple operation execution information corresponding to test cases of different IP cores with protocol functions are encapsulated in the general method library 203, where the multiple operation execution information includes multiple common operation execution information corresponding to test cases of different IP cores with protocol functions for common parts thereof, and multiple distinguishing operation execution information corresponding to different distinguishing parts. The test cases of different types with the same type function have the same type of data transmission function as the PCI-E, SATA, USB and the like, but the IP protocols respectively corresponding to the test cases are different and belong to different types; the operation execution information represents various operation instructions to be executed when verification is performed and other information, wherein each operation instruction can be an operation instruction to be executed by each verification component, an operation instruction to be executed when a corresponding verification component is searched, and the like, and the other information can be interface data information and the like corresponding to each verification component corresponding to the test case; the common operation execution information and the differential operation execution information corresponding to the test cases of the same kind of function are understood to be that the test cases of the same kind of function have a part of common operation execution information (common part) and operation execution information (differential part) unique to each test case, the common part and the differential part of the different test cases of the same kind of function are packaged in the common method library 203, and the differential part of the test cases to be verified is updated or loaded according to the method loading in the method library during verification.
The above embodiment is different from the existing mode in that, in the existing mode, in order to ensure reusability, the distinguishing part of the same-level verification environment shared by all test cases with the same type of functions is completely embedded in the shared part (as can be seen from the composition of all IP protocols in fig. 4), and is distributed in the subsystem level and the test scene layer of the IP core level, so that the development and maintenance of the independent verification functions of all test cases are not facilitated when the reusability is inherited; the general method library of the scheme of the application is shown in fig. 5, the common operation execution information and the differential operation execution information corresponding to the test cases with the same type of functions but different types are split and then packaged in the general method library, and the common method library is loaded in a method reloading mode during verification, so that the problem that the development and maintenance of the independent verification function of each test case are not facilitated because the differential part of the common-level verification environment shared by each test case with the same type of functions is completely embedded in the common part at present is solved, and the verification development efficiency of each test case in the same level is improved.
Based on the foregoing embodiments, the above-mentioned schemes may be specifically explained by taking each IP protocol having the same kind of function as an example, as shown in fig. 6, the verification system includes a verification environment of a subsystem and an IP verification environment, the verification environment of the subsystem level includes a TEST scene layer (sys_test_top in the drawing), the verification environment of the IP core level includes a TEST scene layer (ip_test_top in the drawing), a core environment layer (central_env or ip_env in the drawing) of the IP, and a general method library (ip_method_utends in the drawing), in which a plurality of verification Components (reusable_ip_components) required for verification of each IP protocol having the same kind of function are packaged, and a plurality of common operation execution information (common part) of the IP protocol having the same kind of function and a plurality of different operation execution information (different part) corresponding to each IP protocol are packaged in the general method library, so as to form the verification system designed by the present application.
Second embodiment
As shown in fig. 7, the present application provides a chip verification method, which is mainly applied to a chip having a verification system described in the first embodiment, and specifically includes the following steps:
step S200: parameter information of a test case to be tested is obtained through a test scene layer of the IP core layer and a test scene layer of the subsystem layer, and a plurality of operation execution information corresponding to the test case to be tested is obtained according to the parameter information of the test case to be tested.
Step S202: and transmitting the operation execution information to the core environment layer through the test scene layer of the IP core layer and the test scene layer of the subsystem layer.
Step S204: a plurality of target verification components are determined by the core environment layer from a plurality of verification components encapsulated in the core environment layer according to the plurality of operation execution information.
Step S206: and distributing each operation execution information to a corresponding target verification component through the core environment layer so that the multiple target verification components verify the test cases to be tested.
In step S200, the test scene layer of the IP core layer and the test scene layer of the subsystem layer acquire parameter information of the test case to be tested during chip verification, the parameter information is applied to different level verification environments and different IP cores, wherein the parameter information of the test cases with similar functions is different from each other, so that each test case has unique parameter information, and further the test case can be identified or the corresponding verification component and operation execution information required for verification can be found according to the unique parameter information of the test case. According to the foregoing description, if it is required to identify which test the test case is, the parameter information of the test case may be equivalent to the identity of the test case, and the test layer may identify which test case needs to be verified by the parameter information, for example, when performing the verification of the IP protocol with the data transmission function, the test layer of the IP may obtain the parameter information of the IP to be tested, so as to identify which IP protocol of the IP protocols to be verified, which has the data transmission function, according to the parameter information of the IP to be tested.
In another embodiment, it is also possible to directly use the parameter information of the test case to obtain a plurality of operation execution information corresponding to the test case without identifying which test case is specific, where the parameter information of the test case has a correspondence with the corresponding plurality of operation execution information, and the corresponding plurality of operation execution information can be searched through the parameter information; the plurality of operation execution information in the present embodiment may be in a form in which the common portion and the differential portion distributed in the test layer of the test case are embedded together in the existing manner described in the first embodiment; the common part and the differential part described in the first embodiment may also be in the form of being split and packaged in a common method library. After obtaining the plurality of operation execution information corresponding to the test case to be tested, executing step S202, the test scene layer of the IP core layer and the test scene layer of the subsystem layer transmit the obtained plurality of operation execution information to the core environment layer through the communication interface with the core environment layer, and further executing step S204.
In step S204, the core environment layer determines a plurality of target verification components from the plurality of verification components packaged inside according to the plurality of operation execution information obtained by transmission. In the first embodiment, verification components of all test cases with similar functions are described as being packaged in a core environment layer of the test case, so that a plurality of verification components are arranged in the core environment layer, and only part of verification components needed in verification of a certain test case are needed, and then a target verification component needed in verification of the test case needs to be determined in the verification components. The specific implementation manner may be that the test scene layer of the IP core layer and the test scene layer of the subsystem layer obtain a plurality of operation execution information according to the parameter information of the test case to be tested, where the plurality of operation execution information includes related information of the verification component corresponding to each operation execution information, so that the core environment layer can determine a plurality of target verification components according to the related information of the verification component corresponding to each operation execution information, and then execute step S206, the core environment layer distributes each operation execution information to the corresponding target verification component to verify the test case to be tested.
The specific manner in which the target verification component performs the corresponding operation execution information to perform verification in step S206 is the same as the existing verification manner, for example, it has been described in the first embodiment that the verification component may generally include, for example, a Driver (Driver), a Monitor (Monitor), an Assertion (Assertion), an Agent (Agent), a Checker (Checker), and a Scoreboard (Scoreboard), and the Agent receives high-level transactions transmitted from an upper layer and converts these high-level transactions into separate commands to be provided to the Driver during verification; after receiving the command sent by the agent, the driver generates corresponding incentive data, the incentive data is input into a module DUT (Design Under Test) to be verified, the design to be verified is designed, the scoreboard is used for dynamically predicting the response of the design, the incentive applied to the DUT is simultaneously applied to the scoreboard, the conversion function in the scoreboard converts the input incentive into the form of the final response, and the final response is stored in a data structure so as to be transmitted to the checker, the scoreboard can record and count all the transactions, record the number of the executed transactions, the number of the successful and failed transactions, whether a certain transaction is missed or not, and the like; the monitor is used for monitoring the change of the interface signal and converting the change into a transaction to be transmitted to the checker; the checker judges whether the test case to be tested is correct or not by comparing the data transmitted by the monitor with the prediction response stored in the scoreboard; assertions are used to mark and verify the expected results.
In the chip verification method, the test scene layer of the IP core layer and the test scene layer of the subsystem layer are used for acquiring the test cases to be tested, a plurality of operation execution information is acquired according to the acquired parameter information of the test cases to be tested, then a plurality of target verification components are determined from a plurality of verification components packaged in the core environment layer according to the operation execution information, and further verification is carried out on the test cases to be tested according to the determined operation execution information of the target verification components and the operation execution information of each target verification component.
In an optional implementation manner of this embodiment, in the foregoing implementation manner, a plurality of operation execution information includes related information of a verification component corresponding to each operation execution information, and specifically, the plurality of operation execution information includes a plurality of operation execution instructions, where the operation execution instructions are expressed as operation instructions for finding a corresponding target verification component, and on this basis, as shown in fig. 8, step S204 may specifically be the following steps:
step S2040: and calling an internal storage method of the core environment layer through the core environment layer according to each operation execution instruction to translate each operation execution information into configuration information of a corresponding target verification component.
Step S2042: and determining a corresponding target verification component from a plurality of verification components packaged in the core environment layer according to the configuration information of each target verification component through the core environment layer.
Based on the above, step S206 distributes the plurality of operation execution information to the corresponding target verification component through the core environment layer, specifically may be the following steps:
step S2060: and distributing the configuration information translated by each operation execution information to the corresponding target verification component through the core environment layer.
In step S2040, after receiving the plurality of operation execution information transmitted by the test scene layer, the core environment layer invokes the method stored internally according to the operation instruction in each operation execution information to translate each operation execution information into the configuration information of the corresponding target verification component, and then searches the corresponding target verification component according to the configuration information of each target verification component, and distributes the corresponding configuration information to the corresponding target verification component. The configuration information includes the identifier of the target verification component corresponding to each operation execution information and the method to be executed in the corresponding verification process.
In step S2060, each of the plurality of operation execution instructions has a corresponding target verification component, that is, one target verification component may execute the plurality of operation execution instructions, so the core environment layer may assign the corresponding configuration information translated by each operation execution instruction to the corresponding target verification component, so that each searched target verification component executes the corresponding operation execution, thereby completing verification of the test case to be tested.
In an alternative implementation manner of the present embodiment, the foregoing description has been given of a form in which the common portion and the differential portion are embedded together in the test scenario layer distributed at the subsystem level and the test scenario layer at the IP core level in the existing manner described in the first embodiment; the common part and the differential part described in the first embodiment may also be in the form of being split and packaged in a common method library.
If the test case is in one form, the specific way of acquiring the operation execution information corresponding to the test case according to the parameter information of the test case in step S200 is to directly search the shared part of the test case in the test scene layer of the subsystem level and the test scene layer of the IP core level according to the parameter information of the test case, and search the different parts embedded in the shared part, so as to obtain the operation execution information of the test case.
If the parameter information of the test case to be tested is in the second form, the parameter information of the test case to be tested includes type identifiers of an IP core protocol, and the test cases of different IP cores having protocol functions encapsulated in the universal method library respectively correspond to a plurality of operation execution information, where the plurality of operation execution information includes a plurality of common operation execution information corresponding to common parts of the test cases of different IP cores having protocol functions, and a plurality of distinguishing operation execution information corresponding to distinguishing parts, where the plurality of distinguishing operation execution information corresponding to each type of test case has a corresponding relationship with the type identifiers of the test cases, as shown in fig. 9, step S200 may specifically be:
Step S2000: searching a plurality of pieces of common operation execution information in the general method library, and searching a plurality of corresponding pieces of distinguishing operation execution information in the general method library according to the protocol type identification of the IP core.
Step S2002: and carrying out method reloading on the execution information of the multiple distinguishing operations.
In step S2000, since the plurality of common operation execution information (common portion) and the plurality of distinguishing operation execution information (distinguishing portion) are split and packaged in the common method library, and the common portion is a portion that is executed during each verification, the corresponding identifier may not be set, it may be set to be searched during each search, the distinguishing portion is a unique portion of each type of test case, it may be set to correspond to the type identifier of the corresponding IP core protocol, the plurality of distinguishing operation execution information required during verification of the test case to be tested may be found through the type identifier of the IP core protocol, and further, step S2002 is executed to splice the common portion and the distinguishing portion to perform method reload, so that the plurality of operation execution information may be obtained, and the distinguishing portion may also be updated during the method reload, for example, during the next verification, only the distinguishing portion needs to be replaced and then the method reload, so that the operation information required to be executed during the next verification may be obtained.
In the embodiment of the design, the shared operation execution information and the differentiated operation execution information which have the same type of functions but are corresponding to different types of test cases are split and then packaged in a general method library, and are loaded in a method reloading mode when verification is carried out, so that the problem that development and maintenance of independent verification functions of each test case are not facilitated due to the fact that a distinguishing part of each test case sharing the same type of functions is completely embedded in a shared part in the same-level verification environment is solved, and verification development efficiency of each test case in the same level is improved.
Third embodiment
Fig. 10 shows a schematic block diagram of a chip authentication apparatus according to the present application, which is applied to a chip including the authentication system of the first embodiment, and it should be understood that the apparatus corresponds to the method embodiment executed in fig. 7 to 9 described above, and is capable of executing the steps involved in the method of the second embodiment, and specific functions of the apparatus may be referred to the above description, and detailed descriptions thereof are omitted herein as appropriate to avoid redundancy. Specifically, the device comprises: the acquiring module 300 is configured to acquire a test case to be tested through a test scene layer of the IP core layer and a test scene layer of a subsystem layer, where the test case to be tested carries parameter information applied to different layer verification environments and different IP cores; acquiring a plurality of operation execution information corresponding to the test case to be tested according to the parameter information; a sending module 302, configured to transmit the plurality of operation execution information to the core environment layer through a test scene layer of the IP core layer and a test scene layer of a subsystem layer; a determining module 304, configured to determine, by the core environment layer, a plurality of target verification components from a plurality of verification components encapsulated in the core environment layer according to the plurality of operation execution information; and the allocation module 306 is configured to allocate each operation execution information to a corresponding target verification component through the core environment layer, so that the multiple target verification components verify the test case to be tested.
In the chip verification device designed above, multiple operation execution information is obtained by the test scene layer according to the obtained parameter information of the test case to be tested, multiple target verification components are determined from multiple verification components packaged in the core environment layer according to the multiple operation execution information, and then the test case to be tested is verified according to the determined multiple target verification components and the operation execution information corresponding to each target verification component.
In an alternative implementation manner of this embodiment, the plurality of operation execution information includes a plurality of operation execution instructions, and the determining module 304 is specifically configured to invoke, by the core environment layer, a method for storing in the core environment layer according to each operation execution instruction to translate each operation execution information into configuration information of a corresponding target verification component; determining a corresponding target verification component from a plurality of verification components packaged in the core environment layer according to configuration information of each target verification component through the core environment layer; the allocation module 306 is specifically configured to allocate the configuration information translated from each operation execution information to the corresponding target verification component.
In an alternative implementation manner of the present embodiment, the parameter information of the test case includes an IP core type identifier of the test case, the verification environment of the test case further includes a general method library, a plurality of common operation execution information corresponding to test cases with different IP core types having similar functions and a plurality of differentiated operation execution information corresponding to test cases with each IP core type are packaged in the general method library, and the search module 308 is specifically configured to search the general method library for the plurality of common operation execution information, search the general method library for the corresponding plurality of differentiated operation execution information according to the protocol type identifier of the IP core, and implement reloading of the plurality of differentiated operation execution methods according to specific requirements of a test scenario.
Fourth embodiment
The present application provides a non-transitory storage medium having stored thereon a computer program which, when executed by a processor, performs the method of the second embodiment, any optional implementation of the second embodiment, such as step S200 to step S206: acquiring a test case to be tested through a test scene layer of an IP core layer and a test scene layer of a subsystem layer, wherein the test case to be tested carries parameter information applied to different layers of verification environments and different IP cores; acquiring a plurality of operation execution information corresponding to the test case to be tested according to the parameter information; transmitting a plurality of operation execution information to a core environment layer through a test scene layer of an IP core layer and a test scene layer of a subsystem layer; determining, by the core environment layer, a plurality of target verification components from a plurality of verification components encapsulated in the core environment layer according to the plurality of operation execution information; and distributing each operation execution information to a corresponding target verification component through the core environment layer so that the multiple target verification components verify the test cases to be tested.
The storage medium may be implemented by any type of volatile or nonvolatile Memory device or combination thereof, such as static random access Memory (Static Random Access Memory, SRAM), electrically erasable Programmable Read-Only Memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), erasable Programmable Read-Only Memory (Erasable Programmable Read Only Memory, EPROM), programmable Read-Only Memory (PROM), read-Only Memory (ROM), magnetic Memory, flash Memory, magnetic disk, or optical disk.
The present application provides a computer program product which, when run on a computer, causes the computer to perform the method in any of the alternative implementations of the second embodiment.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
Further, the units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Furthermore, functional modules in various embodiments of the present application may be integrated together to form a single portion, or each module may exist alone, or two or more modules may be integrated to form a single portion.
It should be noted that the functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM) random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and variations will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (9)
1. A chip verification method, wherein the chip comprises a verification system, the verification system comprises a subsystem-level verification environment and an IP core-level verification environment, the subsystem-level verification environment comprises a subsystem-level test scene layer, the IP core-level verification environment comprises an IP core-level test scene layer, and the subsystem-level test scene layer and the IP core-level test scene layer multiplex a core environment layer, the method is applied to the chip, and the method comprises:
acquiring parameter information of a test case to be tested through a test scene layer of the IP core layer and a test scene layer of a subsystem layer;
acquiring a plurality of operation execution information corresponding to the test case to be tested according to the parameter information;
transmitting the operation execution information to the core environment layer through the test scene layer of the IP core layer and the test scene layer of the subsystem layer;
Determining, by the core environment layer, a plurality of target verification components from a plurality of verification components encapsulated in the core environment layer according to the plurality of operation execution information;
and distributing each operation execution information to a corresponding target verification component through the core environment layer so that the plurality of target verification components verify the test cases to be tested.
2. The method of claim 1, wherein the plurality of operation execution information comprises a plurality of operation execution instructions, wherein determining, by the core environment layer, a plurality of target verification components from a plurality of verification components encapsulated in the core environment layer according to the plurality of operation execution information comprises:
calling an internal storage method of the core environment layer through the core environment layer according to each operation execution instruction to translate each operation execution information into configuration information of a corresponding target verification component;
determining, by the core environment layer, a corresponding target verification component from a plurality of verification components encapsulated in the core environment layer according to configuration information of each target verification component;
distributing, by the core environment layer, the each operation execution information to a corresponding target verification component, including:
And distributing the configuration information translated by each operation execution information to the corresponding target verification component.
3. The method according to claim 1, wherein the parameter information includes an IP core protocol type identifier of the test case to be tested, the verification environment of the IP core level further includes a general method library, the test cases of different IP cores having protocol functions encapsulated in the general method library respectively correspond to a plurality of operation execution information, the plurality of operation execution information includes a plurality of common operation execution information corresponding to a common portion of the test cases of different IP cores having protocol functions, and a plurality of distinguishing operation execution information corresponding to each distinguishing portion, and the obtaining the plurality of operation execution information corresponding to the test case to be tested according to the parameter information includes:
searching the common operation execution information in the general method library, searching the corresponding differential operation execution information in the general method library according to the protocol type identifier of the IP core, and carrying out method reloading on the differential operation execution information.
4. A chip verification device, wherein the chip comprises a verification system, the verification system comprises a subsystem-level verification environment and an IP core-level verification environment, the subsystem-level verification environment comprises a subsystem-level test scene layer, the IP core-level verification environment comprises an IP core-level test scene layer, the subsystem-level test scene layer and the IP core-level test scene layer multiplex core environment layer, the device is applied to the chip, the device comprises:
The acquisition module is used for acquiring parameter information of the test case to be tested through the test scene layer of the IP core layer and the test scene layer of the subsystem layer; acquiring a plurality of operation execution information corresponding to the test case to be tested according to the parameter information;
the sending module is used for transmitting the operation execution information to the core environment layer through the test scene layer of the IP core layer and the test scene layer of the subsystem layer;
a determining module, configured to determine, by the core environment layer, a plurality of target verification components from a plurality of verification components encapsulated in the core environment layer according to the plurality of operation execution information;
the distribution module is used for distributing each operation execution information to the corresponding target verification component through the core environment layer so that the plurality of target verification components verify the test cases to be tested.
5. The apparatus according to claim 4, wherein the plurality of operation execution information includes a plurality of operation execution instructions, and the determining module is specifically configured to invoke, by the core environment layer, the core environment layer internal storage method according to each operation execution instruction to translate each operation execution information into configuration information of a corresponding target verification component; determining, by the core environment layer, a corresponding target verification component from a plurality of verification components encapsulated in the core environment layer according to configuration information of each target verification component;
The allocation module is specifically configured to allocate the configuration information translated from each operation execution information to the corresponding target verification component.
6. The chip is characterized by comprising a verification system, wherein the verification system comprises a subsystem-level verification environment and an IP core-level verification environment, the subsystem-level verification environment comprises a subsystem-level test scene layer, the IP core-level verification environment comprises an IP core-level test scene layer, the subsystem-level test scene layer and the IP core-level test scene layer multiplex a core environment layer, the subsystem-level test scene layer and the IP core-level test scene layer are in communication connection with the core environment layer, a plurality of verification components are packaged in the core environment layer, and the verification components are obtained through transmission of the subsystem-level test scene layer and the IP core-level test scene layer.
7. The chip of claim 6, wherein a plurality of common operation execution information corresponding to a plurality of test cases of different IP core types and a plurality of differential operation execution information corresponding to the test cases of each IP core type are distributed in the test scene layer of the subsystem hierarchy and the test scene layer of the IP core hierarchy.
8. The chip of claim 6, wherein the verification environment of the IP core level further includes a general method library, the general method library being in communication with the test scenario layer of the subsystem level, the test scenario layer of the IP core level, and the core environment layer, the general method library having encapsulated therein a plurality of common operation execution information corresponding to test cases of different IP core types and a plurality of distinct operation execution information corresponding to test cases of each IP core type.
9. A storage medium having stored thereon a computer program, which when executed by a processor, implements the method of any of claims 1 to 3.
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| CN112433900B (en) * | 2020-12-03 | 2023-03-14 | 海光信息技术股份有限公司 | Method, system, device and storage medium for chip verification |
| CN112597717B (en) * | 2020-12-15 | 2023-03-21 | 海光信息技术股份有限公司 | IP verification method and device and electronic equipment |
| CN114650246A (en) * | 2020-12-18 | 2022-06-21 | 中国移动通信有限公司研究院 | Detection method, device and equipment for IP core calling |
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| CN115495388B (en) * | 2022-11-17 | 2023-03-10 | 瀚博半导体(上海)有限公司 | Chip verification method, device, equipment and medium for AI reasoning chip |
| CN116719729B (en) * | 2023-06-12 | 2024-04-09 | 南京金阵微电子技术有限公司 | Universal verification platform, universal verification method, medium and electronic equipment |
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