CN113254296B - Software implementation method and system for chip SLT test - Google Patents
Software implementation method and system for chip SLT test Download PDFInfo
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- CN113254296B CN113254296B CN202110708174.3A CN202110708174A CN113254296B CN 113254296 B CN113254296 B CN 113254296B CN 202110708174 A CN202110708174 A CN 202110708174A CN 113254296 B CN113254296 B CN 113254296B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
Abstract
The invention discloses a software implementation method and a system for chip SLT test, relates to the technical field of chip test, and solves the technical problem of low transplantation rate of SLT test software. Under the cooperation of the SOC development board, the SLT test is realized under the software and hardware environment of the real operation of the chip. The realization of the test case of the SLT test software is independently developed, and software realization personnel of the test case can realize the test case independently without modifying the realization of the SLT test software, thereby ensuring the stability of the software. And moreover, the bug in the single test case can not cause the test card of the whole SLT to be dead, and the robustness of the software is ensured.
Description
Technical Field
The present disclosure relates to the field of chip testing technologies, and in particular, to a software implementation method and system for chip SLT testing.
Background
In the current chip production process, Final Test is divided into ATE (automatic Test Equipment) and SLT (System Level Test). SLT is a system level test, and a general test method is to mount a packaged chip on a test board, start up dedicated SLT test software or conventional system software, and record a test result. The main purpose of the SLT test is to improve the yield of the chip leaving the factory.
As system-on-chip (SOC) becomes more complex, the software for chip SLT testing becomes more complex. A general chip, usually dedicated small system SLT test software, can meet the requirements. The complex SOC chip has no uniform standard, generally performs software customization based on a conventional operating system, for example, on heterogeneous multi-core chip testing, repeated customization development is needed, and the defects of low test coverage rate, instable test software, poor portability and the like exist.
Disclosure of Invention
The present disclosure provides a software implementation method and system for chip SLT test, which aims to improve the test coverage rate of the chip SLT test software and implement the portability of the chip SLT test software.
The technical purpose of the present disclosure is achieved by the following technical solutions:
a software implementation method for a chip SLT test is realized by SLT test software, the SLT test software runs on an operation system of an SOC chip to be tested, the SOC chip to be tested is placed on an SOC development board, the SOC development board is connected with an SLT test machine PC, SLT test management software is installed on the SLT test machine PC, and the SLT test management software is connected with the SLT test software, and the method comprises the following steps:
the SLT test software respectively tests each test case of the SOC chip to be tested to obtain a test result, and returns the test result to the SLT test management software; wherein the test case is developed independently of the SLT test software.
A software implementation system for chip SLT test comprises:
the SLT test machine PC is provided with SLT test management software;
the SOC development board is used for placing an SOC chip to be tested;
the SOC development board is connected with the SLT test machine PC, SLT test software runs on an operating system of the SOC chip to be tested, the SLT test management software is connected with the SLT test software, the SLT test software respectively tests each test case of the SOC chip to be tested to obtain a test result, and the test result is returned to the SLT test management software; wherein the test case is developed independently of the SLT test software.
The beneficial effect of this disclosure lies in: according to the invention, the SLT test software is used as a component to run on the operating system of the SOC chip to be tested, is decoupled from the system software, and is convenient to transplant. Under the cooperation of the SOC development board, the SLT test is realized under the software and hardware environment of the real operation of the chip. The realization of the test case of the SLT test software is independently developed, and software realization personnel of the test case can realize the test case independently without modifying the SLT test software, thereby ensuring the stability of the software. And moreover, the bug in the single test case can not cause the test card of the whole SLT to be dead, and the robustness of the software is ensured.
In the chip test of the application, all test cases of the cores are run out respectively in all the cores, and the result is returned. That is to say, the test of each core test case is carried out independently, and each core can simultaneously and independently test different test cases without mutual interference, so that the test efficiency can be improved.
Drawings
FIG. 1 is a schematic diagram of a software implementation system for chip SLT testing according to the present disclosure;
FIG. 2 is a flowchart of a software implementation method for chip SLT testing according to the present disclosure;
FIG. 3 is a schematic view of a first embodiment of the present disclosure;
FIG. 4 is a schematic view of a second embodiment of the disclosure;
fig. 5 is a basic flowchart inside the SLT test software.
Detailed Description
The technical scheme of the disclosure will be described in detail with reference to the accompanying drawings.
The software implementation system for chip SLT test comprises an SLT test machine PC and an SOC development board, wherein SLT test management software is installed on the SLT test machine PC, an SOC chip to be tested is placed on the SOC development board, and the SOC development board is connected with the SLT test machine PC as shown in figure 1. The SLT testing software is operated in the actual working software and hardware environment of the SOC chip to be tested, for example, the chip A is used for an automobile cabin and a digital instrument panel, when the chip A performs the SLT test, the hardware uses an actual cabin reference development board, the software operates cabin system software, and the SLT testing software is operated on the cabin system software as a software component to perform various SLT tests.
The SLT test software runs on an operating system of the SOC chip to be tested, the SLT test management software is connected with the SLT test software, the SLT test software respectively tests each test case of the SOC chip to be tested to obtain a test result, and the test result is returned to the SLT test management software; wherein each test case is developed independently of the SLT test software. Therefore, each test case can be dynamically inserted in a plug-in mode, each test case can be independently realized, development and test control are facilitated, and robustness of test software is guaranteed.
In fig. 1, the SLT test machine PC and the SOC development board are connected via a UART (Universal Asynchronous Receiver/Transmitter) interface, and the SOC chip to be tested is powered on and operated on the SOC development board (generally using socket).
The SLT test software comprises a master module and at least one slave module, the SOC chip to be tested comprises a master core and at least one slave core, the master core is used for communicating with the SLT test machine PC (through the SLT test management software), the slave core does not communicate with the SLT test machine PC, and the master core and the slave core exchange information through inter-core communication.
In fact, the concept of a master core and a slave core does not exist in the multi-core heterogeneous chip, the SOC chip to be tested generally includes a plurality of CPUs of different or the same types, the CPUs are divided into the master core and the slave core from the perspective of the SLT test software in the present application, and for convenience of description, all descriptions about the master core and the slave core in the present application are divided from the perspective of the SLT test software.
The master module runs on the operating system of the master core, and the slave module runs on the operating system of the slave core, as shown in fig. 3, that is, the master module runs on the master core communicating with the SLT test station PC, the slave module runs on the slave core not communicating with the SLT test station PC, and the master module and the slave module also exchange information through inter-core communication. The number of the slave modules is related to the cores of the SOC chip to be tested, and generally, one slave module is operated on one core, and there are cases where a plurality of slave modules are operated on one core, for example, it is difficult for one slave module to test all test cases of the slave core.
The main module is generally used for communicating with the SLT test machine PC and testing a test case of the main core; the slave module is used for testing the test case of the slave core.
In fig. 4, the master module and the slave module each include a master management unit, a test configuration unit, a single test unit, and a message processing unit.
The main management unit is the implementation of the main control logic of the SLT test software, and comprises the implementation of module initialization and the like. Taking management of the SLT test flow through a message-driven mechanism as an example, the master management module creates an event processing thread, an external message thread, an internal message thread, and the like after entering, and converts to a message event by monitoring an external message to enter the event processing flow.
The test configuration unit is used for realizing specific configuration of a test environment of the chip, such as a test environment of voltage of the chip, running frequency of the chip and the like.
The single-item test unit is used for (1) realizing mounting and initialization of a single-item test; (2) managing single tests and starting serial or parallel tests; (3) and recording the test result. The single test unit realizes a plug-in mechanism of a single test case, taking a linux operating system as an example, dynamic loading of the test case can be realized in a dynamic link library mode, a single test frame is constructed, and the single test can ensure that the single test case is stuck and does not influence the whole SLT test through an overtime mechanism.
And the message processing unit is mainly used for realizing external message receiving and sending interface packaging, and taking the connection of the SLT test machine PC and the SOC chip to be tested through the UART interface as an example, the communication between the main module and the SLT test machine PC is realized through calling the UART receiving and sending interface of the operating system. When the connection interface between the SLT test machine PC and the SOC chip to be tested is changed into the SPI interface, only the UART interface of the operating system called by the message processing unit needs to be changed into the SPI interface, and other units are not changed, so that the software stability is ensured. Besides the message receiving and sending of the SOC chip to be tested and the external equipment, the message receiving and sending of all heterogeneous cores in the SOC chip to be tested are packaged in the message processing unit.
The software implementation method for the chip SLT test is implemented through SLT test software, the SLT test software runs on an operation system of an SOC chip to be tested, the SOC chip to be tested is placed on an SOC development board, the SOC development board is connected with an SLT test machine PC, SLT test management software is installed on the SLT test machine PC, and the SLT test management software is connected with the SLT test software, and the method comprises the following steps: testing each test case of the SOC chip to be tested through the SLT test software to obtain a test result, and returning the test result to the SLT test management software; wherein the test case is developed independently of the SLT test software.
Further, the SLT test software comprises a master module and at least one slave module, the SOC chip to be tested comprises a master core and at least one slave core, the master core is used for communicating with an SLT test machine PC (SLT test management software), the slave core does not communicate with the SLT test machine PC, and the master core and the slave core exchange information through inter-core communication.
The master module runs on an operating system of the master core, and the slave module runs on an operating system of the slave core, the method further comprising: and testing each test case of the master core through the master module, and testing each test case of the slave core through the slave module.
Fig. 2 is a specific flowchart of a software implementation method for chip SLT testing according to the present disclosure, where the main module respectively tests each test case of the main core, and the method includes:
s100: the SLT test management software initializes the master module.
S101: and the SLT test management software sends a test command to the main module, and the main module starts to test the test case of the main core.
S102: and after the main module finishes the test, returning the test result to the SLT test management software.
When the slave module tests each test case of the slave core respectively, the method includes:
s200: and after the SLT test management software initializes the master module, the master module initializes the slave module.
S201: the SLT test management software sends a test command to the master module, the master module sends the test command to the slave module, and the slave module starts to carry out single test on the test case of the slave core.
S202: and after the slave module finishes the single test, the test result is returned to the master module, and the master module returns the test result to the SLT test management software.
And the test result is returned after the single test of the slave module is finished, so that the master module can record the test result in time. In addition, after receiving the test result of the single test of the slave module, the master module may return the test result of the single test to the SLT test machine PC (through the SLT test management software), or may process all the test results and return the processed test results to the SLT test machine PC after the slave module completes all the tests.
Fig. 5 is a basic flowchart of the inside of the SLT test software, in which the SLT test machine PC sends an initialization command to the master module through the SLT test management software, the master management unit of the master module starts initialization, and the master module notifies the master management unit of the slave module to start initializing the slave module.
After initialization is finished, the SLT test machine PC sends a test command to the master module through SLT test management software, and the master module receives the test command and then sends the test command to the slave module through inter-core communication. Meanwhile, the test configuration units of the master module and the slave module start to configure the test environment, and after configuration is completed, the single test unit starts to test each single test case. The single test unit of the master module is used for testing the test case of the master core, and the single test unit of the slave module is used for testing the test case of the slave core.
After the test is finished, the slave module returns the test result to the master module, and the master module returns the test result to the SLT test machine PC through the SLT test management software.
As a specific embodiment, taking the test of a multi-core heterogeneous chip as an example, a basic flow of test operation includes: (1) starting SLT test software; (2) a test command sent by the SLT test machine PC; (3) configuring a test attribute; (4) starting a single test; (5) configuring and starting the test of other cores in the chip; (6) recording a test result; (7) and returning the test result to the SLT test machine PC.
According to the method and the device, the testing of the SOC level chip is completed through the SLT testing software, the SLT testing software does not need to be changed for different SOC chips, the testing can be completed only by changing a single testing case of each SOC chip, the SLT testing software controls each testing case to complete the testing and returns the testing result, the transportability of the SLT testing software is improved, and the testing efficiency of the SOC chip is also improved.
The foregoing is an exemplary embodiment of the present disclosure, and the scope of the present disclosure is defined by the claims and their equivalents.
Claims (6)
1. A software implementation method for chip SLT test is characterized in that the chip SLT test is implemented by SLT test software, the SLT test software runs on an operation system of an SOC chip to be tested, the SOC chip to be tested is placed on an SOC development board, the SOC development board is connected with an SLT test machine PC, SLT test management software is installed on the SLT test machine PC, and the SLT test management software is connected with the SLT test software, and the method comprises the following steps:
the SLT test software respectively tests each test case of the SOC chip to be tested to obtain a test result, and returns the test result to the SLT test management software; wherein the test cases are developed independently of the SLT test software;
the SLT test software comprises a master module and at least one slave module, the SOC chip to be tested comprises a master core and at least one slave core, the master core is used for communicating with the SLT test management software, the slave core does not communicate with the SLT test management software, and the master core and the slave core exchange information through inter-core communication; the master module running on an operating system of the master core and the slave module running on an operating system of the slave core, the method further comprising:
and respectively testing each test case of the master core through the master module, and respectively testing each test case of the slave core through the slave module.
2. The method of claim 1, wherein the master module separately testing each test case of the master core comprises:
the SLT test management software initializes the main module;
the SLT test management software sends a test command to the main module, and the main module starts to test the test case of the main core;
and after the main module finishes the test, returning the test result to the SLT test management software.
3. The method of claim 2, wherein the slave module separately testing each test case of the slave core comprises:
after the SLT test management software initializes the master module, the master module initializes the slave module;
the SLT test management software sends a test command to the master module, the master module sends the test command to the slave module, and the slave module starts to carry out single test on the test case of the slave core;
and after the slave module finishes the single test, the test result is returned to the master module, and the master module returns the test result to the SLT test management software.
4. A software implementation system for chip SLT test is characterized by comprising:
the SLT test machine PC is provided with SLT test management software;
the SOC development board is used for placing an SOC chip to be tested;
the SOC development board is connected with the SLT test machine PC, SLT test software runs on an operating system of the SOC chip to be tested, the SLT test management software is connected with the SLT test software, the SLT test software respectively tests each test case of the SOC chip to be tested to obtain a test result, and the test result is returned to the SLT test management software; wherein the test cases are developed independently of the SLT test software;
the SLT test software comprises a master module and at least one slave module, the SOC chip to be tested comprises a master core and at least one slave core, the master core is used for communicating with the SLT test management software, the slave core does not communicate with the SLT test management software, and the master core and the slave core exchange information through inter-core communication;
the master module runs on an operating system of the master core, and the slave module runs on an operating system of the slave core; the master module is used for testing each test case of the master core respectively, and the slave module is used for testing each test case of the slave core respectively.
5. The system of claim 4, wherein the master module and the slave module each comprise:
the master management unit initializes the master module and the slave module;
the test configuration unit is used for configuring the test environment after receiving the test command;
a single item test unit for: mounting and initializing a single test; managing single tests, and starting serial tests or parallel tests; and recording the test result.
6. The system of claim 5, wherein the master module and the slave module further comprise a message processing unit to implement:
packaging the SOC chip to be tested and a message transceiving interface of the SLT testing machine PC;
and packaging a message transceiving interface between the master core and the slave core in the SOC chip to be tested.
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