CN114814540B - SLT test method and system of SIP chip - Google Patents

SLT test method and system of SIP chip Download PDF

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Publication number
CN114814540B
CN114814540B CN202210420155.5A CN202210420155A CN114814540B CN 114814540 B CN114814540 B CN 114814540B CN 202210420155 A CN202210420155 A CN 202210420155A CN 114814540 B CN114814540 B CN 114814540B
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chip
tested
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slt
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CN114814540A (en
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刁志峰
刘高云
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Suzhou Wuai Yida Internet Of Things Co ltd
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Suzhou Wuai Yida Internet Of Things Co ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2896—Testing of IC packages; Test features related to IC packages
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
    • G01R35/005—Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Monitoring And Testing Of Transmission In General (AREA)

Abstract

The invention provides a SLT test method and a system of a SIP chip, the method is operated in a SLT test system, the SLT test system comprises a first test station and a second test station, the second test station comprises a radio frequency comprehensive tester, a second test machine PC, a second sorter and a second test base plate, the method comprises the steps of: the first testing station carries out firmware burning and code writing on the chip to be tested; the radio frequency calibration test software controls the radio frequency comprehensive tester to perform radio frequency calibration test on the chip to be tested to obtain a first test result, and the first test result is sent to the second classifier through the second test machine PC; the second sorter sorts the chips to be tested based on the first test result; the SLT test scheme supporting the SIP chip radio frequency calibration test, which is characterized by separate firmware burning and test, improves the test flexibility and test efficiency of the calibration comprehensive test.

Description

SLT test method and system of SIP chip
Technical Field
The invention relates to the technical field of chip testing, in particular to an SLT testing method and system of a SIP chip.
Background
SIP (System In a Package, system in package) packaging is a packaging scheme in which multiple functional wafers, including processors, memory, etc., are integrated into one package, thereby achieving a substantially complete function. Corresponding to a SOC (System On a Chip). SIP packaging is a packaging mode in which different chips are packaged side by side or stacked, while SOC is a high integration of components required by a system onto one chip.
The SIP level chip can effectively combine the devices required by each function into a whole, so that higher integration level is achieved, and a basically complete functional device is realized. Meanwhile, by means of efficient production process and testing capability, development time of products can be greatly reduced in use, and cost is saved.
In the current SIP-level chip production process, the Final Test is divided into two steps: ATE (AutomaticTest Equipment ) and SLT (System Level Test, system level test). The existing SLT test scheme is basically a one-stop solution for burning and testing, and the one-stop SLT test scheme has the defects of long test time and low test efficiency when the radio frequency calibration comprehensive test function is required to be realized.
Disclosure of Invention
In view of this, the present invention provides a method and a system for testing an SLT of a SIP chip, which are beneficial to improving the testing efficiency of the SLT testing scheme when implementing the radio frequency calibration comprehensive testing function; avoiding the problems of complicated operation process and easy error caused by multiple requirements (such as burning and testing) on one testing station.
According to one aspect of the present invention, there is provided an SLT test method of a SIP chip, which is operated in an SLT test system, the SLT test system including a first test station and a second test station, the second test station including a radio frequency integrated tester, a second test machine PC, a second sorter, and a second test base board, the second test base board being installed and connected to the second sorter, the second test base board being connected to a chip to be tested, the radio frequency integrated tester being connected to the second test machine PC and the second test base board, respectively, the second test machine PC being connected to the second test base board and the second sorter, respectively; the second test machine PC is provided with radio frequency calibration test software; the method comprises the steps of:
s110, the first testing station burns firmware of the chip to be tested and writes codes;
s120, the radio frequency calibration test software controls the radio frequency comprehensive tester to perform radio frequency calibration test on the chip to be tested to obtain a first test result, and the first test result is sent to the second classifier through the second test machine PC; and
s130, the second sorter sorts the chips to be tested based on the first test result.
Optionally, the first test station includes a first test machine PC, a first sorter, and a first test base, where the first test base is mounted on the first sorter, the first test base is connected to the chip to be tested, and the first test machine PC is connected to the first sorter and the first test base respectively; the first test machine PC is provided with programming code software; the chip to be tested is provided with identity information; step S110 includes:
the code burning software burns the firmware of the chip to be tested;
the first sorter reads the identity information of the chip to be tested and sends the identity information to the first test machine PC;
the writing code software obtains the identity information and obtains IMEI code information related to the chip to be tested based on the identity information; and
and the writing code software writes the IMEI code information into the chip to be tested.
Optionally, the first test bottom plate comprises a first linear stabilized power supply, a second linear stabilized power supply, a sampling resistor, a relay and an MCU module; the first linear stabilized power supply is respectively connected with the first test machine PC, the sampling resistor and the relay, and the second linear stabilized power supply is respectively connected with the first test machine PC and the MCU module; the MCU module is also connected with the sampling resistor and the relay; the sampling resistor, the relay and the MCU module are all connected with the chip to be tested; the first test machine PC is also provided with standby current test software; the method comprises the following steps:
the standby current testing software controls the relay to be switched from a chip working channel to a chip standby channel through the MCU module so as to realize standby current testing of the chip to be tested, obtain a second testing result and return the second testing result to the first testing machine PC;
the first test machine PC sends the second test result to the first sorting machine;
and the first sorting machine sorts the chips to be tested based on the second test result.
Optionally, the method comprises:
the code programming software obtains a firmware programming result of the chip to be tested and returns the firmware programming result to the first test machine PC;
the first test machine PC sends the firmware burning result to the first sorting machine;
and the first sorting machine sorts the chips to be tested based on the firmware burning result.
Optionally, the first testing station further includes a first chip socket, where the first chip socket is connected to the chip to be tested and the first testing bottom board respectively;
the second testing station further comprises a second chip socket, and the second chip socket is respectively connected with the chip to be tested and the second testing bottom plate.
Optionally, the SLT test system further includes a server, and the method further includes the steps of:
and the second test machine PC sends the first test result to the server for storage.
Optionally, the precision of the sampling resistor is 0.05%.
Optionally, the first testing station further includes a first chip socket, where the first chip socket is connected to the chip to be tested and the first testing bottom board respectively;
the first test bottom plate further comprises a third linear stabilized power supply, a USB connector, a converter and a SIM card seat, wherein the converter is used for converting USB connection into serial connection; the SIM card seat is used for placing an SIM card;
the sampling resistor, the relay, the MCU module, the converter and the SIM card seat are respectively connected with the first chip socket.
Optionally, the first test machine PC is further provided with SIM card test software; the method further comprises the steps of:
the SIM card test software performs SIM card reading test on the chip to be tested to obtain an SIM card test result, and sends the SIM card test result to the first sorting machine through the first test machine PC;
and the first sorting machine sorts the chips to be tested based on the SIM card test result.
According to another aspect of the present invention, there is provided an SLT test system for a SIP chip, controlled by any one of the above SLT test methods, the SLT test system including a first test station and a second test station, the first test station being configured to perform firmware burning and code writing on the chip to be tested;
the second test station comprises a radio frequency comprehensive tester, a second test machine PC, a second sorting machine and a second test base plate, wherein the second test base plate is installed and connected with the second sorting machine, the second test base plate is connected with a chip to be tested, the radio frequency comprehensive tester is respectively connected with the second test machine PC and the second test base plate, and the second test machine PC is respectively connected with the second test base plate and the second sorting machine;
the second test machine PC is provided with radio frequency calibration test software; the radio frequency calibration test software controls the radio frequency comprehensive tester to perform radio frequency calibration test on the chip to be tested to obtain a first test result, and the first test result is sent to the second classifier through the second test machine PC; and the second sorter sorts the chips to be tested based on the first test result.
Optionally, the first test station includes a first test machine PC, a first sorter, and a first test base, where the first test base is mounted on the first sorter, the first test base is connected to the chip to be tested, and the first test machine PC is connected to the first sorter and the first test base respectively; the first test machine PC is provided with programming code software; the chip to be tested is provided with identity information;
the first sorter reads the identity information of the chip to be tested and sends the identity information to the first test machine PC; the writing code software obtains the identity information, obtains IMEI code information related to the chip to be tested based on the identity information, and writes the IMEI code information into the chip to be tested.
Optionally, the first test bottom plate comprises a first linear stabilized power supply, a second linear stabilized power supply, a sampling resistor, a relay and an MCU module; the first linear stabilized power supply is respectively connected with the first test machine PC, the sampling resistor and the relay, and the second linear stabilized power supply is respectively connected with the first test machine PC and the MCU module; the MCU module is also connected with the sampling resistor and the relay; the sampling resistor, the relay and the MCU module are all connected with the chip to be tested; the first test machine PC is also provided with standby current test software;
the standby current testing software controls the relay to be switched from a chip working channel to a chip standby channel through the MCU module so as to realize standby current testing of the chip to be tested, obtain a second testing result and return the second testing result to the first testing machine PC; the first test machine PC sends the second test result to the first sorting machine; and the first sorting machine sorts the chips to be tested based on the second test result.
Compared with the prior art, the invention has the beneficial effects that:
the SLT test method and the SLT test system for the SIP chip realize firmware burning and code writing based on the first test station, and the second test station is a chip calibration comprehensive test station, namely, the firmware burning and the chip calibration test are separated, so that the test flexibility and the test efficiency of the calibration comprehensive test are improved; and when the test fails, the quick tracking and positioning of faults are convenient, and the actual production is facilitated.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is evident that the drawings in the following description are only some embodiments of the present invention and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic structural diagram of an SLT test system of a SIP chip according to an embodiment of the present invention;
FIG. 2 is a flow chart of a SLT testing method of a SIP chip according to an embodiment of the present invention;
fig. 3 is a flowchart of step S110 in an SLT testing method of a SIP chip according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a first testing chassis in an SLT testing system of a SIP chip according to an embodiment of the present invention;
FIG. 5 is a flow chart of a SLT testing method for a SIP chip according to another embodiment of the present invention;
fig. 6 is a flowchart of step S110 in an SLT testing method of a SIP chip according to another embodiment of the present invention.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the present disclosure. One skilled in the relevant art will recognize, however, that the disclosed aspects may be practiced without one or more of the specific details, or with other methods, materials, apparatus, etc. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted.
The terms "a," "an," "the," "said" and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising," "having," and "provided" are used in an open-ended fashion and mean that additional elements/components/etc., may be present in addition to the listed elements/components/etc.
As shown in fig. 1, an embodiment of the present invention discloses an SLT test system for a SIP chip. The SLT test system is used for performing SLT test on the chip 11 to be tested. The SLT test system described above includes a first test station 12 and a second test station 13. The packaged chip enters the first test station 12. The first test station 12 is used for performing firmware burning and code writing on the chip 11 to be tested. The second test station 13 performs rf calibration comprehensive test on the chip 11 to be tested. And then packaging the chip passing through the radio frequency calibration comprehensive measurement. Therefore, the application provides a set of firmware burning and testing separated SLT test scheme supporting the SIP chip radio frequency calibration test.
In this embodiment, the first test station 12 includes a first test station PC (personal computer) 14, a first sorter 15, a first test base 16, and a first chip Socket 17 (Socket). The first test bench PC14 is connected to the first sorter 15 and the first test floor 16, respectively. The first chip socket 17 is connected to the chip 11 to be tested and the first test board 16, respectively. The first chip socket 17 is mounted and connected to the first test base 16. The first test bench PC14 may be connected to the first sorter 15 through a serial line. The first test station PC14 may be connected to the first test base 16 via a USB cable.
The first test floor 16 is mounted and connected to the first separator 15. Specifically, the first sorting machine 15 is provided with a plurality of first testing stations, and each first testing station is provided with a first testing bottom plate 16, that is, the first testing bottom plates 16 are in one-to-one correspondence with the first testing stations.
The second test station 13 includes a radio frequency integrated tester 21, a second test bench PC22, a second sorter 23, a second test floor 24, and a second chip socket 25. The first test base plate 16 and the second test base plate 24 have the same internal structure. The rf integrated tester 21 is connected to the second test board PC22 and the second test board 24, respectively. The second chip socket 25 is connected to the chip 11 to be tested and the second test board 24, respectively. The second test bench PC22 is connected to the second test floor 24 and the second sorter 23, respectively. The second test bench PC22 may be connected to the second separator 23 through a serial line. The second test station PC22 may be connected to the second test base 24 via a USB cable.
The second test floor 24 is mounted and connected to the second separator 23. Specifically, the second sorting machine 23 is provided with a plurality of second testing stations, and each second testing station is provided with a second testing bottom plate 24, that is, the second testing bottom plates 24 are in one-to-one correspondence with the second testing stations.
As shown in fig. 2, an embodiment of the present invention discloses a SLT testing method of a SIP chip. The test method is operated in the SLT test system disclosed in any of the above embodiments. In this embodiment, the second test machine PC is provided with radio frequency calibration test software. The first test machine PC is provided with code burning software. The chip to be tested has identity information. The identity information can be displayed in the form of two-dimensional code information arranged on the surface of the chip to be tested.
In this embodiment, the above-mentioned SLT test method includes the steps of:
s110, the first testing station burns the firmware of the chip to be tested and writes codes.
S120, the radio frequency calibration test software controls the radio frequency comprehensive tester to perform radio frequency calibration test on the chip to be tested to obtain a first test result, and the first test result is sent to the second sorting machine through the second test machine PC. and
S130, the second sorter sorts the chips to be tested based on the first test result.
Because there is no program in the SIP chip at the beginning in the production process, in order for the SIP chip to perform operation according to the pre-designed function, the program execution file written in engineering needs to be burned into the SIP chip, that is, the firmware burning operation is performed. Since the SIP chip in this embodiment needs to have a cellular network communication function, rf calibration and comprehensive measurement are required. The calibrated parameters include, but are not limited to, transmit power and receive sensitivity, among others. The first test result is that the calibration test passes or the calibration test fails. And the calibration test is passed, namely the corresponding parameters after calibration can reach the preset range. In specific implementation, chips to be tested passing the calibration test can be sorted into trays of good products for the second sorting machine. And the second sorting machine sorts the chips to be tested which pass the calibration test into the trays of defective products.
Specifically, as shown in fig. 3, in the present embodiment, step S110 includes:
s111, the code burning software burns the firmware of the chip to be tested.
S115, the first sorter reads the identity information of the chip to be tested and sends the identity information to the first testing machine PC.
S116, the writing code software acquires the identity information, and acquires IMEI code information related to the chip to be tested based on the identity information. and
S117, the writing code software writes the IMEI code information into the chip to be tested.
In this embodiment, the identity information is two-dimensional code information on the surface of the chip to be tested. The chip to be tested is placed in a material groove to be tested of the first sorting machine, a suction nozzle on the first sorting machine absorbs the chip to be tested, photographs and identifies two-dimensional code information on the chip to be tested, and transmits the two-dimensional code information to the programming code software in the first testing machine PC through a serial port line. Meanwhile, the transmission arm on the first sorting machine transmits the chips to be tested to the chip sockets of the test base plate on the corresponding test station through the guide rail. And the code writing software reads the IMEI (International Mobile Equipment Identity, international mobile equipment identification code) code, and writes the IMEI code into the chip to be tested, so that the firmware writing and code writing operation is completed.
After the code writing is completed, the suction nozzle sucks the chip to be tested and places the chip to be tested into the tested trough of the first sorting machine through the driving arm. A good product tray and a defective product tray are arranged in the measured trough.
As shown in fig. 4, in the present embodiment, the first test board 16 includes a first linear voltage regulator 41, a second linear voltage regulator 42, a third linear voltage regulator 43, a sampling resistor 45, a relay 44, an MCU module 46, a USB connector 48, a converter 47, a SIM card holder 49, and a radio frequency connector 51. The first linear stabilized power supply 41 is connected to the first test bench PC14, the sampling resistor 45, and the relay 44, respectively. The second linear voltage regulator 42 is connected to the first test station PC14 and the MCU module 46, respectively. The MCU module 46 is also connected to the sampling resistor 45 and the relay 44. The sampling resistor 45, the relay 44 and the MCU module 46 are all connected to the chip 11 to be tested. The converter 47 is used to convert a USB connection into a serial connection. The SIM card holder 49 is used for placing a SIM card.
The sampling resistor 45, the relay 44, the MCU module 46, the converter 47, the SIM card holder 49, and the rf connector 51 are connected to the first chip socket 17, respectively. Of course, for the second test base 24, the rf connector 51 is connected to the second chip socket 25, and the rf connector 51 is also connected to the rf integrated tester 21.
It should be noted that, in this application, the first test board 16 and the second test board 24 have the same internal structure in order to reduce the design cost of the test boards. In other embodiments, the first test chassis 16 and the second test chassis 24 may be different in structure. Fig. 4 is an exemplary illustration of the structure of the first test floor 16.
Optionally, in an embodiment, the first test board PC14 is further provided with standby current test software. As shown in fig. 5, the present embodiment further includes, on the basis of the corresponding embodiment of fig. 2, between step S110 and step S120:
and S140, the standby current testing software controls the relay to be switched from a chip working channel to a chip standby channel through the MCU module so as to realize the standby current testing of the chip to be tested, obtain a second testing result and return the second testing result to the first testing machine PC. That is, when the low power consumption test is performed, the chip is in a standby state.
S150, the first test machine PC sends the second test result to the first sorter.
S160, the first sorting machine sorts the chips to be tested based on the second test result.
In this embodiment, the sampling resistor is a high-precision sampling resistor, and the standby current test with low power consumption is realized by matching the high-precision sampling resistor with the relay. According to the method and the device, the minimum 0.1uA level standby current test can be realized by adjusting the value of the high-precision sampling resistor, and the low-power consumption test is completed. Similarly, the second test result is pass or fail. The test passes, i.e. the standby current is within the preset range. In specific implementation, the chips to be tested passing the test can be sorted into trays of good products by the first sorting machine. And the first sorting machine sorts the chips to be tested which are not passed in the test into the tray of defective products. Only the chips to be tested in the good product tray, namely the chips to be tested with the second test result passing the second test result, can be subjected to the next radio frequency calibration test.
It should be noted that, when performing the subsequent radio frequency calibration test, the standby state of the chip to be tested needs to be turned off.
Illustratively, in this embodiment, the accuracy of the sampling resistor is 0.05%. But the present application is not limited thereto.
On the other hand, the test efficiency of the chip is optimized through dual control of the two test machines PC and the MCU module, and more complex test requirements can be completed.
Optionally, in an embodiment, on the basis of the corresponding embodiment of fig. 3, as shown in fig. 6, step S110 is between step S111 and step S115, and further includes:
s112, the writing code software obtains the firmware writing result of the chip to be tested, and returns the firmware writing result to the first test machine PC.
S113, the first test machine PC sends the firmware burning result to the first sorting machine.
And S114, the first sorting machine sorts the chips to be tested based on the firmware burning result.
Similarly, the firmware burning result is passed or failed. In specific implementation, the chips to be tested passing the test can be sorted into trays of good products by the first sorting machine. And the first sorting machine sorts the chips to be tested which are not passed in the test into the tray of defective products. Only the chip to be tested in the good tray, namely the chip to be tested with the firmware burning result passing the firmware burning result, can be subjected to subsequent low-power consumption test and radio frequency calibration test.
Optionally, in an embodiment, on the basis of the corresponding embodiment of fig. 5, the first test board PC is further provided with SIM card test software. The test method disclosed in this embodiment further includes the steps of:
and the SIM card testing software performs SIM card reading test on the chip to be tested to obtain an SIM card testing result, and sends the SIM card testing result to the first sorting machine through the first testing machine PC. and
And the first sorting machine sorts the chips to be tested based on the SIM card test result.
Similarly, the SIM card test result is passed or failed. And the test passing indicates that the SIM card can be read successfully. In specific implementation, the chips to be tested passing the test can be sorted into trays of good products by the first sorting machine. And the first sorting machine sorts the chips to be tested which are not passed in the test into the tray of defective products. And only the chips to be tested in the good product tray, namely the chips to be tested with the SIM card, pass the test result, can be subjected to subsequent low-power consumption test and radio frequency calibration test.
In the application, when a first test station tests, a first test machine PC is connected to a first test base plate through a USB to perform firmware burning, IMEI code writing and SIM card detection are performed after the firmware burning is completed, then standby current is sampled through an MCU module and a high-precision sampling resistor, and a test result is transmitted back to the first test machine PC through a USB to serial port, namely a converter.
Optionally, in an embodiment, the SLT test system further includes a server, and the method further includes the steps of:
and the second test machine PC sends the first test result to a server for storage. All other test results can be sent to the server for storage. This facilitates statistics of test data for this type of chip and tracking and localization of subsequent chip failures.
The embodiment of the invention also provides an SLT test system of the SIP chip. The test system is controlled by the SLT test method disclosed in any of the above embodiments.
In summary, the SLT testing method and system of the SIP chip of the present invention has at least the following advantages:
the SLT test method and the SLT test system for the SIP chip, disclosed by the embodiment, are based on the first test station to realize firmware burning and code writing, and the second test station provides a set of SLT test scheme which is separated from firmware burning and testing and supports the radio frequency calibration and low power consumption test of the SIP chip for the chip calibration comprehensive test station, so that the test flexibility and the test efficiency of the calibration comprehensive test are improved; for example, when only firmware burn-in is needed, and no test is needed, it is easier to operate. And when the test fails, the quick tracking and positioning of faults are convenient, and the actual production is facilitated.
On the other hand, the firmware burning and the calibration comprehensive measurement are separated, so that the chip firmware upgrading and reworking operations can be more conveniently carried out.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims (8)

1. The SLT test method of the SIP chip is characterized by comprising an SLT test system, wherein the SLT test system comprises a first test station and a second test station, the second test station comprises a radio frequency comprehensive tester, a second test machine PC, a second sorting machine and a second test base plate, the second test base plate is installed and connected with the second sorting machine, the second test base plate is connected with the chip to be tested, the radio frequency comprehensive tester is respectively connected with the second test machine PC and the second test base plate, and the second test machine PC is respectively connected with the second test base plate and the second sorting machine; the second test machine PC is provided with radio frequency calibration test software; the method comprises the steps of:
s110, the first testing station burns firmware of the chip to be tested and writes codes;
s120, the radio frequency calibration test software controls the radio frequency comprehensive tester to perform radio frequency calibration test on the chip to be tested to obtain a first test result, and the first test result is sent to the second classifier through the second test machine PC; and
s130, sorting the chips to be tested by the second sorting machine based on the first test result;
the first test station comprises a first test machine PC, a first sorting machine and a first test base plate, wherein the first test base plate is arranged on the first sorting machine, the first test base plate is connected with the chip to be tested, and the first test machine PC is respectively connected with the first sorting machine and the first test base plate; the first test machine PC is provided with programming code software; the chip to be tested is provided with identity information; step S110 includes:
the code burning software burns the firmware of the chip to be tested;
the first sorter reads the identity information of the chip to be tested and sends the identity information to the first test machine PC;
the writing code software obtains the identity information and obtains IMEI code information related to the chip to be tested based on the identity information; and
the writing code software writes the IMEI code information into the chip to be tested;
the first test bottom plate comprises a first linear stabilized power supply, a second linear stabilized power supply, a sampling resistor, a relay and an MCU module; the first linear stabilized power supply is respectively connected with the first test machine PC, the sampling resistor and the relay, and the second linear stabilized power supply is respectively connected with the first test machine PC and the MCU module; the MCU module is also connected with the sampling resistor and the relay; the sampling resistor, the relay and the MCU module are all connected with the chip to be tested; the first test machine PC is also provided with standby current test software; the method comprises the following steps:
the standby current testing software controls the relay to be switched from a chip working channel to a chip standby channel through the MCU module so as to realize standby current testing of the chip to be tested, obtain a second testing result and return the second testing result to the first testing machine PC;
the first test machine PC sends the second test result to the first sorting machine;
and the first sorting machine sorts the chips to be tested based on the second test result.
2. The SLT testing method of claim 1, wherein the method includes:
the code programming software obtains a firmware programming result of the chip to be tested and returns the firmware programming result to the first test machine PC;
the first test machine PC sends the firmware burning result to the first sorting machine;
and the first sorting machine sorts the chips to be tested based on the firmware burning result.
3. The SLT testing method of claim 1, wherein the first test station further includes a first chip socket connected to the chip under test and the first test floor, respectively;
the second testing station further comprises a second chip socket, and the second chip socket is respectively connected with the chip to be tested and the second testing bottom plate.
4. The SLT testing method of claim 1, wherein the SLT testing system further includes a server, the method further comprising the steps of:
and the second test machine PC sends the first test result to the server for storage.
5. The SLT test method of claim 1, wherein the sampling resistor has an accuracy of 0.05%.
6. The SLT testing method of claim 1, wherein the first test station further includes a first chip socket connected to the chip under test and the first test floor, respectively;
the first test bottom plate further comprises a third linear stabilized power supply, a USB connector, a converter and a SIM card seat, wherein the converter is used for converting USB connection into serial connection; the SIM card seat is used for placing an SIM card;
the sampling resistor, the relay, the MCU module, the converter and the SIM card seat are respectively connected with the first chip socket.
7. The SLT testing method of claim 6, wherein the first test station PC is further equipped with SIM card testing software; the method further comprises the steps of:
the SIM card test software performs SIM card reading test on the chip to be tested to obtain an SIM card test result, and sends the SIM card test result to the first sorting machine through the first test machine PC;
and the first sorting machine sorts the chips to be tested based on the SIM card test result.
8. An SLT test system of a SIP chip, characterized in that the SLT test system is controlled by the SLT test method of claim 1, and the SLT test system includes a first test station and a second test station, where the first test station is used to perform firmware burning and code writing on the chip to be tested;
the second test station comprises a radio frequency comprehensive tester, a second test machine PC, a second sorting machine and a second test base plate, wherein the second test base plate is installed and connected with the second sorting machine, the second test base plate is connected with a chip to be tested, the radio frequency comprehensive tester is respectively connected with the second test machine PC and the second test base plate, and the second test machine PC is respectively connected with the second test base plate and the second sorting machine;
the second test machine PC is provided with radio frequency calibration test software; the radio frequency calibration test software controls the radio frequency comprehensive tester to perform radio frequency calibration test on the chip to be tested to obtain a first test result, and the first test result is sent to the second classifier through the second test machine PC; and the second sorter sorts the chips to be tested based on the first test result.
CN202210420155.5A 2022-04-20 2022-04-20 SLT test method and system of SIP chip Active CN114814540B (en)

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CN201876869U (en) * 2010-12-10 2011-06-22 惠州市蓝微电子有限公司 Chip programming and testing equipment
CN103149526B (en) * 2011-12-07 2016-03-23 深圳市汇川技术股份有限公司 PCBA board test macro and method
CN103969572B (en) * 2013-02-05 2017-05-17 泰斗微电子科技有限公司 SIP (system in package) chip testing platform and method
CN104202099B (en) * 2014-09-16 2016-05-11 太仓市同维电子有限公司 A kind of for calibrating the method for 3G network interface card
CN113254296B (en) * 2021-06-25 2021-10-01 上海励驰半导体有限公司 Software implementation method and system for chip SLT test
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