CN108984403A - The verification method and device of FPGA logical code - Google Patents
The verification method and device of FPGA logical code Download PDFInfo
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- CN108984403A CN108984403A CN201810747792.7A CN201810747792A CN108984403A CN 108984403 A CN108984403 A CN 108984403A CN 201810747792 A CN201810747792 A CN 201810747792A CN 108984403 A CN108984403 A CN 108984403A
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Abstract
The present invention provides a kind of verification method of FPGA logical code and devices, belong to computer verification technique field.The verification method and device of FPGA logical code provided in an embodiment of the present invention, by the way that FPGA logical code to be measured is carried out logic interfacing with the UVM verification environment put up, then pass through eda tool, FPGA logical code to be measured is integrated in UVM verification environment, obtain UVM authentication module, and the checking case write is input in UVM authentication module, to complete the verifying to FPGA logical code to be measured, so that FPGA logical code carries out comprehensive and systematic verifying, and when board level test encounters problems, preferably problem can be reappeared by EDA mode, the locating speed and efficiency of Upgrade Problem；Meanwhile the present invention can sufficiently be multiplexed the compilation script of FPGA developing instrument generation, be directly called in verification environment, avoid developing compilation script again, save debugging and compilation time.
Description
Technical field
The present invention relates to computer verification technique fields, in particular to a kind of verification method of FPGA logical code
And device.
Background technique
With the gradually increasing of FPGA (Field Programmable Gate Array, programmable gate array) device scale
Greatly, it carries the number of resources of logic and complexity also increases on year-on-year basis, utilize FPGA developing instrument merely, built by Verilog
Testbench can not carry out comprehensive and systematic verifying to the logical code of FPGA, it is difficult to ensure that the correctness of verifying；Meanwhile it is logical
When crossing Verilog and building Testbench and verified to FPGA logical code, often due to debugging signal crawl amount and downloading program are raw
At the limitation of speed, it is difficult quickly to navigate to root because causing positioning problems speed and efficiency to be difficult to the progress of matching product exploitation
It is required that.
Summary of the invention
For above-mentioned problems of the prior art, the present invention provides a kind of verification method of FPGA logical code and
Device can carry out comprehensive and systematic verifying to FPGA logical code and guarantee that the function of logic is correct before carrying out board level test
Property.
In a first aspect, the embodiment of the invention provides a kind of verification methods of FPGA logical code, wherein the method packet
Include: by FPGA logical code to be measured with put up UVM (Universal Verification Methodology, it is general to test
Demonstrate,prove methodology) verification environment progress logic interfacing；
It, will be described to be measured by EDA (Electronics Design Automation, electric design automation) tool
FPGA logical code is integrated in the UVM verification environment, obtains UVM authentication module；
The checking case write is input in the UVM authentication module, to complete to the FPGA logical code to be measured
Verifying.
With reference to first aspect, the embodiment of the invention provides the first possible embodiments of first aspect, wherein institute
Before stating the step of FPGA logical code to be measured is carried out logic interfacing with the UVM verification environment put up, the method is also wrapped
It includes:
It carries out UVM verification environment to the FPGA logical code to be measured to build, wherein testing in the UVM verification environment
Card component includes: driving source, expected component, detection components, comparison component.
With reference to first aspect, the embodiment of the invention provides second of possible embodiments of first aspect, wherein institute
State the step of FPGA logical code to be measured is subjected to logic interfacing with the UVM verification environment put up, comprising:
The logic top layer of the FPGA logical code to be measured is packaged in the UVM verification environment, so that described
Each interface signal of FPGA logical code to be measured is correspondingly connected with each interface signal of the UVM verification environment.
With reference to first aspect, the embodiment of the invention provides the third possible embodiments of first aspect, wherein institute
State the step of FPGA logical code to be measured is integrated in the UVM verification environment, obtains UVM authentication module, comprising:
It is compiled by logic top layer of the eda tool to the FPGA logical code, generates compilation script A；
Logical code is write by the eda tool, obtains Run Script B；
The compilation script A is inputted into the eda tool, it is compiled to obtain library file C；
The library file C and the Run Script B are integrated into the UVM verification environment, UVM authentication module is obtained；
With reference to first aspect, the embodiment of the invention provides the 4th kind of possible embodiments of first aspect, wherein will
The step of checking case write is input in the UVM authentication module, completes the verifying to the FPGA logical code to be measured,
Include:
Observe the output content of checking case；
The output content is detected by the detection components；
The output content detected is sent to comparison component；
The comparison component is by the output content detected and the expected component comparative analysis.
The 4th kind of possible embodiment with reference to first aspect, the embodiment of the invention provides the 5th kind of first aspect
Possible embodiment, wherein the comparison component is by the output content detected and the expected component comparative analysis
The step of after, the method also includes:
If the output content is consistent with expected component content, judgement passes through；
If the output content and expected component content are inconsistent, restoring to normal position.
Second aspect, the embodiment of the invention also provides a kind of verifying devices of FPGA logical code, wherein includes:
Logic interfacing unit, for FPGA logical code to be measured to be carried out logic interfacing with the UVM verification environment put up；
UVM authentication module acquiring unit, for the FPGA logical code to be measured being integrated to described by eda tool
In UVM verification environment, UVM authentication module is obtained；
Authentication unit, for the checking case write to be input in the UVM authentication module, to complete to described to be measured
The verifying of FPGA logical code.
In conjunction with second aspect, the embodiment of the invention provides the first possible embodiments of second aspect, wherein institute
State device further include:
Environmental structure unit is built for carrying out UVM verification environment to the FPGA logical code to be measured.
In conjunction with second aspect, the embodiment of the invention provides second of possible embodiments of second aspect, wherein institute
It states logic interfacing unit to be also used to: the logic top layer of the FPGA logical code to be measured is carried out in the UVM verification environment
Encapsulation connects so that each interface signal of the FPGA logical code to be measured is corresponding with each interface signal of the UVM verification environment
It connects.
In conjunction with second aspect, the embodiment of the invention provides the third possible embodiments of second aspect, wherein institute
It states UVM authentication module acquiring unit to be also used to: be compiled by logic top layer of the eda tool to the FPGA logical code,
Generate compilation script A；Logical code is write by the eda tool, obtains Run Script B；The compilation script A is inputted into institute
Eda tool is stated, it is compiled to obtain library file C；The library file C and the Run Script B are integrated into the UVM verification environment
In, obtain UVM authentication module.The embodiment of the present invention bring it is following the utility model has the advantages that
The verification method and device of FPGA logical code provided in an embodiment of the present invention, by by FPGA logical code to be measured
Logic interfacing is carried out with the UVM verification environment put up, eda tool is then utilized, FPGA logical code to be measured is integrated to UVM
In verification environment, UVM authentication module is obtained, finally the checking case write is input in UVM authentication module, to complete to treat
The verifying of FPGA logical code is surveyed, comprehensive and systematic verifying can be carried out to FPGA logical code, guarantee the function of fpga logic
Correctness preferably can carry out quick problem positioning by EDA mode when board level test encounters problems.
Other features and advantages of the present invention will illustrate in the following description, also, partly become from specification
It obtains it is clear that understand through the implementation of the invention.The objectives and other advantages of the invention are in specification, claims
And specifically noted structure is achieved and obtained in attached drawing.
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, preferred embodiment is cited below particularly, and cooperate
Appended attached drawing, is described in detail below.
Detailed description of the invention
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art be briefly described, it should be apparent that, it is described below
Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor
It puts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is the flow chart of the verification method of FPGA logical code provided by the embodiment of the present invention；
Fig. 2 is the module map of the verifying device of FPGA logical code provided by the embodiment of the present invention；
Fig. 3 is the module map of the verifying device of FPGA logical code provided by the embodiment of the present invention；
Fig. 4 is the logic diagram of the exploitation of FPGA logical code provided by the embodiment of the present invention；
Fig. 5 is the structural block diagram of UVM verification platform provided by the embodiment of the present invention.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with attached drawing to the present invention
Technical solution be clearly and completely described, it is clear that described embodiments are some of the embodiments of the present invention, rather than
Whole embodiments.The component of embodiments of the present invention, which are generally described and illustrated herein in the accompanying drawings can be matched with a variety of different
It sets to arrange and design.Therefore, the detailed description of the embodiment of the present invention provided in the accompanying drawings is not intended to limit below
The range of claimed invention, but it is merely representative of selected embodiment of the invention.Based on the embodiments of the present invention, originally
Field those of ordinary skill every other embodiment obtained without making creative work, belongs to the present invention
The range of protection.
For existing problem, the embodiment of the invention provides a kind of verification method of FPGA logical code and device, with
Under describe in detail first to the verification method of FPGA logical code of the invention.
Embodiment one
A kind of verification method of FPGA logical code is present embodiments provided, is as shown in Figure 1 the process of UVM verification method
Figure, this method comprises the following steps:
Step 102, FPGA logical code to be measured is subjected to logic interfacing with the UVM verification environment put up.
Optionally, before the step of FPGA logical code to be measured being carried out logic interfacing with the UVM verification environment put up,
The method can also include: to carry out UVM verification environment to FPGA logical code to be measured to build, wherein in UVM verification environment
Checking assembly includes: driving source, expected component, detection components, comparison component.Specifically, driving source is in System verilog
Manual compiling is in exploitation environment to generate driving source；It is expected that component is generated by driving source；Detection components can be used for verifying in UVM
When, detection output content；Comparison component output content can be compared with output content in expected component, in analysis output
Whether correct hold.
In UVM verification environment, generation or corresponding detection model is motivated generally all to be encapsulated in the module of Verilog
In, wherein module is one of Verilog function body, and logic top code is write in module and passes through function
(function declaration sentence) either task (a kind of class function) come generate various excitations or receive it is various corresponding so that FPGA to be measured
Logic top layer is instantiated in UVM verification environment by module function body, and logic top layer exampleization to UVM is verified ring
In border, wherein UVM verification environment logic top layer indicates with TOP, TOP can also the checking case layer test to UVM carry out example
Change.
Test is checking case layer, and UVM can be according to emulation command row option come the corresponding checking case of exampleization.Each test
Different verification environment env and the virtual sequence of exampleization according to actual needs, forms different testcase.Separately
Outside, env is typically all that configurable, different test can be with different parameters to env.
Env is verification environment, be used for the specific checking assembly of exampleization, including Bus_agent, Tx_agent/Rx_agent,
score board.Bus_agent, Tx_agent/Rx_agent generally comprise an excitation generation module sequencer, and one
Motivate a sending module driver and interface monitoring module monitor.Sequencer, which is responsible for generating, meets the random sharp of constraint
The driver for encouraging, and being sent in the agent.Driver is responsible for the transmission for grade of trading being converted to corresponding input signal concurrent
It is sent to the input terminal of DUT.Monitor is responsible for monitoring these signal wires, statistical function coverage rate.
Specifically, when FPGA logical code to be measured being carried out logic interfacing with the UVM verification environment put up, needing will be to
The logic top layer for surveying FPGA logical code is packaged in UVM verification environment, so that each interface of FPGA logical code to be measured
Signal and each interface signal of UVM verification environment are correspondingly connected with, and completion verification environment is docked with fpga logic.
Step 104, by eda tool, FPGA logical code to be measured is integrated in UVM verification environment, obtains UVM verifying
Module.
It is illustrated in figure 4 the logic diagram of FPGA logical code exploitation, by each interface signal of FPGA logical code to be measured
After docking with the completion of each interface signal of UVM verification environment, select logic top layer as compiling in fpga logic exploitation software
Top layer is compiled by logic top layer of the eda tool to FPGA logical code, generates compilation script A.
Specifically, the exploitation environment that system verilog can be used in the embodiment of the present invention, is compiled using eda tool
Script A is generated, which can be the exploitation that the developing instruments such as Quartus II carry out script A, with authentication code volume
It translates with the presence or absence of grammer or logic error, and whether the environment configurations for verifying UVM are correct.
Further, it is illustrated in figure 5 the structure chart of UVM verification platform, logical code is write by eda tool, is obtained
Run Script B, wherein generated by UVM verification platform by manual compiling code in Run Script B, to instruct EDA authentication function
It is whether correct, meanwhile, with verifying instruction in Run Script B, script A is generated into instruction and is sent to fpga logic exploitation software,
To generate compilation script A.
Compilation script A is inputted into eda tool, it is compiled to obtain library file C；Library file C and Run Script B are integrated into
In UVM verification environment, UVM authentication module is obtained.
Specifically, the compilation script A of generation is integrated into the operation of UVM verification environment, is transported in UVM verification environment script
Before row, script A is first called, generates library file C, then script B calls library file C, with the fpga logic top in UVM verification environment
Layer and each checking assembly of UVM are compiled verifying, obtain UVM authentication module.
Step 106, by eda tool, FPGA logical code to be measured is integrated in UVM verification environment, to complete to treat
Survey the verifying of FPGA logical code.
Checking case is write in obtained UVM authentication module, verifying is compiled by eda tool, controls driving source
Fpga logic is verified in the excitation for sending out different, and observation eda tool exports content, which may include output waveform
Or output signal strength etc., it then will export the content content that detects by detection components, and will test and be sent to pair
Than component, the output content expectation component that comparing component will test is compared and analyzed, if output content and expected component
Content is consistent, then determines to pass through, and prompts to detect successfully, and manipulator can according to testing result analyze detection content, will
Problem repetition positioning；If the output content and expected component content are inconsistent, restoring to normal position, manipulator can check mistake
It misses and carries out positioning modification.
The embodiment of the invention provides a kind of verification method of FPGA logical code, by by FPGA logical code to be measured with
The UVM verification environment put up carries out logic interfacing, then by eda tool, FPGA logical code to be measured is integrated to UVM and is tested
It demonstrate,proves in environment, obtains UVM authentication module, and the checking case write is input in UVM authentication module, to complete to be measured
The verifying of FPGA logical code, the verification method can carry out comprehensive and systematic verifying to FPGA logical code, and when plate grade is surveyed
When examination encounters problems, preferably problem can be reappeared by EDA mode, the locating speed and efficiency of Upgrade Problem；Together
When, the embodiment of the present invention can sufficiently be multiplexed the compilation script of FPGA developing instrument generation, directly be adjusted in verification environment
With avoiding developing compilation script again, save debugging and compilation time.
Embodiment two
The embodiment of the invention provides a kind of verifying devices of FPGA logical code, are illustrated in figure 2 FPGA logical code
Verifying structure drawing of device, which includes:
Logic interfacing unit 21, for FPGA logical code to be measured to be carried out logic pair with the UVM verification environment put up
It connects；
UVM authentication module acquiring unit 22, for by eda tool, FPGA logical code to be measured to be integrated to UVM verifying
In environment, UVM authentication module is obtained；
Authentication unit 23, for the checking case write to be input in UVM authentication module, to complete to patrol FPGA to be measured
Collect the verifying of code.
Logic interfacing unit 21 can be also used for, and the interface signal of each interface signal and environment is attached, so as to patrol
Volume top layer carries out instantiation and puts into verification environment.
UVM authentication module acquiring unit 22 can be also used for, and carries out FPGA exploitation using developing instrument, generates script script
File A, B, and script file A, B are integrated into UVM verification environment, so that each checking assembly and script in UVM verification environment
A, B are verified.
In an alternative embodiment, as shown in figure 3, above-mentioned apparatus can also include:
Environmental structure unit 31 is built for carrying out UVM verification environment to FPGA logical code to be measured.
The verifying device of FPGA logical code provided in an embodiment of the present invention, by by FPGA logical code to be measured with build
Good UVM verification environment carries out logic interfacing, and then by eda tool, FPGA logical code to be measured is integrated to UVM verifying ring
In border, UVM authentication module is obtained, and the checking case write is input in UVM authentication module, to complete to patrol FPGA to be measured
The verifying of code is collected, which can carry out comprehensive and systematic verifying to FPGA logical code, right before carrying out board level test
UVM verification environment is built, and guarantees the function accuracy of fpga logic；And when board level test encounters problems, Neng Gougeng
Good reappears problem by EDA mode, the locating speed and efficiency of Upgrade Problem；
Further, the embodiment of the invention also provides a kind of machine readable storage medium, the machine readable storage mediums
It is stored with machine-executable instruction, when being called and being executed by processor, machine-executable instruction promotees the machine-executable instruction
Processor is set to realize above-mentioned data back up method.
Verification method and the device technical characteristic having the same of FPGA logical code provided in an embodiment of the present invention, so
Also it can solve identical technical problem, reach identical technical effect.
It should be noted that in embodiment provided by the present invention, it should be understood that disclosed system and method, it can
To realize by another way.The apparatus embodiments described above are merely exemplary, for example, the unit is drawn
Point, only a kind of logical function partition, there may be another division manner in actual implementation, in another example, multiple units or group
Part can be combined or can be integrated into another system, or some features can be ignored or not executed.It is described to be used as separation unit
The unit that part illustrates may or may not be physically separated, and component shown as a unit can be or can also
Not to be physical unit, it can it is in one place, or may be distributed over multiple network units.It can be according to reality
Needs some or all of the units may be selected to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in embodiment provided by the invention can integrate in one processing unit, it can also
To be that each unit physically exists alone, can also be integrated in one unit with two or more units.
It, can be with if the function is realized in the form of SFU software functional unit and when sold or used as an independent product
It is stored in a computer readable storage medium.Based on this understanding, technical solution of the present invention is substantially in other words
The part of the part that contributes to existing technology or the technical solution can be embodied in the form of software products, the meter
Calculation machine software product is stored in a storage medium, including some instructions are used so that a computer equipment (can be a
People's computer, server or network equipment etc.) it performs all or part of the steps of the method described in the various embodiments of the present invention.
And storage medium above-mentioned includes: that USB flash disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), arbitrary access are deposited
The various media that can store program code such as reservoir (RAM, Random Access Memory), magnetic or disk.
In addition, term " first ", " second ", " third " are used for description purposes only, it is not understood to indicate or imply phase
To importance.
Finally, it should be noted that embodiment described above, only a specific embodiment of the invention, to illustrate the present invention
Technical solution, rather than its limitations, scope of protection of the present invention is not limited thereto, although with reference to the foregoing embodiments to this hair
It is bright to be described in detail, those skilled in the art should understand that: anyone skilled in the art
In the technical scope disclosed by the present invention, it can still modify to technical solution documented by previous embodiment or can be light
It is readily conceivable that variation or equivalent replacement of some of the technical features；And these modifications, variation or replacement, do not make
The essence of corresponding technical solution is detached from the spirit and scope of technical solution of the embodiment of the present invention, should all cover in protection of the invention
Within the scope of.Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. a kind of verification method of FPGA logical code characterized by comprising
FPGA logical code to be measured is subjected to logic interfacing with the UVM verification environment put up；
By eda tool, the FPGA logical code to be measured is integrated in the UVM verification environment, obtains UVM verifying mould
Block；
The checking case write is input in the UVM authentication module, to complete to test the FPGA logical code to be measured
Card.
2. the method according to claim 1, wherein described by FPGA logical code to be measured and the UVM put up
Before verification environment carries out the step of logic interfacing, the method also includes:
It carries out UVM verification environment to the FPGA logical code to be measured to build, wherein the validation group in the UVM verification environment
Part includes: driving source, expected component, detection components, comparison component.
3. the method according to claim 1, wherein described by FPGA logical code to be measured and the UVM put up
Verification environment carries out the step of logic interfacing, comprising:
The logic top layer of the FPGA logical code to be measured is packaged in the UVM verification environment, so that described to be measured
Each interface signal of FPGA logical code is correspondingly connected with each interface signal of the UVM verification environment.
4. the method according to claim 1, wherein it is described the FPGA logical code to be measured is integrated to it is described
In UVM verification environment, the step of obtaining UVM authentication module, comprising:
It is compiled by logic top layer of the eda tool to the FPGA logical code, generates compilation script A；
Logical code is write by the eda tool, obtains Run Script B；
The compilation script A is inputted into the eda tool, it is compiled to obtain library file C；
The library file C and the Run Script B are integrated into the UVM verification environment, UVM authentication module is obtained.
5. the method according to claim 1, wherein the checking case write, which is input to the UVM, verifies mould
In block, the step of completion to the verifying of the FPGA logical code to be measured, comprising:
Observe the output content of checking case；
The output content is detected by the detection components；
The output content detected is sent to comparison component；
The comparison component is by the output content detected and the expected component comparative analysis.
6. according to the method described in claim 5, it is characterized in that, the comparison component by the output content detected with
After the step of expected component comparative analysis, the method also includes:
If the output content is consistent with expected component content, judgement passes through；
If the output content and expected component content are inconsistent, restoring to normal position.
7. a kind of verifying device of FPGA logical code characterized by comprising
Logic interfacing unit, for FPGA logical code to be measured to be carried out logic interfacing with the UVM verification environment put up；
UVM authentication module acquiring unit, for the FPGA logical code to be measured being integrated to the UVM and is tested by eda tool
It demonstrate,proves in environment, obtains UVM authentication module；
Authentication unit, for the checking case write to be input in the UVM authentication module, to complete to the FPGA to be measured
The verifying of logical code.
8. device according to claim 7, which is characterized in that described device further include: environmental structure unit, for institute
FPGA logical code progress UVM verification environment to be measured is stated to build.
9. device according to claim 7, which is characterized in that the logic interfacing unit is also used to: will be described to be measured
The logic top layer of FPGA logical code is packaged in the UVM verification environment, so that the FPGA logical code to be measured
Each interface signal and each interface signal of the UVM verification environment are correspondingly connected with.
10. device according to claim 7, which is characterized in that the UVM authentication module acquiring unit is also used to: being passed through
Eda tool is compiled the logic top layer of the FPGA logical code, generates compilation script A；It is write by the eda tool
Logical code obtains Run Script B；The compilation script A is inputted into the eda tool, it is compiled to obtain library file C；By institute
It states library file C and the Run Script B is integrated into the UVM verification environment, obtain UVM authentication module.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109669872A (en) * | 2018-12-24 | 2019-04-23 | 郑州云海信息技术有限公司 | A kind of verification method and device |
| CN109740250A (en) * | 2018-12-29 | 2019-05-10 | 湖北航天技术研究院总体设计所 | The acquisition methods and system of FPGA software verification result simulation waveform based on UVM |
| CN110737571A (en) * | 2019-08-31 | 2020-01-31 | 苏州浪潮智能科技有限公司 | HDP + FPGA-based compression and decompression reference performance verification method, system and equipment |
| CN112416760A (en) * | 2020-11-11 | 2021-02-26 | 北京京航计算通讯研究所 | Module packaging method and device for universal test platform Testbench |
| CN112560378A (en) * | 2020-12-23 | 2021-03-26 | 苏州易行电子科技有限公司 | Be applied to automation platform of integrating complete chip development flow |
| CN113392620A (en) * | 2021-06-25 | 2021-09-14 | 上海阵量智能科技有限公司 | Chip prototype verification method and device, computer equipment and storage medium |
| CN116090376A (en) * | 2023-04-10 | 2023-05-09 | 芯来智融半导体科技(上海)有限公司 | Chip integrated verification component development method and device and computer equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104065536A (en) * | 2014-07-02 | 2014-09-24 | 浪潮集团有限公司 | Ethernet switch FPGA verification method based on UVM verification method |
| CN104268310A (en) * | 2014-09-05 | 2015-01-07 | 浪潮集团有限公司 | Method for calling UVM verification environment through special graphical interface |
| CN104865560A (en) * | 2015-04-21 | 2015-08-26 | 中国电子科技集团公司第三十八研究所 | UVM-based phased array radar digital beam former module verification method and verification platform thereof |
-
2018
- 2018-07-09 CN CN201810747792.7A patent/CN108984403A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104065536A (en) * | 2014-07-02 | 2014-09-24 | 浪潮集团有限公司 | Ethernet switch FPGA verification method based on UVM verification method |
| CN104268310A (en) * | 2014-09-05 | 2015-01-07 | 浪潮集团有限公司 | Method for calling UVM verification environment through special graphical interface |
| CN104865560A (en) * | 2015-04-21 | 2015-08-26 | 中国电子科技集团公司第三十八研究所 | UVM-based phased array radar digital beam former module verification method and verification platform thereof |
Non-Patent Citations (4)
| Title |
|---|
| BETTY: "基于UVM的verilog验证", 《HTTPS://WWW.CNBLOGS.COM/BETTTY/P/5285785.HTML》 * |
| JAKUB PODIVINSKY 等: "Verification of Robot Controller for Evaluating Impacts of Faults in Electro-mechanical Systems", 《2016 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN》 * |
| 习建博 等: "基于UVM方法的FPGA验证技术", 《电子科学技术》 * |
| 赵唯唯: "面向无线传感网络的UVM验证方法应用研究", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
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| CN112560378A (en) * | 2020-12-23 | 2021-03-26 | 苏州易行电子科技有限公司 | Be applied to automation platform of integrating complete chip development flow |
| CN112560378B (en) * | 2020-12-23 | 2023-03-24 | 苏州易行电子科技有限公司 | Be applied to automation platform of integrating complete chip development flow |
| CN113392620A (en) * | 2021-06-25 | 2021-09-14 | 上海阵量智能科技有限公司 | Chip prototype verification method and device, computer equipment and storage medium |
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| CN116090376A (en) * | 2023-04-10 | 2023-05-09 | 芯来智融半导体科技(上海)有限公司 | Chip integrated verification component development method and device and computer equipment |
| CN116090376B (en) * | 2023-04-10 | 2023-08-15 | 芯来智融半导体科技(上海)有限公司 | Chip integrated verification component development method and device and computer equipment |
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