CN104268310A - Method for calling UVM verification environment through special graphical interface - Google Patents
Method for calling UVM verification environment through special graphical interface Download PDFInfo
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Abstract
The invention discloses a method for calling a UVM verification environment through a special graphical interface and relates to the FPGA logic verification technology. According to the method, a graphical user interface is provided for using the complex UVM verification environment by means of graphical packaging of a standard UVM verification platform; firstly, a user graphical interface verifick is run in a verification simulation item directory; after a window of the user graphical interface appears, a running mode, a verification platform and test cases are selected; lastly, running is started through clicking, and a running result is waited for and checked. By means of the method, developers do not need to input complex commands, use of professional verification tools and verification methods by non-professional verification staff is facilitated greatly, the use threshold of the UVM verification environment is lowered, and the efficiency and quality of logic code development are improved.
Description
Technical field
The present invention relates to fpga logic verification technique, specifically use dedicated graphics interface to call the method for UVM verification environment.
Background technology
Traditional FPGA design cycle, after selected FPGA device, is first carried out the design input of hardware description language, is debugged after simple simulation with regard to comprehensively going out net table and downloading to Target Board.Simulating, verifying generally as the means of main guarantee designing quality, also can not can not use any verification methodology.But with the contemporary lifting of FPGA capacity and the raising of design complexities, only debugging can waste the plenty of time on phase plate rearward, and be difficult to positioning logic mistake, so the importance of simulating, verifying in FPGA design cycle improves gradually, and be inclined to use the methodology used in chip checking.
UVM is a kind of verification methodology of the up-to-date research and development of chip checking industry, Utility Engineers it can create Verification Components and the verification platform of solid, reusable, tool interoperability.UVM provides a set of built-in function based on SystemVerilog language development, and slip-stick artist can save the trouble of exploitation verification environment of oneself starting from scratch by calling storehouse.
But general chip design checking develops with FPGA the hardware environment used very large difference.Chip design checking is general uses environment based on linux server, slip-stick artist logs on the enterprising line operate of server, and utilize various shell, Makefile and script to make design verification environmental energy automatically run, chip slip-stick artist general custom utility command row is finished the work.But FPGA developer generally uses Windows PC, by graphical interfaces function software, order line not too accustomed to using automatically performs task.For there is no SystemVerilog language basis and UVM use experience completely, seldom using the FPGA developer of Linux order line, directly using UVM verification environment to be a challenging task by order line under linux.Even if for order line accustomed to using, have the slip-stick artist of some UVM use experiences, also need manually to knock in a lot of command parameter when starting verification environment, this operation itself is bothersome easily to make mistakes.Therefore, for verification environment develops a graphic operation interface, facilitate developer to use, being one greatly can improve development efficiency, advances the thing of new technology widespread use.
Commercial eda software company such as Mentor, Cadence etc. also provide some verification management instruments, and the Vmanager of such as Cadence is exactly the very powerful management tool of a function, provides very detailed graphical interfaces to be user-friendly to.But these management tools all will collect extremely expensive cost of use, and they can bind the emulator of oneself company, and such as Vmanager can only call IUS emulator, can not use the emulator of other companies.Meanwhile, these management tools powerful also brings a drawback and uses more complicated exactly, needs to carry out special training, just can make its use flow process clear.
Comprehensive above various factors, stand-alone development is a kind of to be simple and easy to, can the verification environment graphical interfaces of compatible multiple emulation tool, is necessary.
Summary of the invention
The present invention is directed to the weak point that prior art exists, provide a kind of method using dedicated graphics interface to call to be applied to the UVM verification environment of fpga logic design verification.
The invention provides the method using dedicated graphics interface to call UVM verification environment, its technical scheme solving the problems of the technologies described above employing is as follows: the method for UVM verification environment is called at described use dedicated graphics interface, by the graphical packaging to standard UV M verification platform, provide an easy clear graphical user interface and use complicated UVM verification environment, reduce the use threshold of UVM verification environment, improve efficiency and the quality of logical code exploitation.
The method of UVM verification environment is called at this use dedicated graphics interface, and its concrete steps comprise: start graphical interfaces, select operational mode, select verification platform, select test case, click brings into operation, wait for operation result and check operation result; Wherein, described selection operational mode comprises, and can run these four kinds of patterns select operational mode from precompile design, debugging mode operation, Text Mode operation and batch mode; Described selection verification platform comprises, test platform available in meeting automatic search project, and the behavior needs of design code under different scene uses different test platforms to verify; Described selection test case comprises, and the test case in project can be demonstrated in lists, and the behavior needs of design code under different test and excitation uses different test cases to verify.
Use dedicated graphics interface of the present invention is adopted to call the method for UVM verification environment, first run user graphical interfaces verifick in checking emulation project directory, after occurring that user uses the forms of graphical interfaces, then operational mode is selected, and select verification platform and select test case, finally click and bring into operation, and wait for operation result, check operation result, until end of run.
The method that UVM verification environment is called at use dedicated graphics interface of the present invention is compared with the prior art the beneficial effect had: the method achieve and use dedicated graphics interface to call the UVM verification environment being applied to fpga logic design verification, the graphical interfaces of this UVM verification environment is the Graphic Design of standard UV M verification platform, may be used for various logic design item, for logical design personnel provide an easy clear interface to use complicated UVM verification environment; The verification environment interface of this graphical interfaces, do not need developer to input complicated order, the parameter that clear and definite display can be selected, greatly facilitates verification tool and the verification method of amateur checking librarian use specialty;
The method of UVM verification environment is called by this use dedicated graphics interface, verification platform and the test case of available use in project can be provided from trend user, support the functions such as precompile, debugging mode operation, Text Mode operation and batch mode operation, reduce the use threshold of UVM verification environment, improve efficiency and the quality of logical code exploitation, advance the widespread use in the design process of new verification technique.
Accompanying drawing explanation
Accompanying drawing 1 is that the user of verification environment in the present embodiment uses process flow diagram;
Accompanying drawing 2 is the relation block diagram that the user of verification environment uses graphical interfaces and UVM verification environment kernel;
In accompanying drawing 2: test _ plan represents test plan; Testcase_list represents test case list; Coverage_list represents covering tabulation; Batch run represents batch processing; Perl script represents perl script; Batch mode represents batch mode; Txt mode represents Text Mode; Debug mode represents debugging mode; Error report represents error reporting; Log file for check represents journal file inspection; Wlf file for debug represents debugging WLF file; DUT, TB, TC_LIB represent the core of UVM verification environment.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly understand, hereinafter will by reference to the accompanying drawings the method that UVM verification environment is called at use dedicated graphics interface of the present invention be described in detail.
Graphic user interface, also known as graphical user interface, refers to the computer operation user interface adopting graphics mode display, and compared with the Command Line Interface used with early stage computing machine, graphical interfaces is visually easier to accept for user.The method of UVM verification environment is called at use dedicated graphics interface of the present invention, propose the method using dedicated graphics interface to call the UVM verification environment being applied to fpga logic design verification, by the graphical packaging to standard UV M verification platform, for logical design personnel provide an easy clear graphical user interface to use complicated UVM verification environment, can operational verification platform and checking case in option easily by dedicated graphics interface manner, support precompile, debugging mode runs, Text Mode runs, the functions such as batch mode operation, reduce the use threshold of UVM verification environment, improve efficiency and the quality of logical code exploitation.
The method of UVM verification environment is called at use dedicated graphics interface of the present invention, and its concrete steps comprise: start graphical interfaces, select operational mode, select verification platform, select test case, click brings into operation, wait for operation result and check operation result; First run user graphical interfaces verifick in checking emulation project directory, after occurring that user uses the forms of graphical interfaces, then operational mode is selected, and select verification platform and select test case, finally click and bring into operation, and wait for operation result, check operation result, until end of run.
Embodiment:
Below by an embodiment, use dedicated graphics interface of the present invention is called to advantage and the design content of the method for UVM verification environment, be described in detail.
Accompanying drawing 1 is that the user of verification environment in the present embodiment uses process flow diagram, as shown in Figure 1, the user of verification environment uses step as follows: first run user graphical interfaces verifick in checking emulation project directory, after occurring that user uses the forms of graphical interfaces, then select operational mode, and select verification platform and select test case, finally click and bring into operation, and wait for operation result, check operation result, until end of run.
Use dedicated graphics interface to call in the method for UVM verification environment described in the present embodiment, described selection operational mode comprises, and can run these four kinds of patterns select operational mode from precompile design, debugging mode operation, Text Mode operation and batch mode; Described selection verification platform comprises, test platform available in meeting automatic search project, and the behavior needs of design code under different scene uses different test platforms to verify; Described selection test case comprises, and the test case in project can be demonstrated in lists, and the behavior needs of design code under different test and excitation uses different test cases to verify.
Dedicated graphics interface is used to call in the method for UVM verification environment described in the present embodiment, when carrying out selection operational mode, if select precompile design, then can compile all relevant logical codes, verification platform and checking case, and check grammar mistake wherein, but not Dynamic simulation;
If select debugging mode to run, then can compile all relevant logical codes, verification platform and checking case, and call emulator Dynamic simulation and wave recording file, generate simulation report, open the waveform that user specifies, for developer's debug logic code;
If select Text Mode to run, then can compile all relevant logical codes, verification platform and checking case, and call emulator Dynamic simulation and generate simulation report, but not wave recording file, and do not open the graphical interfaces of emulator, be conducive to developer like this and understand logical code sooner whether function is correct;
If select batch mode to run, then can compile all relevant logical codes, verification platform and checking case, and call all test cases of specifying of emulator operation, and provide the simulation report of each test case and coverage rate report, to facilitate the situation understanding the whether logically true and checking coverage rate of code; Batch mode is run generally consuming time longer, and operational process median surface can complete use-case and wait for the quantity of use-case by Dynamic Announce, and namely wherein how many use-cases have run, and how many use-cases still run in wait.
For above several operational mode in the present embodiment, at the general code tester initial stage, the more debugging mode that uses carrys out Amending design, to the code debugging later stage, when function is basicly stable, more can use Text Mode and batch mode.The verification environment interface of this graphical interfaces, do not need developer to input complicated order, the parameter that clear and definite display can be selected, greatly facilitates verification tool and the verification method of amateur checking librarian use specialty.
Accompanying drawing 2 is the relation block diagram that the user of verification environment uses graphical interfaces and UVM verification environment kernel, and as shown in Figure 2, graphical interface program verifick is made up of Python program, have invoked the storehouse of Tkinter to build graphical interfaces; If have selected debugging mode to run (Debug run) or Text Mode operation (txt run), then the parameter that user selects can be passed to the Makefile file in emulation catalogue, by make command calls emulator, figure 2 shows the situation calling questasim emulator, for other emulators, situation is also similar; If have selected batch mode to run (batch run), then first can call a perl script (perl script), according to test case list, generate one group of emulation command, and perform each test case successively, obtain simulation report and coverage rate report, and result reactionary slogan, anti-communist poster is returned test plan (test_plan).In accompanying drawing 2, DUT, TB, TC_LIB are the cores of whole verification environment, TB, TC_LIB be wherein all based on UVM verification environment base class build form, ensure that height reusability and the dirigibility of whole verification environment.
Makefile described in accompanying drawing 2 defines a series of rule to specify, source file countless in an engineering by type, function, module be when being placed on respectively in several catalogues, which file needs first to compile, compiling after which file needs, which file needs to recompilate, and even can perform shell script in makefile; Makefile is responsible for " robotization compiling ", and only need a make order, the complete automatic compiling of whole engineering, greatly improves the efficiency of software development.Described QuestaSim is measured monokaryon validation engine, is integrated with a HDL simulator, a constraint solver, judgement engine, a functional coverage, and the user interface that general; Possess powerful analog simulation function, in design, compiling, emulation and test, debug in performance history, have a whole set of available instrument, and it is relatively more flexible to operate, and can carry out work by the mode of menu, shortcut and order line.
Above-mentioned embodiment is only concrete case of the present invention; scope of patent protection of the present invention includes but not limited to above-mentioned embodiment; any claims according to the invention and any person of an ordinary skill in the technical field to its suitable change done or replacement, all should fall into scope of patent protection of the present invention.
Claims (6)
1. use dedicated graphics interface to call the method for UVM verification environment, it is characterized in that, by the graphical packaging to standard UV M verification platform, provide the UVM verification environment that a graphical user interface uses complexity, its concrete steps comprise: start graphical interfaces, select operational mode, select verification platform, select test case, click brings into operation, wait for operation result and check operation result; Wherein, described selection operational mode comprises, and can run these four kinds of patterns select operational mode from precompile design, debugging mode operation, Text Mode operation and batch mode; Described selection verification platform comprises, test platform available in meeting automatic search project, and the behavior needs of design code under different scene uses different test platforms to verify; Described selection test case comprises, and the test case in project is shown in lists, and the behavior needs of design code under different test and excitation uses different test cases to verify.
2. the method for UVM verification environment is called at use dedicated graphics interface according to claim 1, it is characterized in that, first run user graphical interfaces verifick in checking emulation project directory, after occurring that user uses the forms of graphical interfaces, then select operational mode, and select verification platform and select test case, finally click and bring into operation, and wait for operation result, check operation result, until end of run.
3. the method for UVM verification environment is called at use dedicated graphics interface according to claim 2, it is characterized in that, when carrying out selection operational mode, if select precompile design, then can compile all relevant logical codes, verification platform and checking case, and check grammar mistake wherein, but not Dynamic simulation.
4. the method for UVM verification environment is called at use dedicated graphics interface according to claim 2, it is characterized in that, if select debugging mode to run, then can compile all relevant logical codes, verification platform and checking case, and call emulator Dynamic simulation and wave recording file, generate simulation report, open the waveform that user specifies.
5. the method for UVM verification environment is called at use dedicated graphics interface according to claim 2, it is characterized in that, if select Text Mode to run, then can compile all relevant logical codes, verification platform and checking case, and call emulator Dynamic simulation and generate simulation report.
6. the method for UVM verification environment is called at use dedicated graphics interface according to claim 2, it is characterized in that, if select batch mode to run, then can compile all relevant logical codes, verification platform and checking case, and call all test cases of specifying of emulator operation, and provide simulation report and the coverage rate report of each test case, operational process median surface can complete use-case and waits for the quantity of use-case by Dynamic Announce.
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Cited By (13)
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| CN105045698A (en) * | 2015-07-27 | 2015-11-11 | 浪潮集团有限公司 | Method for analyzing chip verification progress by using MATPLOTLIB of PYTHON |
| CN105138386A (en) * | 2015-08-26 | 2015-12-09 | 浪潮集团有限公司 | Logic design verification continuous integration platform based on Jenkins and vManager |
| CN106933730A (en) * | 2015-12-29 | 2017-07-07 | 北京国睿中数科技股份有限公司 | Method of testing, device and test frame system based on test frame system |
| CN107608659A (en) * | 2017-08-25 | 2018-01-19 | 北京智行鸿远汽车有限公司 | Design method applied to the LabVIEW of response multitask software architecture |
| CN108038294A (en) * | 2017-12-06 | 2018-05-15 | 北京松果电子有限公司 | UVM environmental structure method and systems |
| CN108984403A (en) * | 2018-07-09 | 2018-12-11 | 天津芯海创科技有限公司 | The verification method and device of FPGA logical code |
| CN109492269A (en) * | 2018-10-22 | 2019-03-19 | 北方电子研究院安徽有限公司 | A kind of digital fuse timing circuit verification platform based on UVM |
| CN110096441A (en) * | 2019-04-26 | 2019-08-06 | 北京航空航天大学 | One kind is based on FPGA Software Simulation Test environment method for building up under UVM method |
| CN110765028A (en) * | 2019-12-27 | 2020-02-07 | 中科寒武纪科技股份有限公司 | Visual construction method and device of verification environment and storage medium |
| CN111290954A (en) * | 2020-02-10 | 2020-06-16 | 中国电子科技集团公司第十四研究所 | FPGA component visual test framework and method based on UVM |
| CN112559264A (en) * | 2020-12-08 | 2021-03-26 | 北京京航计算通讯研究所 | Simulation test method for realizing FPGA (field programmable Gate array) universal serial port by verification platform based on UVM (Universal verification Module) |
| CN112965736A (en) * | 2021-03-04 | 2021-06-15 | 北京锐安科技有限公司 | Code processing method and device, electronic equipment and medium |
| CN115455877A (en) * | 2022-11-09 | 2022-12-09 | 芯耀辉科技有限公司 | Verification platform generation device, method, medium and electronic equipment |
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Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105045698A (en) * | 2015-07-27 | 2015-11-11 | 浪潮集团有限公司 | Method for analyzing chip verification progress by using MATPLOTLIB of PYTHON |
| CN105138386A (en) * | 2015-08-26 | 2015-12-09 | 浪潮集团有限公司 | Logic design verification continuous integration platform based on Jenkins and vManager |
| CN106933730A (en) * | 2015-12-29 | 2017-07-07 | 北京国睿中数科技股份有限公司 | Method of testing, device and test frame system based on test frame system |
| CN107608659A (en) * | 2017-08-25 | 2018-01-19 | 北京智行鸿远汽车有限公司 | Design method applied to the LabVIEW of response multitask software architecture |
| CN108038294A (en) * | 2017-12-06 | 2018-05-15 | 北京松果电子有限公司 | UVM environmental structure method and systems |
| CN108984403A (en) * | 2018-07-09 | 2018-12-11 | 天津芯海创科技有限公司 | The verification method and device of FPGA logical code |
| CN109492269A (en) * | 2018-10-22 | 2019-03-19 | 北方电子研究院安徽有限公司 | A kind of digital fuse timing circuit verification platform based on UVM |
| CN109492269B (en) * | 2018-10-22 | 2023-06-27 | 北方电子研究院安徽有限公司 | Digital fuze timing circuit verification platform based on UVM |
| CN110096441B (en) * | 2019-04-26 | 2021-02-19 | 北京航空航天大学 | FPGA software simulation test environment establishment method based on UVM method |
| CN110096441A (en) * | 2019-04-26 | 2019-08-06 | 北京航空航天大学 | One kind is based on FPGA Software Simulation Test environment method for building up under UVM method |
| CN110765028A (en) * | 2019-12-27 | 2020-02-07 | 中科寒武纪科技股份有限公司 | Visual construction method and device of verification environment and storage medium |
| CN111290954B (en) * | 2020-02-10 | 2023-04-14 | 中国电子科技集团公司第十四研究所 | FPGA component visual test framework and method based on UVM |
| CN111290954A (en) * | 2020-02-10 | 2020-06-16 | 中国电子科技集团公司第十四研究所 | FPGA component visual test framework and method based on UVM |
| CN112559264A (en) * | 2020-12-08 | 2021-03-26 | 北京京航计算通讯研究所 | Simulation test method for realizing FPGA (field programmable Gate array) universal serial port by verification platform based on UVM (Universal verification Module) |
| CN112559264B (en) * | 2020-12-08 | 2021-08-06 | 北京京航计算通讯研究所 | Simulation test method for realizing FPGA (field programmable Gate array) universal serial port by verification platform based on UVM (Universal verification Module) |
| CN112965736A (en) * | 2021-03-04 | 2021-06-15 | 北京锐安科技有限公司 | Code processing method and device, electronic equipment and medium |
| CN115455877A (en) * | 2022-11-09 | 2022-12-09 | 芯耀辉科技有限公司 | Verification platform generation device, method, medium and electronic equipment |
| CN115455877B (en) * | 2022-11-09 | 2023-03-21 | 芯耀辉科技有限公司 | Verification platform generation device, method, medium and electronic equipment |
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