CN106649101A - ICE automated test system and test method - Google Patents
ICE automated test system and test method Download PDFInfo
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- CN106649101A CN106649101A CN201611020255.XA CN201611020255A CN106649101A CN 106649101 A CN106649101 A CN 106649101A CN 201611020255 A CN201611020255 A CN 201611020255A CN 106649101 A CN106649101 A CN 106649101A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3648—Software debugging using additional hardware
- G06F11/3652—Software debugging using additional hardware in-circuit-emulation [ICE] arrangements
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- G—PHYSICS
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Abstract
The invention discloses an ICE (In-Circuit Emulator) automated test system and an ICE automated test method. The test system comprises two major parts including an upper computer and a lower computer, wherein the upper computer uses a script as a central control board of the test system; the lower computer comprises a DUT (Device Under Test) and a TB (Test Board); and the upper computer communicates with the lower computer through an API (Application Programming Interface). According to the automated test system and method, digital function testing of all ICE supported models can be realized, labor input of testing is reduced, manual operation is reduced to a great extent, and a test process is greatly shortened; and a test log is automatically output, so that test personnel can quickly discover problems and repair chip design.
Description
Technical field
The invention belongs to automatization testing technique field, more particularly to a kind of in-circuit emulation based on field programmable gate array
Device automatization test system and method.
Background technology
In-circuit emulator (ICE) is also referred to as hardware emulator, belong to used in MCU development processes with chip Equivalent Physical
Device.The characteristic of its product seeks to functional characteristic, electrical characteristic and physical characteristic of strict approaching to reality chip etc..User
Using the equipment and its supporting IDE development environment, embedded programming, cross compile, real-time simulation tune can be rapidly performed by
Examination etc..The kind equipment typically is provided with the ICE of reconfigurable characteristic, i.e., can generally simulate the characteristic of many money MCU chips.
However, as the compatible chip types of ICE are more and more, it is incomparably huge that the test of product becomes a workload
Thing.Because each MCU chip function of itself is many, and testing procedure is comprising RTL checkings, the mould before flow
Sample test, CP tests after number hybrid verification, FPGA checkings and flow etc..ICE as another independent product,
Its test job amount naturally also increases by a year-on-year basis.So how by way of automatic test, realize test Case recurrence and
Traversal, reduces the input of test manpower, referred to as very important problem in ICE product development processes.
As patent application 201510617717.5 discloses a kind of MCU emulation modes for ICE, the method passes through CS-
Realizing, CPU the and CS-SIM primary modules of wherein ICE are integrated in FPGA, CS-SIM for SIM primary modules and CS-SIM slave modules
Slave module is integrated in objective chip；The SFR buses that CS-SIM primary modules pass through monitoring CPU, in the related deposit of CPU read-write simulations
While device, SFR information is written in the middle of objective chip by CS-SIM buses；Pass through CS-SIM slave modules in objective chip
Receive SFR information and complete SFR configurations, most at last simulation output is mapped on I/O port, realizes chip internal digital analog interface to ICE numbers
The equivalence replacement of mould interface.However, CS-SIM primary modules and CS-SIM slave modules do not record the model of ICE and various applications
Program, for different ICE product tests, it is necessary to re-start all of testing procedure, inevitably bring resource and
The waste of cost, affects the efficiency of test.
The content of the invention
Based on this, thus the primary mesh of the present invention be to provide a kind of ICE automatization test systems and method of testing, should be from
Dynamicization test system and method for testing, can realize that all ICE support the digital function test of model, while can also extend support core
The FPGA automatic Verifications of piece and the digital automation test of print.
Another mesh ground of the present invention is to provide a kind of ICE automatization test systems and method of testing, and the automation is surveyed
Test system and method for testing can reduce the input of test manpower, reduce manually operated, substantially reduce testing process, improve
Testing efficiency.
For achieving the above object, the technical scheme is that：
A kind of ICE automatization test systems, the test system includes host computer and slave computer two large divisions, wherein：
The host computer uses script as the central control board of test system, and houses ICE models storehouse, program use-case
Storehouse (FC, Firmware Case), TB use-cases storehouse and test case library (TC, Test Case)；
The slave computer is included：DUT (Device Under Test) ICE itself and TB (Test Board) test board,
DUT is the hardware carrier of program use-case, and TB serves as the signal generator of the DUT input stimulus X of system and DUT output results Y
The test suites such as signal measurement instrument；
The host computer and slave computer are communicated by api interface.
Host computer mainly includes control script, TC, FC and API (Application Programming
Interface), control script carries out hardware reconstruction by calling RBF files to DUT and TB, calls MSCL (Microsoft
Compiler) compiler test use-case TC generates EXE executable files, calls CSCL (ChipSea Compiler) cross compile journey
Sequence use-case FC generates HEX files, and TC is loaded by API and realize in FC to DUT software reconfiguration, and performs the survey of certain digital function
Examination.
Slave computer mainly includes USB interface, DUT board and TB plates, and DUT is by CPLD, FPGA and GPIO circuits and CS-SIM master
Module composition, by CPLD modularization design is carried out to FPGA, and quick reconfiguration realizes the hardware reconstruction of DUT, and DUT is again by loading
FC realizes software reconfiguration, and stimulation arrangement and measurement configuration are carried out to TB by CS-SIM primary modules generation bus C, by GPIO
Circuit receives signal excitation and produces response signal；TB is made up of CPLD, FPGA and GPIO circuits and CS-SIM slave modules, is passed through
CPLD carries out quick reconfiguration to FPGA, realizes reconfigurable type multiple test suite；TB receives the configuration of bus C by CS-SIM slave modules
After information, test suite is called to DUT output signals excitation X and receive output result Y.
Further, the TB, it passes through USB interface and is communicated with host computer, is entered with GPIO circuits by GPIO interface
Row communication, is communicated by CS-SIM interfaces (C mouths) with DUT.
Further, the C mouths are the universal serial bus of a master slave mode, and it is parallel that CS-SIM slave modules are switched to BIU
Bus, X signal produces required module, such as G0 signals generator, G1 sequence generators, and the measurement module of Y-signal,
Such as M0 frequency meters, M1 pulse width measures meter all carries are in BIU buses.In addition, if DUT includes following standard interface,
Such as UART, I2C, SPI, it is also possible to the carry correspondence standard interface module in BIU.
Because DUT is reconfigurable, GPIO pin arrangement change is various.In TB, the position of only C mouths pin is fixed
's.Change that the position of X pins and Y pins is configured with DUT and change.
Therefore in TB, there is a GPIO multiplexed arrays, and GPIO peripheral modules；GPIO multiplexed arrays will can appoint
The input and output of meaning G, M, S module are assigned in any GPIO peripheral modules, and GPIO peripheral modules draw for configuring any GPIO
The input of pin, output, upper drop-down isotype, the distribution and configuration of GPIO are also by by GPIO multiplexed arrays and GPIO peripheral hardware moulds
What block carry was realized in BIU buses.
The host computer using perl script as whole test system glue language, can automatic order call API
Hardware reconstruction is carried out to DUT and TB, compiler is recalled and FC codes is compiled and downloaded automatically.
After host computer test starting, main testing process is：
101st, the first step accesses ICE models storehouse and selects to specify model to carry out hardware reconstruction to DUT；
102nd, second step accesses the suitable TB models of TB models storehouse selection and hardware reconstruction (optional) is carried out to TB；
103rd, the 3rd step accesses program use-case storehouse and carries out software reconfiguration to the program area of DUT；
104th, the 4th step test case specified brings into operation test.
ICE is divided from hardware, can be largely classified into 3 big functional modules：Emulation module, kernel module and peripheral hardware mould
Block.Therefore, CS-ATS method of testings can be divided into 3 big class：
1) copying test.For the class testing, it is not necessary to carry out the 102nd step of above-mentioned testing process.And test and use
Main program area, data field, register, PC pointers that DUT is read and write by API of example etc., and call single step, breakpoint operation, entirely
Speed operation emulation command etc., carrys out analog subscriber operating process on IDE.For the class testing, each test case matching one
Individual suitable program use-case, test and excitation and assert all in test case embody.
2) core functions test.For the class testing, it is not necessary to carry out the 102nd step of above-mentioned testing process.For such
Test, each program use-case, share a fixed test case, test and excitation and assert all in program use-case embody.
3) peripheral functionality test.For the class testing, each program use-case shares a fixed test case, surveys
Examination excitation embodies in TB, and test assertion embodies in program use-case.
Automatization test system and method for testing that the present invention is realized, can realize that all ICE support the digital work(of model
Can test, reduce the input of test manpower, largely reduce manually operated, substantially reduce testing process.And from
Dynamicization exports test log, facilitates tester quickly to pinpoint the problems, and then repairs chip design.
Description of the drawings
Fig. 1 is the structure principle chart that the present invention is implemented.
Fig. 2 is the structural representation that the present invention is implemented.
Fig. 3 is the TB logical architecture figures that the present invention is implemented.
Fig. 4 is the script test flow chart that the present invention is implemented.
Fig. 5 is the testing case flow chart that the present invention is implemented.
Fig. 6 is the program use-case test flow chart that the present invention is implemented.
Specific embodiment
In order that the objects, technical solutions and advantages of the present invention become more apparent, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that specific embodiment described herein is only to explain the present invention, and
It is not used in the restriction present invention.
Shown in Fig. 1, by the present invention a kind of schematic diagram of ICE automatization test systems of enforcement, in figure, the test system
Comprising host computer and slave computer two large divisions, wherein：
Host computer uses script as the central control board of test system, and houses ICE models storehouse, program use-case storehouse
(FC), TB use-cases storehouse and test case library (TC).
Slave computer is included：DUT and TB test boards, DUT is the hardware carrier of program use-case, and TB serves as the DUT inputs of system
The test suite such as the signal generator of excitation X and the signal measurement instrument of DUT output results Y.The host computer and slave computer pass through
Api interface is communicated.
With reference to shown in Fig. 2, host computer mainly includes control script, and TC, FC and API control script by calling RBF literary
Part carries out hardware reconstruction to DUT and TB, calls MSCL compiler test use-cases TC to generate EXE executable files, calls CSCL to intersect
Compiler use-case FC generates HEX files, and TC is loaded by API and realize in FC to DUT software reconfiguration, and performs certain digital work(
The test of energy.
Slave computer mainly includes USB interface, DUT board and TB plates, and DUT is by CPLD, FPGA and GPIO circuits and CS-SIM master
Module composition, by CPLD modularization design is carried out to FPGA, and quick reconfiguration realizes the hardware reconstruction of DUT, and DUT is again by loading
FC realizes software reconfiguration, and stimulation arrangement and measurement configuration are carried out to TB by CS-SIM primary modules generation bus C, by GPIO
Circuit receives signal excitation and produces response signal；TB is made up of CPLD, FPGA and GPIO circuits and CS-SIM slave modules, is passed through
CPLD carries out quick reconfiguration to FPGA, realizes reconfigurable type multiple test suite；TB receives the configuration of bus C by CS-SIM slave modules
After information, test suite is called to DUT output signals excitation X and receive output result Y.
TB, it passes through USB interface and is communicated with host computer, is communicated with GPIO circuits by GPIO interface, passes through
CS-SIM interfaces (C mouths) are communicated with DUT.
Fig. 3 show the logical architecture figure of TB, and with reference to shown in Fig. 3, C mouths are the universal serial bus of a master slave mode, CS-
SIM slave modules are switched to BIU parallel bus, and X signal produces required module, and such as G0 signals generator, G1 sequences is produced
Raw device, and the measurement module of Y-signal, such as M0 frequency meters, M1 pulse width measures meter all carries are in BIU buses.In addition,
If DUT includes following standard interface, such as UART, I2C, SPI, it is also possible to the carry correspondence standard interface module in BIU.
Because DUT is reconfigurable, GPIO pin arrangement change is various.In TB, the position of only C mouths pin is fixed
's.Change that the position of X pins and Y pins is configured with DUT and change.Therefore in TB, there are a GPIO multiplexed arrays,
And GPIO peripheral modules；The input and output of any G, M, S module can be assigned to any GPIO peripheral hardwares by GPIO multiplexed arrays
In module, GPIO peripheral modules are used to configuring input, output, the upper drop-down isotype of any GPIO pin, the distribution of GPIO with
Configuration is also by the way that GPIO multiplexed arrays and GPIO peripheral modules carry are realized in BIU buses.
Host computer using perl script as whole test system glue language, can automatic order call API to DUT
Hardware reconstruction is carried out with TB, compiler is recalled and FC codes is compiled and downloaded automatically.
Meanwhile, host computer, as test case is write, directly invokes the api interface of ICE offers using C++, can be quick
Friendly access ICE equipment.The assembler language coding use-case supported using ICE, and the program of DUT is loaded into by API
Qu Zhong.
Slave computer then using ICE motherboard circuits directly as TB test boards hardware circuit so as to support quick reconfiguration,
The characteristic that various ICE such as GPIO multiplexings possess.And all kinds of test suites needed for by reconstructed number logic realization DUT.
And, slave computer selects CS-SIM interfaces as the standard interface of TB collocation channels.DUT is quickly matched somebody with somebody by the interface
Put the test suite in TB and produce test signal, and the test result for reading test suite in TB.
Meanwhile, the integrated of all kinds of test suites of TB is realized from the bus architecture mode of one master and multiple slaves, using a kind of GPIO
Multiplexed arrays module realizes the pin dynamically distributes of all kinds of test suite input and output.
After host computer test starting, main testing process is：
101st, the first step accesses ICE models storehouse and selects to specify model to carry out hardware reconstruction to DUT；
102nd, second step accesses the suitable TB models of TB models storehouse selection and hardware reconstruction (optional) is carried out to TB；
103rd, the 3rd step accesses program use-case storehouse and carries out software reconfiguration to the program area of DUT；
104th, the 4th step test case specified brings into operation test.
Method of testing can be divided into 3 big class：
1) copying test.For the class testing, it is not necessary to carry out the 102nd step of above-mentioned testing process.And test and use
Main program area, data field, register, PC pointers that DUT is read and write by API of example etc., and call single step, breakpoint operation, entirely
Speed operation emulation command etc., carrys out analog subscriber operating process on IDE.For the class testing, each test case matching one
Individual suitable program use-case, test and excitation and assert all in test case embody.
2) core functions test.For the class testing, it is not necessary to carry out the 102nd step of above-mentioned testing process.For such
Test, each program use-case, share a fixed test case, test and excitation and assert all in program use-case embody.
3) peripheral functionality test.For the class testing, each program use-case shares a fixed test case, surveys
Examination excitation embodies in TB, and test assertion embodies in program use-case.
Thus, script, TC and FC are attached to, concrete condition is as follows：
As shown in figure 4, script process is：Console perform script, loading RBF carries out DUT hardware reconstructions, if judging test
Type is peripheral hardware test, then also needing to loading Rbf carries out the reconstruct of test suite.Then call CSCL to compile FC, load FC and arrive
Software reconfiguration is realized in DUT, calls MSCL to compile TC, performed TC and provide test and excitation, read DUT response results, console is sentenced
Break and provide test result.
The program loading of DUT and commissioning test action have TC control realizations.TC flow charts are as shown in figure 5, all surveys
Example TC on probation first initializes DUT parameter using similar flow process, reloads the program use-case FC operated in DUT.Then start
Perform artificial debugging order, such as single step, reset, commissioning test, setting breakpoint.The phase for reading DUT can be passed through after execution
Off status information, such as PC values, RAM areas content, ROM areas content judge whether DUT work is working properly etc..
The test of digital peripherals point input class and output class, input class provides signal excitation, DUT output response knots for TB
Really, TB is measured.Output class outputs signals to TB and measures for DUT.Two types are required for carrying out MCU digital peripherals
Initialization and the initialization of test suite, then carry out selecting excitation module and measurement mould according to the digital function of concrete test
Block.Digital peripherals test FC flow charts are as shown in Figure 6.
Therefore, the present invention is realized automatization test system and method for testing, can realize that all ICE support the number of model
Word functional test, reduces the input of test manpower, largely reduces manually operated, substantially reduces testing process.And
And output test log is automated, facilitate tester quickly to pinpoint the problems, and then repair chip design.
Presently preferred embodiments of the present invention is the foregoing is only, not to limit the present invention, all essences in the present invention
Any modification, equivalent and improvement made within god and principle etc., should be included within the scope of the present invention.
Claims (10)
1. a kind of ICE automatization test systems, the test system includes host computer and slave computer two large divisions, and its feature exists
In：
The host computer uses script as the central control board of test system, and house ICE models storehouse, program use-case storehouse,
TB use-cases storehouse and test case library；
The slave computer is included：DUT and TB test boards, DUT is the hardware carrier of program use-case, and TB serves as the DUT inputs of system
The test suite such as the signal generator of excitation X and the signal measurement instrument of DUT output results Y；
The host computer and slave computer are communicated by api interface.
2. ICE automatization test systems as claimed in claim 1, it is characterised in that host computer mainly includes control script,
TC, FC and API, control script carries out hardware reconstruction by calling RBF files to DUT and TB, calls MSCL compiler test use-cases
TC generates EXE executable files, calls CSCL cross complier use-cases FC to generate HEX files, and TC loads FC and arrives by API
Software reconfiguration is realized in DUT, and performs the test of certain digital function.
3. ICE automatization test systems as claimed in claim 2, it is characterised in that slave computer mainly includes USB interface, DUT
Plate and TB plates, DUT is made up of CPLD, FPGA and GPIO circuits and CS-SIM primary modules, when being configured to FPGA by CPLD
Sequence, quick reconfiguration realizes the hardware reconstruction of DUT, and DUT realizes software reconfiguration by loading FC again, and by CS-SIM primary modules
Producing bus C carries out stimulation arrangement and measurement configuration to TB, receives signal excitation by GPIO circuits and produces response signal；TB
By CPLD, FPGA and GPIO circuits and CS-SIM slave modules are constituted, and quick reconfiguration is carried out to FPGA by CPLD, realize restructural
Formula test suite；TB is received after the configuration information of bus C by CS-SIM slave modules, calls test suite to DUT output signals
Excitation X and reception output result Y.
4. ICE automatization test systems as claimed in claim 3, it is characterised in that the TB, its pass through USB interface with it is upper
Machine is communicated, and is communicated with GPIO circuits by GPIO interface, is communicated with DUT by CS-SIM interfaces.
5. ICE automatization test systems as claimed in claim 4, it is characterised in that the CS-SIM interfaces are principal and subordinate's moulds
The universal serial bus of formula, CS-SIM slave modules are switched to BIU parallel bus, and X signal produces required module all carries in BIU
In bus.
6. ICE automatization test systems as claimed in claim 3, it is characterised in that in TB, only CS-SIM interface pins
Position be fixed, the change that the position of X pins and Y pins is configured with DUT and change.
7., a GPIO multiplexing battle array be present in ICE automatization test systems as claimed in claim 6, it is characterised in that in TB
Row, and GPIO peripheral modules；GPIO multiplexed arrays can be assigned to the input and output of any G, M, S module outside any GPIO
If in module, GPIO peripheral modules are used to configure input, output, the upper drop-down isotype of any GPIO pin, the distribution of GPIO
It is also by the way that GPIO multiplexed arrays and GPIO peripheral modules carry are realized in BIU buses with configuration.
8. ICE automatization test systems as claimed in claim 1, it is characterised in that the host computer adopts perl script conduct
The glue language of whole test system, the API that calls of energy automatic order carries out hardware reconstruction to DUT and TB, recalls compiler
FC codes are compiled and downloaded automatically.
9. a kind of ICE automated testing methods, it is characterised in that after host computer test starting, main testing process is：
101st, the first step accesses ICE models storehouse and selects to specify model to carry out hardware reconstruction to DUT；
102nd, second step accesses the suitable TB models of TB models storehouse selection and hardware reconstruction (optional) is carried out to TB；
103rd, the 3rd step accesses program use-case storehouse and carries out software reconfiguration to the program area of DUT；
104th, the 4th step test case specified brings into operation test.
10. ICE automated testing methods as claimed in claim 9, it is characterised in that ICE is divided from hardware, mainly can be with
It is divided into 3 big functional modules：Emulation module, kernel module and peripheral module, therefore, it is big that CS-ATS method of testings can be divided into 3
Class：
1) copying test：For the class testing, it is not necessary to carry out the 102nd step of above-mentioned testing process, and test case master
Program area, data field, register, the PC pointers of DUT are read and write by API, and call single step, breakpoint operation, full speed running
Emulation command, carrys out analog subscriber operating process on IDE；For the class testing, each test case matches one suitably
Program use-case, test and excitation and assert all in test case embody；
2) core functions test：For the class testing, it is not necessary to carry out the 102nd step of above-mentioned testing process.For the class testing,
Each program use-case, share a fixed test case, test and excitation and assert all in program use-case embody；
3) peripheral functionality test：For the class testing, each program use-case shares a fixed test case, and test swashs
Encourage and embodied in TB, test assertion embodies in program use-case.
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| CN108763077B (en) * | 2018-05-24 | 2022-04-19 | 上海微小卫星工程中心 | Verification test system based on-satellite on-orbit reconfigurable FPGA software |
| CN108763077A (en) * | 2018-05-24 | 2018-11-06 | 上海微小卫星工程中心 | Verifying test system based on in-orbit reconfigurable FPGA software on star |
| CN109885433A (en) * | 2018-12-29 | 2019-06-14 | 芯海科技（深圳）股份有限公司 | A kind of method of quick test SPI communication module |
| CN109885433B (en) * | 2018-12-29 | 2022-09-16 | 芯海科技（深圳）股份有限公司 | Method for rapidly testing SPI communication module |
| CN110377473A (en) * | 2019-08-23 | 2019-10-25 | 珠海艾派克微电子有限公司 | MCU parameter test system and method |
| CN110782873A (en) * | 2019-11-12 | 2020-02-11 | 中国电子科技集团公司第四十一研究所 | Reconfigurable modular test system applicable to electronic equipment based on voice interaction |
| CN111965447A (en) * | 2020-07-22 | 2020-11-20 | 电子科技大学 | Hardware configurable analog signal comprehensive test system |
| CN111965447B (en) * | 2020-07-22 | 2022-10-18 | 电子科技大学 | Hardware configurable analog signal comprehensive test system |
| CN112506517A (en) * | 2020-11-30 | 2021-03-16 | 天津飞腾信息技术有限公司 | Bare computer system-level excitation cross compiling system and compiling method |
| CN112996034A (en) * | 2021-02-04 | 2021-06-18 | 苏州源控电子科技有限公司 | Network function testing device and method |
| CN112996034B (en) * | 2021-02-04 | 2022-06-24 | 苏州源控电子科技有限公司 | Network function testing device and method |
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