CN106649101B - A kind of ICE automatization test system and test method - Google Patents
A kind of ICE automatization test system and test method Download PDFInfo
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- CN106649101B CN106649101B CN201611020255.XA CN201611020255A CN106649101B CN 106649101 B CN106649101 B CN 106649101B CN 201611020255 A CN201611020255 A CN 201611020255A CN 106649101 B CN106649101 B CN 106649101B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3648—Software debugging using additional hardware
- G06F11/3652—Software debugging using additional hardware in-circuit-emulation [ICE] arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
Abstract
The invention discloses a kind of ICE automatization test system and test method, the test macro includes upper computer and lower computer two large divisions, and the host computer uses central control board of the script as test macro, and the slave computer includes: DUT and TB test board；The upper computer and lower computer is communicated by api interface.The automatization test system and test method that the present invention is realized are able to achieve the digital function test that all ICE support model, reduce the investment of test manpower, largely reduce manual operation, substantially reduce testing process.And output test log is automated, tester is facilitated quickly to find the problem, and then repairs chip design.
Description
Technical field
The invention belongs to automatization testing technique field, in particular to a kind of in-circuit emulation based on field programmable gate array
Device automatization test system and method.
Background technique
In-circuit emulator (ICE) is also referred to as hardware emulator, belong to used in MCU development process with chip Equivalent Physical
Device.The characteristic of its product seeks to functional characteristic, electrical characteristic and the physical characteristic etc. of stringent approaching to reality chip.User
Environment is developed using the equipment and its matched IDE, embedded programming, cross compile, real-time simulation tune can be rapidly performed by
Examination etc..Such equipment typically is provided with restructural characteristic, i.e. an ICE, can usually simulate the characteristic of a plurality of MCU chips.
However, it is incomparably huge that the test of product becomes a workload as the compatible chip type of ICE is more and more
Thing.Because the function of each MCU chip itself is many, and testing procedure includes the RTL verifying before flow, mould
Sample test, CP test after number hybrid verification, FPGA verifying and flow etc..ICE as another independent product,
Its test job amount naturally also increases by a year-on-year basis.So how by way of automatic test, realize test Case recurrence and
Traversal reduces the investment of test manpower, referred to as problem extremely important in ICE product development process.
If patent application 201510617717.5 discloses a kind of MCU emulation mode for ICE, this method passes through CS-
SIM main module and CS-SIM realize that wherein the CPU and CS-SIM main module of ICE is integrated in FPGA, CS-SIM from module
It is integrated in objective chip from module；CS-SIM main module passes through the SFR bus of monitoring CPU, reads and writes the related deposit of simulation in CPU
While device, SFR information is written in objective chip by CS-SIM bus；Pass through CS-SIM in objective chip from module
It receives SFR information and completes SFR configuration, finally simulation output is mapped on I/O port, realize chip interior digital analog interface to ICE number
The equivalence replacement of mould interface.However, there is no the models and various applications that record ICE from module by CS-SIM main module and CS-SIM
Program, for different ICE product tests, it is necessary to re-start all testing procedures, inevitably bring resource and
The waste of cost influences the efficiency of test.
Summary of the invention
Based on this, therefore primary mesh of the invention be to provide a kind of ICE automatization test system and test method, should be from
Dynamicization test macro and test method are able to achieve all ICE and support the digital function test of model, while can also extend support core
The digital automation test of the FPGA automatic Verification and print of piece.
Another mesh of the invention it is to provide a kind of ICE automatization test system and test method, the automation is surveyed
Test system and test method can be reduced the investment of test manpower, reduce manual operation, substantially reduce testing process, improve
Testing efficiency.
To achieve the above object, the technical solution of the present invention is as follows:
A kind of ICE automatization test system, the test macro include upper computer and lower computer two large divisions, in which:
The host computer uses central control board of the script as test macro, and houses ICE model library, program use-case
Library (FC, Firmware Case), TB use-case library and test case library (TC, Test Case)；
The slave computer includes: DUT (Device Under Test) ICE and TB itself (Test Board) test board,
DUT is the hardware carrier of program use-case, and TB serves as the signal generator of the DUT input stimulus X of system and DUT exports result Y's
The test suites such as signal measurement instrument；
The upper computer and lower computer is communicated by api interface.
Host computer mainly includes control script, TC, FC and API (Application Programming
Interface), control script calls MSCL (Microsoft by calling RBF file to carry out hardware reconstruction to DUT and TB
Compiler) compiler test use-case TC generates EXE executable file, calls CSCL (ChipSea Compiler) cross compile journey
Sequence use-case FC generates HEX file, and TC loads the survey realized software reconfiguration in FC to DUT, and execute certain digital function by API
Examination.
Slave computer mainly includes USB interface, DUT board and TB plate, and DUT is by CPLD, FPGA and GPIO circuit and CS-SIM master
Module composition carries out modularization design to FPGA by CPLD, is reconfigured quickly, realizes that the hardware reconstruction of DUT, DUT pass through load again
FC realizes software reconfiguration, and generates bus C by CS-SIM main module and carry out stimulation arrangement and measuring configuration to TB, passes through GPIO
Circuit receives signal excitation and generates response signal；TB is passed through by CPLD, FPGA and GPIO circuit and CS-SIM from module composition
FPGA is reconfigured quickly in CPLD, realizes reconfigurable type multiple test suite；TB receives the configuration of bus C by CS-SIM from module
After information, test suite is called to DUT output signal excitation X and receives output result Y.
Further, the TB is communicated by USB interface with host computer, by GPIO interface and GPIO circuit into
Row communication, is communicated by CS-SIM interface (C mouthfuls) with DUT.
Further, described C mouthfuls be a master slave mode universal serial bus, it is parallel that CS-SIM from module is switched to BIU
Bus, module required for X signal generates, such as the measurement module of G0 signal generator, G1 sequence generator and Y-signal,
Such as M0 frequency meter, M1 pulse width measure meter all carries is in BIU bus.In addition, if DUT includes following standard interface,
Such as UART, I2C, SPI can also correspond to standard interface module by carry in BIU.
Since DUT is restructural, GPIO pin arrangement variation multiplicity.In TB, the position of only C mouthfuls of pin is fixed
's.The position of X pin and Y pin changes with the variation that DUT is configured.
Therefore in TB, there are a GPIO multiplexed arrays and GPIO peripheral modules；GPIO multiplexed arrays can will appoint
The input and output of meaning G, M, S module are assigned in any GPIO peripheral module, and GPIO peripheral module draws for configuring any GPIO
The input of foot, output, upper drop-down isotype, the distribution of GPIO and configuration are also by by GPIO multiplexed arrays and GPIO peripheral hardware mould
What block carry was realized in BIU bus.
The host computer uses glue language of the perl script as entire test macro, the calling API of energy automatic order
Hardware reconstruction is carried out to DUT and TB, compiler is recalled and FC code is compiled and downloaded automatically.
After host computer test starting, main testing process are as follows:
101, first step access ICE model library selects specified model to carry out hardware reconstruction to DUT；
102, second step access TB model library selects suitable TB model to carry out hardware reconstruction (optional) to TB；
103, third step access program use-case library carries out software reconfiguration to the program area of DUT；
104, the 4th step is brought into operation test with specified test case.
ICE is divided from hardware, can be mainly divided into 3 big functional modules: emulation module, kernel module and peripheral hardware mould
Block.Therefore, CS-ATS test method can be divided into 3 major class:
1) copying is tested.For the class testing, the 102nd step for carrying out above-mentioned testing process is not needed.And it tests and uses
Main program area, data field, register, the PC pointer etc. that DUT is read and write by API of example, and single step, breakpoint is called to run, is complete
Speed operation emulation command etc., carrys out analog subscriber operating process on IDE.For the class testing, each test case matching one
A suitable program use-case, test and excitation and asserting all embody in test case.
2) core functions are tested.For the class testing, the 102nd step for carrying out above-mentioned testing process is not needed.For such
Test, each program use-case share a fixed test case, and test and excitation and asserting all embodies in program use-case.
3) peripheral functionality is tested.For the class testing, each program use-case shares a fixed test case, surveys
Examination excitation embodies in TB, and test assertion embodies in program use-case.
The automatization test system and test method that the present invention is realized are able to achieve the digital function that all ICE support model
It can test, reduce the investment of test manpower, largely reduce manual operation, substantially reduce testing process.And from
Dynamicization exports test log, and tester is facilitated quickly to find the problem, and then repairs chip design.
Detailed description of the invention
Fig. 1 is the structure principle chart that the present invention is implemented.
Fig. 2 is the structural schematic diagram that the present invention is implemented.
Fig. 3 is the TB logical architecture figure that the present invention is implemented.
Fig. 4 is the script test flow chart that the present invention is implemented.
Fig. 5 is the testing case flow chart that the present invention is implemented.
Fig. 6 is the program use-case test flow chart that the present invention is implemented.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
Shown in Fig. 1, implement the schematic diagram of ICE automatization test system a kind of for the present invention, in figure, the test macro
Include upper computer and lower computer two large divisions, in which:
Host computer uses central control board of the script as test macro, and houses ICE model library, program use-case library
(FC), TB use-case library and test case library (TC).
Slave computer includes: DUT and TB test board, and DUT is the hardware carrier of program use-case, and TB serves as the DUT input of system
Motivate the test suites such as the signal generator of X and the signal measurement instrument of DUT output result Y.The upper computer and lower computer passes through
Api interface is communicated.
As shown in connection with fig. 2, host computer mainly includes control script, TC, FC and API, and control script is by calling RBF text
Part carries out hardware reconstruction to DUT and TB, and MSCL compiler test use-case TC is called to generate EXE executable file, and CSCL is called to intersect
Compiler use-case FC generates HEX file, and TC is loaded by API realizes software reconfiguration in FC to DUT, and executes certain digital function
The test of energy.
Slave computer mainly includes USB interface, DUT board and TB plate, and DUT is by CPLD, FPGA and GPIO circuit and CS-SIM master
Module composition carries out modularization design to FPGA by CPLD, is reconfigured quickly, realizes that the hardware reconstruction of DUT, DUT pass through load again
FC realizes software reconfiguration, and generates bus C by CS-SIM main module and carry out stimulation arrangement and measuring configuration to TB, passes through GPIO
Circuit receives signal excitation and generates response signal；TB is passed through by CPLD, FPGA and GPIO circuit and CS-SIM from module composition
FPGA is reconfigured quickly in CPLD, realizes reconfigurable type multiple test suite；TB receives the configuration of bus C by CS-SIM from module
After information, test suite is called to DUT output signal excitation X and receives output result Y.
TB is communicated by USB interface with host computer, is communicated, is passed through with GPIO circuit by GPIO interface
CS-SIM interface (C mouthfuls) is communicated with DUT.
Fig. 3 show the logical architecture figure of TB, as shown in connection with fig. 3, C mouthfuls be a master slave mode universal serial bus, CS-
SIM is switched to BIU parallel bus, module required for X signal generates, as G0 signal generator, G1 sequence produce from module
The measurement module of raw device and Y-signal, such as M0 frequency meter, M1 pulse width measure meter all carries are in BIU bus.In addition,
If DUT includes following standard interface, such as UART, I2C, SPI, standard interface module can also be corresponded to by carry in BIU.
Since DUT is restructural, GPIO pin arrangement variation multiplicity.In TB, the position of only C mouthfuls of pin is fixed
's.The position of X pin and Y pin changes with the variation that DUT is configured.Therefore in TB, there are a GPIO multiplexed arrays,
And GPIO peripheral module；The input and output of any G, M, S module can be assigned to any GPIO peripheral hardware by GPIO multiplexed arrays
In module, GPIO peripheral module is used to configure the input, output, upper drop-down isotype of any GPIO pin, the distribution of GPIO and
Configuration is also by realizing GPIO multiplexed arrays and GPIO peripheral module carry in BIU bus.
Host computer uses glue language of the perl script as entire test macro, and the calling API of energy automatic order is to DUT
Hardware reconstruction is carried out with TB, compiler is recalled and FC code is compiled and downloaded automatically.
Meanwhile host computer is used as using C++ and writes test case, and the api interface of ICE offer is called directly, it can be quick
Friendly access ICE equipment.Program use-case is write using the assembler language that ICE is supported, and is loaded into the program of DUT by API
Qu Zhong.
Slave computer then uses ICE motherboard circuit directly as the hardware circuit of TB test board, its support is reconfigured quickly,
The characteristic that a variety of ICE such as GPIO multiplexing have.And pass through all kinds of test suites needed for reconstructed number logic realization DUT.
Moreover, slave computer selects standard interface of the CS-SIM interface as TB collocation channel.DUT is quickly matched by the interface
It sets the test suite in TB and generates test signal, and read the test result of test suite in TB.
Meanwhile the bus architecture mode of one master and multiple slaves being selected to realize the integrated of all kinds of test suites of TB, use a kind of GPIO
Multiplexed arrays module realizes that the pin of all kinds of test suite input and output dynamically distributes.
After host computer test starting, main testing process are as follows:
101, first step access ICE model library selects specified model to carry out hardware reconstruction to DUT；
102, second step access TB model library selects suitable TB model to carry out hardware reconstruction (optional) to TB；
103, third step access program use-case library carries out software reconfiguration to the program area of DUT；
104, the 4th step is brought into operation test with specified test case.
Test method can be divided into 3 major class:
1) copying is tested.For the class testing, the 102nd step for carrying out above-mentioned testing process is not needed.And it tests and uses
Main program area, data field, register, the PC pointer etc. that DUT is read and write by API of example, and single step, breakpoint is called to run, is complete
Speed operation emulation command etc., carrys out analog subscriber operating process on IDE.For the class testing, each test case matching one
A suitable program use-case, test and excitation and asserting all embody in test case.
2) core functions are tested.For the class testing, the 102nd step for carrying out above-mentioned testing process is not needed.For such
Test, each program use-case share a fixed test case, and test and excitation and asserting all embodies in program use-case.
3) peripheral functionality is tested.For the class testing, each program use-case shares a fixed test case, surveys
Examination excitation embodies in TB, and test assertion embodies in program use-case.
It is integrated to script, TC and FC as a result, concrete condition is as follows:
As shown in figure 4, script process are as follows: console perform script, load RBF carry out DUT hardware reconstruction, if judgement test
Type is peripheral hardware test, then also needs to load the reconstruct that Rbf carries out test suite.Then it calls CSCL to compile FC, loads FC and arrive
Software reconfiguration is realized in DUT, MSCL is called to compile TC, is executed TC and is provided test and excitation, read DUT response results, console is sentenced
Break and provides test result.
The program load and commissioning test movement of DUT has TC control to realize.TC flow chart is as shown in figure 5, all surveys
Example TC on probation uses similar process, first initializes DUT parameter, reloads the program use-case FC operated in DUT.Then start
Execute artificial debugging order, such as single step, reset, commissioning test, setting breakpoint.The phase of reading DUT can be passed through after execution
Off status information, such as PC value, the area RAM content, the area ROM content judge whether DUT work is working properly etc..
The test of digital peripherals point input class and output class, input class are that TB provides signal excitation, DUT output response knot
Fruit, TB are measured.Output class outputs signals to TB for DUT and measures.Two types require to carry out MCU digital peripherals
Then the initialization of initialization and test suite carries out selection excitation module according to the digital function specifically tested and measures mould
Block.It is as shown in Figure 6 that digital peripherals test FC flow chart.
Therefore, the automatization test system and test method that the present invention is realized, are able to achieve the number that all ICE support model
Word functional test reduces the investment of test manpower, largely reduces manual operation, substantially reduce testing process.And
And automation output test log, facilitate tester quickly to find the problem, and then repair chip design.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Made any modifications, equivalent replacements, and improvements etc., should all be included in the protection scope of the present invention within mind and principle.
Claims (10)
1. a kind of ICE automatization test system, the test macro includes upper computer and lower computer two large divisions, and feature exists
In:
The host computer uses central control board of the script as test macro, and houses ICE model library, program library, TB use
Example library and test case library；
The slave computer includes: DUT and TB test board, and DUT is the hardware carrier of program use-case, and TB serves as the DUT input of system
Motivate the signal generator of X and the signal measurement instrument test suite of DUT output result Y；
The upper computer and lower computer is communicated by api interface.
2. ICE automatization test system as described in claim 1, it is characterised in that host computer mainly includes control script,
TC, FC and API, control script call MSCL compiler test use-case by calling RBF file to carry out hardware reconstruction to DUT and TB
TC generates EXE executable file, and CSCL cross complier use-case FC is called to generate HEX file, and TC loads FC by API and arrives
Software reconfiguration is realized in DUT, and executes the test of certain digital function.
3. ICE automatization test system as claimed in claim 2, it is characterised in that slave computer mainly includes USB interface, DUT
Plate and TB plate, DUT is made of CPLD, FPGA and GPIO circuit and CS-SIM main module, when being configured by CPLD to FPGA
Sequence is reconfigured quickly, and realizes the hardware reconstruction of DUT, DUT passes through load FC again and realizes software reconfiguration, and passes through CS-SIM main module
It generates bus C and stimulation arrangement and measuring configuration is carried out to TB, signal excitation is received by GPIO circuit and generate response signal；TB
By CPLD, FPGA and GPIO circuit and CS-SIM are reconfigured quickly FPGA by CPLD from module composition, realize restructural
Formula test suite；TB after the configuration information that module receives bus C, calls test suite to DUT output signal by CS-SIM
It motivates X and receives output result Y.
4. ICE automatization test system as claimed in claim 3, it is characterised in that the TB, by USB interface with it is upper
Machine is communicated, and is communicated by GPIO interface with GPIO circuit, is communicated by CS-SIM interface with DUT.
5. ICE automatization test system as claimed in claim 4, it is characterised in that the CS-SIM interface is principal and subordinate's mould
The universal serial bus of formula, CS-SIM are switched to BIU parallel bus from module, and module all carries required for X signal generates are in BIU
In bus.
6. ICE automatization test system as claimed in claim 3, it is characterised in that in TB, only CS-SIM interface pin
Position be it is fixed, the position of X pin and Y pin changes with the variation that DUT is configured.
7. ICE automatization test system as claimed in claim 6, it is characterised in that in TB, there are a GPIO to be multiplexed battle array
Column and GPIO peripheral module；The input and output of any G, M, S module can be assigned to outside any GPIO by GPIO multiplexed arrays
If in module, GPIO peripheral module is used to configure the input, output, upper pull-down pattern of any GPIO pin, the distribution of GPIO and
Configuration is also by realizing GPIO multiplexed arrays and GPIO peripheral module carry in BIU bus.
8. ICE automatization test system as described in claim 1, it is characterised in that the host computer uses perl script conduct
The calling API of the glue language of entire test macro, energy automatic order carries out hardware reconstruction to DUT and TB, recalls compiler
FC code is compiled and downloaded automatically.
9. a kind of ICE automated testing method, it is characterised in that after host computer test starting, main testing process are as follows:
101, first step access ICE model library selects specified model to carry out hardware reconstruction to DUT；
102, second step access TB model library selects suitable TB model to carry out hardware reconstruction (optional) to TB；
103, third step access program use-case library carries out software reconfiguration to the program area of DUT；
104, the 4th step is brought into operation test with specified test case.
10. ICE automated testing method as claimed in claim 9, it is characterised in that ICE is divided from hardware, mainly can be with
It is divided into 3 big functional modules: emulation module, kernel module and peripheral module, therefore, it is big that CS-ATS test method can be divided into 3
Class:
1) copying is tested: for the class testing, do not need the 102nd step for carrying out above-mentioned testing process, and test case master
Program area, data field, register, the PC pointer of DUT are read and write by API, and call single step, breakpoint operation, full speed running
Emulation command carrys out analog subscriber operating process on IDE；For the class testing, each test case matches one suitably
Program use-case, test and excitation and asserting all embody in test case；
2) core functions are tested: for the class testing, not needing the 102nd step for carrying out above-mentioned testing process；For the class testing,
Each program use-case, shares a fixed test case, and test and excitation and asserting all embodies in program use-case；
3) peripheral functionality is tested: for the class testing, each program use-case shares a fixed test case, and test swashs
It encourages and is embodied in TB, test assertion embodies in program use-case.
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| CN107480057B (en) * | 2017-07-31 | 2020-11-24 | 芯海科技（深圳）股份有限公司 | Method for realizing Call Stack function in ICE |
| CN107977243A (en) * | 2017-11-27 | 2018-05-01 | 海尔优家智能科技（北京）有限公司 | A kind of third party's interface call method and device |
| CN108255650A (en) * | 2017-12-14 | 2018-07-06 | 芯海科技（深圳）股份有限公司 | It is a kind of to test the automated method for downloading HEX files |
| CN108763077B (en) * | 2018-05-24 | 2022-04-19 | 上海微小卫星工程中心 | Verification test system based on-satellite on-orbit reconfigurable FPGA software |
| CN109885433B (en) * | 2018-12-29 | 2022-09-16 | 芯海科技（深圳）股份有限公司 | Method for rapidly testing SPI communication module |
| CN110377473A (en) * | 2019-08-23 | 2019-10-25 | 珠海艾派克微电子有限公司 | MCU parameter test system and method |
| CN110782873A (en) * | 2019-11-12 | 2020-02-11 | 中国电子科技集团公司第四十一研究所 | Reconfigurable modular test system applicable to electronic equipment based on voice interaction |
| CN111965447B (en) * | 2020-07-22 | 2022-10-18 | 电子科技大学 | Hardware configurable analog signal comprehensive test system |
| CN112506517A (en) * | 2020-11-30 | 2021-03-16 | 天津飞腾信息技术有限公司 | Bare computer system-level excitation cross compiling system and compiling method |
| CN112996034B (en) * | 2021-02-04 | 2022-06-24 | 苏州源控电子科技有限公司 | Network function testing device and method |
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