WO2022052161A1

WO2022052161A1 - Chip debugging system and debugger

Info

Publication number: WO2022052161A1
Application number: PCT/CN2020/116886
Authority: WO
Inventors: 唐峰; 凌长师; 白耿
Original assignee: 国微集团(深圳)有限公司
Priority date: 2020-09-09
Filing date: 2020-09-22
Publication date: 2022-03-17
Also published as: CN112114899A

Abstract

A chip debugging system and a debugger. The chip debugging system comprises: an FPGA processor, an FPGA logic array, and a debugger which is arranged in a computer, wherein the debugger is used for providing a graphical interface for a user to set an interface type of an FPGA, and sending a corresponding interface configuration file to the FPGA processor according to the setting made by the user; the FPGA processor is used for programming the interface configuration file into the FPGA logic array; and the FPGA logic array is used for simulating a corresponding communication interface according to the interface configuration file. By means of the method, compatibility for chips with a variety of interfaces can be realized.

Description

A chip debugging system and debugger

technical field

The invention relates to the field of chip testing, in particular to a chip debugging system and a debugger.

Background technique

With the development of the EDA industry, the global chip manufacturing demand continues to increase. In order to achieve fast and reliable chip verification and debugging, the performance requirements of the EDA debugging system will become higher and higher. The current EDA chip debugging tools are mainly logic analyzers and debugging equipment for specific occasions. Although a small number of EDA equipment directly uses FPGA, the FPGA debugging tools are customized through the function of the chip to meet the chip production debugging, but this requires the speed of the chip. In other words, it is far from keeping up with the pace of chip development.

The traditional EDA debugging tools have low debugging efficiency, relatively fixed interfaces, and poor interface compatibility.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a chip debugging system and a debugger with good interface compatibility, aiming at the problems existing in the above-mentioned prior art.

In the embodiment of the present invention, a chip debugging system is provided, which especially includes: an FPGA processor, an FPGA logic array, and a debugger set in a computer,

The debugger is used to provide a graphical interface for the user to set the interface type of the FPGA, and send the corresponding interface configuration file to the FPGA processor according to the user's setting;

The FPGA processor is used to program the interface configuration file into the FPGA logic array;

The FPGA logic array is used to simulate a corresponding communication interface according to the interface configuration file.

In the embodiment of the present invention, the debugger is preset with a plurality of interface configuration files corresponding to the type of the communication interface.

In the embodiment of the present invention, the communication interface types include a JTAG interface, an I2C interface, an SPI interface, a UART interface and an I/O interface.

In this embodiment of the present invention, the debugger includes:

The graphical interface providing module is used to provide a graphical interface for users to set the interface type of the FPGA logic array;

The configuration file transmission module is configured to send the corresponding interface configuration file to the FPGA processor according to the interface type set by the user.

In this embodiment of the present invention, the debugger further includes:

The script library is used to pre-store multiple interface configuration files corresponding to various communication interface types.

In the embodiment of the present invention, the chip debugger further includes:

The configuration file obtaining module is configured to obtain the corresponding interface configuration file from the script library according to the interface type set by the user.

In the embodiment of the present invention, a chip debugger is also provided, which includes:

Graphical interface providing module, used to provide a graphical interface for users to set the interface type of FPGA;

The configuration file transmission module is configured to send the corresponding interface configuration file to the FPGA processor according to the interface type set by the user, so as to configure the FPGA logic array.

In the embodiment of the present invention, the chip debugger further includes:

Compared with the prior art, using the chip debugging system and the debugger of the present invention, the designed virtual logic codes are classified and managed, and then encapsulated in their own text library, and the user can indirectly change the FPGA through the visual interface. Internal logic, and then generate the corresponding virtual interface according to the content configured by the interface. Finally, each virtual interface can be selectively assigned to the board hardware interface. By executing the script, each different interface can be instantiated, and then used by the FPGA. Call, and finally generate synthesizable logic, the user can freely configure on the PC side to change the virtual hardware debugging interface, so as to achieve the purpose of configuring different interfaces.

Description of drawings

FIG. 1 is a schematic structural diagram of a chip debugging system according to an embodiment of the present invention.

FIG. 2 is a schematic structural diagram of a chip debugger according to an embodiment of the present invention.

FIG. 3 is a flow chart of the use of the chip debugging system according to the embodiment of the present invention.

detailed description

As shown in FIG. 1 , in an embodiment of the present invention, a chip debugging system is provided, which includes: an FPGA processor, an FPGA logic array, and a debugger set in a computer. The computer can communicate with the FPGA processor via Ethernet. The FPGA processor and the FPGA may be located in one FPGA mainboard, or may be arranged in different FPGA mainboards. The FPGA can be connected with the pins of the chip to be tested through a flexible circuit board.

The debugger is configured to provide a graphical interface for a user to set the interface type of the FPGA logic array, and send a corresponding interface configuration file to the FPGA processor according to the user's setting.

It should be noted that the chip debugging system is mainly used to debug the chip. Since different chips have different communication interfaces, different interface devices need to be used to debug the chips. Therefore, in the embodiment of the present invention, an FPGA logic array is used to simulate different communication interfaces. In order to facilitate the configuration of the FPGA, in the embodiment of the present invention, a plurality of interface configuration files corresponding to the communication interface type are preset in the debugger, and the debugger is used to provide an image interface to set the interface type of the FPGA. . The user only needs to select the corresponding communication interface type, channel and quantity in the graphical interface provided by the debugger, and the debugger can automatically obtain the corresponding interface configuration file. After the user setting is completed, the debugger can send the interface configuration file corresponding to the communication interface set by the user to the FPGA processor. The debugger is also used to provide a graphical interface to control the signals collected and output by the PFGA processor, and to display the debug results in real time.

The FPGA processor is used for programming the interface configuration file into the FPGA logic array.

It should be noted that, in the embodiment of the present invention, the FPGA processor is used to program the FPGA logic array. After the FPGA processor acquires the interface configuration file sent by the debugger, it writes it into the FPGA logic array. The PFGA processor can simultaneously program interface configuration files into multiple PFGA logic arrays.

The FPGA logic array is used for simulating a corresponding communication interface according to the interface configuration file, and the user can assign the position of the interface pins as required.

It should be noted that, according to the characteristics of the FPGA logic array, it can simulate various communication interfaces according to the programmed interface configuration file, so as to communicate with the chip to be tested. In the embodiment of the present invention, the types of the communication interface include a JTAG interface, an I2C interface, an SPI interface, a UART interface and an I/O interface.

In the embodiment of the present invention, two FPGA logic arrays are used, and the user can also add multiple FPGA logic arrays according to actual requirements to increase resources and realize more channels.

As shown in FIG. 2 , the debugger includes a graphical interface providing module, a script library, a configuration file acquisition module and a configuration file transmission module. Each of them will be described below.

The graphical interface providing module is used to provide a graphical interface for the user to set the interface type of the FPGA.

The script library is used to pre-store a plurality of interface configuration files corresponding to various communication interface types.

The interface configuration file transmission module is configured to send the corresponding interface configuration file to the FPGA processor according to the interface type set by the user.

As shown in FIG. 3 , the process of using the chip debugging system to debug the chip is as follows:

The user selects the current device model to be debugged through the graphical interface provided by the debugger on the PC side, and sets relevant parameters of the device according to the requirements. After the parameter setting is completed, the debugger will generate an interface configuration file corresponding to the set parameters and send it to An FPGA processor, where the FPGA processor performs firmware programming on the FPGA logic array. After the chip under test is connected to the FPGA logic array, chip debugging can be performed. The type and quantity of virtual interfaces connected to peripherals can be customized. All virtual peripheral interfaces are composed of logic units, which can be freely programmed to obtain the desired interface, which is very flexible.

To sum up, using the chip debugging system and the debugger of the present invention, the designed virtual logic codes are classified and managed, and then encapsulated in their own text library. The user can indirectly change the internal logic virtual code of the FPGA through the visual interface. Interface, each different interface can be instantiated by executing the script, and then called by the FPGA to finally generate synthesizable logic. The user can configure the virtual hardware debugging interface at will on the PC side, so as to achieve their own Purpose.

The above descriptions are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention shall be included in the protection of the present invention. within the range.

Claims

A chip debugging system, comprising: an FPGA processor, an FPGA logic array, and a debugger set in a computer,

The debugger is used to provide a graphical interface for the user to set the communication interface type of the FPGA, and send the corresponding interface configuration file to the FPGA processor according to the user's setting;

The FPGA processor is used to program the interface configuration file into the FPGA logic array;

The FPGA logic array is used to simulate a corresponding communication interface according to the interface configuration file.
The chip debugging system according to claim 1, wherein, in the debugger, a plurality of interface configuration files corresponding to the communication interface type are preset.
The chip debugging system according to claim 1, wherein the communication interface types include JTAG interface, I2C interface, SPI interface, UART interface and I/O interface.
The chip debugging system according to claim 1, wherein the debugger comprises:

The graphical interface providing module is used to provide a graphical interface for users to set the interface type of the FPGA logic array;

The configuration file transmission module is configured to send the corresponding interface configuration file to the FPGA processor according to the interface type set by the user.
The chip debugging system according to claim 4, wherein the debugger further comprises:

The script library is used to pre-store multiple interface configuration files corresponding to various communication interface types.
The chip debugger according to claim 5, further comprising:

The configuration file obtaining module is configured to obtain the corresponding interface configuration file from the script library according to the interface type set by the user.
A chip debugger, characterized in that it includes:

Graphical interface providing module, used to provide a graphical interface for users to set the interface type of FPGA;

The configuration file transmission module is configured to send the corresponding interface configuration file to the FPGA processor according to the interface type set by the user, so as to configure the FPGA logic array.
The chip debugger according to claim 7, wherein the communication interface types include JTAG interface, I2C interface, SPI interface, UART interface and I/O interface.
The chip debugger according to claim 7, further comprising:

The script library is used to pre-store multiple interface configuration files corresponding to various communication interface types.
The chip debugger according to claim 9, further comprising:

The configuration file obtaining module is configured to obtain the corresponding interface configuration file from the script library according to the interface type set by the user.