CN202189124U - FPGA multiple real-time reconfiguration adapter based on test system - Google Patents
FPGA multiple real-time reconfiguration adapter based on test system Download PDFInfo
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- CN202189124U CN202189124U CN2011202603946U CN201120260394U CN202189124U CN 202189124 U CN202189124 U CN 202189124U CN 2011202603946 U CN2011202603946 U CN 2011202603946U CN 201120260394 U CN201120260394 U CN 201120260394U CN 202189124 U CN202189124 U CN 202189124U
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Abstract
The utility model provides a FPGA multiple real-time reconfiguration adapter based on a test system, comprising an electric design automation (EDA) development supporting board and a configuration test board matching a tested FPGA. The EDA development supporting board carries out programming design to generate an EDA code configuration file according to the tested FPGA programmable logic resource, and comprises a configuration memorizer switching unit, and the configuration test board comprises a configuration memorizer array, a multi-path selector array and an FPGA socket supplied for the connection of the tested FPGA; wherein, the configuration memorizer array is composed of multi-groups of memorizers, stores the EDA code configuration files generated by the EDA development supporting board and is connected between the multi-path selector array and the FPGA socket; the configuration memorizer switching unit transmits a switching signal to the multi-path selector array of the configuration test board via an international standard protocol port when debugs the EDA code configuration file and downloads the EDA code configuration file to the configuration memorizer of the configuration test board, and the multi-path selector array selects a configuration memorizer group on the configuration test board to work according to the switching signal.
Description
[technical field]
The utility model relates to technical field of measurement and test, particularly about the multiple adapter of reshuffling in real time of the on-site programmable gate array FPGA of test macro (Field Programmable Gate Array is called for short FPGA).
[background technology]
SRAM (Static Random Access Memory SRAM) type FPGA on the existing LSI testing system (like 93000 serial LSI testing systems of Verigy company production) has power down and is prone to lose characteristic;, FPGA need carry out the logic function circuit configuration before being tested to the resource of FPGA inside; Through supporting the developing software of manufacturer device is programmed and the configurator download; Programming and download all are under Windows operating system, to accomplish, and the workstation of V93000 testing apparatus is a (SuSE) Linux OS, and the operation of software environment all has corresponding relation with system hardware; Can not move developing software of FPGA FPGA is configured download; Simple test daughter board can not carry out the test of FPGA, because the test of the inner different ingredients of FPGA needs different configuration logic, a kind of logical resource of every test or an AC/DC parameter all need the preceding programmed configurations of once test; So will carry out complete test to FPGA; Just need repeatedly programme repeatedly, dispose, make setup time and test duration all long, reduce testing efficiency FPGA.
[summary of the invention]
The purpose of the utility model is to provide a kind of FPGA based on test macro that addresses the above problem the multiple adapter of reshuffling in real time; It has realized the online multiple adapter design of reshuffling in real time of SRAM type on-site programmable gate array FPGA, has the advantage that setup time is short, lower test duration, raising testing efficiency.
The multiple adapter of reshuffling in real time of the on-site programmable gate array FPGA that the utility model provides based on test macro; Comprise: electric design automation EDA development support plate and the configuration testing plate two parts that match with survey FPGA; EDA development support buttress carries out programmed according to survey FPGA programmable logic resource and generates EDA code configuration file, and it comprises the config memory switch unit; The configuration testing plate comprises: the FPGA socket that configurable memory array, multi path selector array and FPGA that confession is surveyed are connected; Wherein configurable memory array is made up of multi-bank memory, the EDA code configuration file that its storage EDA development support plate generates; Configurable memory array is connected between multi path selector array and the FPGA socket; The config memory switch unit is at debugging EDA code configuration file, when downloading EDA code configuration file to the config memory of configuration testing plate; Transmit the multi path selector array of switching signal to the configuration testing plate through international standard test protocol port, multi path selector array is selected the config memory group work on the configuration testing plate according to switching signal.
Wherein, One of the config memory switch unit of described EDA development support plate is a 4-bit DIP switch; These four dial-ups are respectively signal OEB, OEA, S1 and S0; Four dial-up signals are delivered to the multi path selector array of configuration testing plate through international standard test protocol port, by the memory set work of multi path selector array control configurable memory array, when OEB is height and OEA when low; The wherein memory chip work in one group in the configurable memory array; OEB is low and OEA when being high, the memory chip work in another group in the configurable memory array, and S1, S0 can accomplish the switching of four config memorys in each config memory chipset.
Wherein, Said EDA development support plate also comprises power supply signal unit, reset signal button, reshuffles the signal button, the independent clock signal module; Wherein insert the power supply signal unit and produce configuration testing plate required voltage through voltage transformation module, the power supply signal after the conversion is delivered to each device on the configuration testing plate through international standard test protocol port; The reset signal button is that FPGA work provides reset signal; Reconfigure by key control FPGA through reshuffling signal; The independent clock signal unit is that the FPGA work of being surveyed provides the global clock signal.
Wherein, Multi path selector array comprises ten two No. four selector switchs; Configurable memory array comprises eight XCFxxS config memorys; Have during configuration TDO, TDI, TMS, TCK ,/CEO, D0, CLK ,/CF, OE/RESET ,/CE totally ten road signals; Each two No. four selector switch can be realized the selection of the two paths of signals of four config memorys, and per 5 two No. four selector switchs realize that the switching of 4 config memorys reshuffles signal and the reset signal ordinary numbers passage through test macro and apply, and realizes reshuffling and resetting of circuit.
Wherein, Said power supply signal unit produces work core voltage VCCINT, IO port voltage VCCO, configured port voltage VCCAUX, MUX WV, the config memory WV that required voltage has FPGA through voltage transformation module, and identical voltage uses same source.
Wherein, the direct supply of the external 5V/3A of EDA development support plate.
Wherein, EDA development support plate also comprises the debug extensions unit; It comprises part pull-up resistor net and light emitting diode lamp; Be used for when adapter debugging or the checking of EDA code configuration file, the demonstration directly perceived of giving FPGA input signal or FPGA output signal, described shows signal directly perceived is transmitted through international standard test protocol port.
Wherein, The configuration testing plate also comprises first download interface and second download interface, and first download interface and second download interface meet the international standard test protocol, when debugging checking EDA code; Supply power by EDA development support plate; First download interface only forms international standard test protocol chain with tested FPGA, directly EDA code configuration file is downloaded among the FPGA, and power down is promptly lost; Memory chip is formed an international standard test protocol chain in second download interface and tested FPGA, the configurable memory array; EDA code configuration file is downloaded in the configurable memory array; Power down is difficult for losing, when configuration testing plate disengaging EDA development support plate, when on test macro, testing FPGA; By the test macro power supply, data download to the FPGA from the config memory chip through international standard test protocol chain.
Wherein, the configuration testing plate also comprises the GIS of the address information system connector that is connected with the motherboard of test macro, and its power supply with test macro, digital signal are guided on the configuration testing plate, are connected to each device on the plate through PCB layout.
Wherein, Said EDA development support plate links to each other with configuration testing plate one side; EDA development support plate will download in the config memory in the configuration testing plate through international standard test protocol interface the EDA code configuration file that the FPGA programmable logic resource carries out generating after the programmed; For the configuration testing plate provides power supply, clock input signal, configuration control signal, support the config memory program of configuration testing plate to download; The configuration testing plate is after accomplishing the download of EDA code configuration file; Break away from EDA development support plate, be directly installed on the test macro, supply power to daughter board by test macro; Drive the FPGA device by test vector through TCH test channel and dispose in real time, and the output that detects FPGA accord with expectation value whether.
The utility model is owing to concentrated a lot of config memorys on the adapter, and the speed of reshuffling is fast, efficient is high, has shortened the test duration of FPGA greatly, and human cost has also been saved in configuration automatically.The utility model is through interface J1, J2 simultaneously; Broken through the incompatible difficult problem that can not dispose of causing of test macro and FPGA development environment; Can on test macro, realize disposing before the test of FPGA; And be multiple real-time configuration, can increase the test event of FPGA and the number of config memory flexibly, can more comprehensively test FPGA through expanding.
The utility model has been realized the online multiple adapter design of reshuffling in real time of SRAM type on-site programmable gate array FPGA (Field Programmable Gate Array) on LSI testing system V93000.Solved the multiple problem of reshuffling in real time of FPGA on the test macro through improvement, also significantly reduced setup time, test duration, improved testing efficiency the FPGA test adapter.
[description of drawings]
Fig. 1 is the multiple adapter functions module frame chart of reshuffling in real time of the FPGA based on test macro of the utility model.
[embodiment]
Reach technological means and the effect that predetermined purpose is taked for further setting forth the present invention; Below in conjunction with accompanying drawing and preferred embodiment; To the multiple adapter of reshuffling in real time of the FPGA based on test macro that proposes according to the utility model; Its embodiment, structure, characteristic and effect thereof, explain as after.
The multiple adapter of reshuffling in real time of the FPGA based on test macro that the utility model provides comprises EDA (Electronic Design Automation, electric design automation) development support plate 100 and configuration testing plate 200 two parts.The major function of EDA development support plate 100: after will carrying out the logic function programmed to the FPGA programmable logic resource, the EDA code (configuration file) of generation passes through jtag interface (Joint Test Action Group from microcomputer; Combined testing action group; Be a kind of international standard test protocol) when downloading in the config memory in the configuration testing plate; EDA development support plate 100 links to each other with configuration testing plate 200 1 sides; For the configuration testing plate provides power supply, clock input signal, configuration control signal, FPGA output signal observation indication etc., support the config memory program of configuration testing plate 200 to download.The major function of configuration testing plate 200: after accomplishing the download of EDA code; Break away from EDA development support plate 100; Be directly installed on the test macro; Supply power to daughter board by test macro, drive the FPGA device by test vector through TCH test channel and dispose in real time, and the output that detects FPGA accord with expectation value whether.One-piece construction is as shown in Figure 1.
EDA development support plate 100 comprises power supply signal unit 101, reset signal button 102, reshuffles signal button 103, independent clock signal module 104, debug extensions unit 106 and config memory switch unit 105 and a plurality of international standard test protocol port.Configuration testing plate 200 comprises GIS (Geographic Information System address information system) connector 201, configurable memory array 202, multi path selector array 203 and FPGA socket 204 and the international standard test protocol port that matches with EDA development support plate 100.Wherein configurable memory array 202 is connected between multi path selector array 203 and the FPGA socket 204.The J1, the J2 download interface that meet international standard test protocol port.Configurable memory array 202 comprises multi-bank memory, is used for store configuration files.
The direct supply of EDA development support plate 100 external 5V/3A wherein; Insert power supply signal unit 101; Produce required voltage through voltage transformation module (figure does not show); Work core voltage VCCINT, IO port voltage VCCO, configured port voltage VCCAUX, MUX WV, the configuration ROM WV of FPGA are arranged, and identical voltage can use same source, and power supply signal quantity is according to the FPGA of different model, config memory and difference; Power supply signal after the conversion is delivered to international standard test protocol port JP1 end through international standard test protocol port JP4 end, delivers to each device on the configuration testing plate 200 at last; Reset signal (Reset) button 102 is for FPGA work provides reset signal; Reshuffle signal (ReConfig) button 103, manually control FPGA and reconfigure; Independent clock signal unit 104 (square wave) provides the global clock signal for FPGA work; Debug extensions unit 105 comprises part pull-up resistor net (figure does not show) and LED pilot lamp (figure does not show) etc.; Be used for when adapter debugging or EDA code verification; Give the demonstration directly perceived of FPGA input signal or FPGA output signal, transmit signal through international standard test protocol port JP5, JP3 interface; Config memory switch unit 105 is 14 toggle switch; Be used at debugging EDA code, manually or automatically select the config memory chip on the configuration testing plate when downloading the EDA code to config memory; Be respectively signal OEB, OEA, S1 and S0; 4 signals are through the toggle switch setting, are delivered to the multi path selector array 203 of configuration testing plate 200 through international standard test protocol port JP6, JP2 interface, and OEB is height and OEA when low; The chip operation in one group wherein in the configurable memory array 202; OEB is low and OEA when being high, the chip operation in another group in the configurable memory array 202, and S1, S0 can accomplish the switching of 4 config memorys in each configuring chip group.
The utility model has been realized the multiple design of reshuffling adapter in real time of FPGA on test macro; Owing to concentrated a lot of config memorys on the adapter; The speed of reshuffling is fast, efficient is high, has shortened the test duration of FPGA greatly, and human cost has also been saved in configuration automatically.
The novelty of the utility model is that it has broken through the incompatible difficult problem that can not dispose of causing of test macro and FPGA development environment; Can on test macro, realize disposing before the test of FPGA; And be multiple real-time configuration; Can increase the test event of FPGA and the number of config memory flexibly through expanding, can more comprehensively test FPGA.
In this instructions, the present invention is described with reference to its certain embodiments, still, still can make various modifications and conversion obviously and does not deviate from the spirit and scope of the present invention.Therefore, instructions of the present invention and accompanying drawing are considered to illustrative and nonrestrictive.
Claims (10)
1. multiple adapter of reshuffling in real time of the on-site programmable gate array FPGA based on test macro; It is characterized in that; Comprise: electric design automation EDA development support plate and the configuration testing plate two parts that match with survey FPGA; EDA development support buttress carries out programmed according to survey FPGA programmable logic resource and generates EDA code configuration file, and it comprises the config memory switch unit; The configuration testing plate comprises: the FPGA socket that configurable memory array, multi path selector array and FPGA that confession is surveyed are connected; Wherein configurable memory array is made up of multi-bank memory, the EDA code configuration file that its storage EDA development support plate generates; Configurable memory array is connected between multi path selector array and the FPGA socket; The config memory switch unit is at debugging EDA code configuration file, when downloading EDA code configuration file to the config memory of configuration testing plate; Transmit the multi path selector array of switching signal to the configuration testing plate through international standard test protocol port, multi path selector array is selected the config memory group work on the configuration testing plate according to switching signal.
2. the multiple adapter of reshuffling in real time of the on-site programmable gate array FPGA based on test macro as claimed in claim 1; It is characterized in that; One of the config memory switch unit of described EDA development support plate is a 4-bit DIP switch, and these four dial-ups are respectively signal OEB, OEA, S1 and S0, and four dial-up signals are delivered to the multi path selector array of configuration testing plate through international standard test protocol port; Memory set work by multi path selector array control configurable memory array; When OEB is height and OEA when low, the wherein memory chip work in one group in the configurable memory array, OEB is low and OEA when being high; Memory chip work in another group in the configurable memory array, S1, S0 can accomplish the switching of four config memorys in each config memory chipset.
3. the multiple adapter of reshuffling in real time of the on-site programmable gate array FPGA based on test macro as claimed in claim 1; It is characterized in that; EDA development support plate also comprises power supply signal unit, reset signal button, reshuffles the signal button, the independent clock signal module; Wherein insert the power supply signal unit and produce configuration testing plate required voltage through voltage transformation module, the power supply signal after the conversion is delivered to each device on the configuration testing plate through international standard test protocol port; The reset signal button is that FPGA work provides reset signal; Reconfigure by key control FPGA through reshuffling signal; The independent clock signal unit is that the FPGA work of being surveyed provides the global clock signal.
4. the multiple adapter of reshuffling in real time of the on-site programmable gate array FPGA based on test macro as claimed in claim 3; It is characterized in that; Multi path selector array comprises ten two No. four selector switchs; Configurable memory array comprises eight XCFxxS config memorys, have during configuration TDO, TDI, TMS, TCK ,/CEO, D0, CLK ,/CF, OE/RESET ,/CE totally ten road signals, each two No. four selector switch can be realized the selection of the two paths of signals of four config memorys; Per 5 two No. four selector switchs realize that the switching of 4 config memorys reshuffles signal and the reset signal ordinary numbers passage through test macro and apply, and realize reshuffling and resetting of circuit.
5. the multiple adapter of reshuffling in real time of the on-site programmable gate array FPGA based on test macro as claimed in claim 4; It is characterized in that; Said power supply signal unit produces required voltage through voltage transformation module has the work core voltage VCCINT of FPGA, IO port voltage VCCO, configured port to press VCCAUX, MUX WV, config memory WV, and identical voltage uses same source.
6. the multiple adapter of reshuffling in real time of the on-site programmable gate array FPGA based on test macro as claimed in claim 5 is characterized in that the direct supply of the external 5V/3A of EDA development support plate.
7. the multiple adapter of reshuffling in real time of the on-site programmable gate array FPGA based on test macro as claimed in claim 5; It is characterized in that; EDA development support plate also comprises the debug extensions unit, and it comprises part pull-up resistor net and light emitting diode lamp, is used for when adapter debugging or the checking of EDA code configuration file; Give the demonstration directly perceived of FPGA input signal or FPGA output signal, described shows signal directly perceived is transmitted through international standard test protocol port.
8. the multiple adapter of reshuffling in real time of the on-site programmable gate array FPGA based on test macro as claimed in claim 1; It is characterized in that; The configuration testing plate also comprises first download interface and second download interface, and first download interface and second download interface meet the international standard test protocol, when debugging checking EDA code; Supply power by EDA development support plate; First download interface only forms international standard test protocol chain with tested FPGA, directly EDA code configuration file is downloaded among the FPGA, and power down is promptly lost; Memory chip is formed an international standard test protocol chain in second download interface and tested FPGA, the configurable memory array; EDA code configuration file is downloaded in the configurable memory array; Power down is difficult for losing, when configuration testing plate disengaging EDA development support plate, when on test macro, testing FPGA; By the test macro power supply, data download to the FPGA from the config memory chip through international standard test protocol chain.
9. the multiple adapter of reshuffling in real time of the on-site programmable gate array FPGA based on test macro as claimed in claim 8; It is characterized in that; The configuration testing plate also comprises the GIS of the address information system connector that is connected with the motherboard of test macro; Its power supply with test macro, digital signal are guided on the configuration testing plate, are connected to each device on the plate through PCB layout.
10. like the multiple adapter of reshuffling in real time of each described on-site programmable gate array FPGA among the claim 1-8 based on test macro; It is characterized in that; Said EDA development support plate links to each other with configuration testing plate one side; EDA development support plate will download in the config memory in the configuration testing plate through international standard test protocol interface the EDA code configuration file that the FPGA programmable logic resource carries out generating after the programmed; For the configuration testing plate provides power supply, clock input signal, configuration control signal, support the config memory program of configuration testing plate to download; The configuration testing plate is after accomplishing the download of EDA code configuration file; Break away from EDA development support plate, be directly installed on the test macro, supply power to daughter board by test macro; Drive the FPGA device by test vector through TCH test channel and dispose in real time, and the output that detects FPGA accord with expectation value whether.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102759674A (en) * | 2012-07-20 | 2012-10-31 | 航天科工防御技术研究试验中心 | Universal adapter for testing optocouplers |
| CN102818987A (en) * | 2012-07-03 | 2012-12-12 | 航天科工防御技术研究试验中心 | Multiple real-time reconfiguration adaptor used in test of field-programmable gate array device |
| CN104020409A (en) * | 2013-02-28 | 2014-09-03 | 中兴通讯股份有限公司 | Chip adaptive configuration method and device |
| CN104965168A (en) * | 2015-07-23 | 2015-10-07 | 北京华峰测控技术有限公司 | FPGA configuration system and method for testing of integrated circuit |
| CN105144114A (en) * | 2013-02-21 | 2015-12-09 | 爱德万测试公司 | A tester with mixed protocol engine in a FPGA block |
| CN106680698A (en) * | 2015-11-11 | 2017-05-17 | 上海复旦微电子集团股份有限公司 | Multi-station rapid configuration device and configuration method thereof for FPGA test |
| CN107589368A (en) * | 2017-08-24 | 2018-01-16 | 成都天奥技术发展有限公司 | EPC3C120F484 types FPGA configurations/test/debugging adapter |
| CN112014726A (en) * | 2020-08-05 | 2020-12-01 | 广东省新一代通信与网络创新研究院 | DSP chip testing device and method |
| CN112286845A (en) * | 2020-10-30 | 2021-01-29 | 重庆金美通信有限责任公司 | Transmission line switching system supporting multiple devices and multiple interfaces |
| CN112287623A (en) * | 2020-10-30 | 2021-01-29 | 中国电子科技集团公司第五十八研究所 | Pretesting platform based on FPGA and V93000 test machine |
| CN113297020A (en) * | 2021-05-20 | 2021-08-24 | 山东云海国创云计算装备产业创新中心有限公司 | Method, device and equipment for testing hardware module in chip and readable storage medium |
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2011
- 2011-07-22 CN CN2011202603946U patent/CN202189124U/en not_active Expired - Lifetime
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| CN102818987A (en) * | 2012-07-03 | 2012-12-12 | 航天科工防御技术研究试验中心 | Multiple real-time reconfiguration adaptor used in test of field-programmable gate array device |
| CN102818987B (en) * | 2012-07-03 | 2014-12-24 | 航天科工防御技术研究试验中心 | Multiple real-time reconfiguration adaptor used in test of field-programmable gate array device |
| CN102759674A (en) * | 2012-07-20 | 2012-10-31 | 航天科工防御技术研究试验中心 | Universal adapter for testing optocouplers |
| CN105144114A (en) * | 2013-02-21 | 2015-12-09 | 爱德万测试公司 | A tester with mixed protocol engine in a FPGA block |
| CN105144114B (en) * | 2013-02-21 | 2019-05-21 | 爱德万测试公司 | FPGA block has the tester of hybrid protocol engine |
| CN104020409A (en) * | 2013-02-28 | 2014-09-03 | 中兴通讯股份有限公司 | Chip adaptive configuration method and device |
| CN104965168A (en) * | 2015-07-23 | 2015-10-07 | 北京华峰测控技术有限公司 | FPGA configuration system and method for testing of integrated circuit |
| CN104965168B (en) * | 2015-07-23 | 2017-11-10 | 北京华峰测控技术有限公司 | A kind of FPGA for integrated circuit testing configures system and method |
| CN106680698B (en) * | 2015-11-11 | 2023-08-18 | 上海复旦微电子集团股份有限公司 | Multi-station rapid configuration device for FPGA test and configuration method thereof |
| CN106680698A (en) * | 2015-11-11 | 2017-05-17 | 上海复旦微电子集团股份有限公司 | Multi-station rapid configuration device and configuration method thereof for FPGA test |
| CN107589368A (en) * | 2017-08-24 | 2018-01-16 | 成都天奥技术发展有限公司 | EPC3C120F484 types FPGA configurations/test/debugging adapter |
| CN112014726A (en) * | 2020-08-05 | 2020-12-01 | 广东省新一代通信与网络创新研究院 | DSP chip testing device and method |
| CN112014726B (en) * | 2020-08-05 | 2023-09-05 | 广东省新一代通信与网络创新研究院 | DSP chip testing device and method |
| CN112286845A (en) * | 2020-10-30 | 2021-01-29 | 重庆金美通信有限责任公司 | Transmission line switching system supporting multiple devices and multiple interfaces |
| CN112287623A (en) * | 2020-10-30 | 2021-01-29 | 中国电子科技集团公司第五十八研究所 | Pretesting platform based on FPGA and V93000 test machine |
| CN112287623B (en) * | 2020-10-30 | 2022-08-02 | 中国电子科技集团公司第五十八研究所 | Pretesting platform based on FPGA and V93000 test machine |
| CN112286845B (en) * | 2020-10-30 | 2023-06-09 | 重庆金美通信有限责任公司 | Transmission line switching system supporting multiple devices and multiple interfaces |
| CN113297020A (en) * | 2021-05-20 | 2021-08-24 | 山东云海国创云计算装备产业创新中心有限公司 | Method, device and equipment for testing hardware module in chip and readable storage medium |
| CN113297020B (en) * | 2021-05-20 | 2023-02-28 | 山东云海国创云计算装备产业创新中心有限公司 | Method, device and equipment for testing hardware module in chip and readable storage medium |
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