CN113297020A - Method, device and equipment for testing hardware module in chip and readable storage medium - Google Patents
Method, device and equipment for testing hardware module in chip and readable storage medium Download PDFInfo
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- CN113297020A CN113297020A CN202110551292.8A CN202110551292A CN113297020A CN 113297020 A CN113297020 A CN 113297020A CN 202110551292 A CN202110551292 A CN 202110551292A CN 113297020 A CN113297020 A CN 113297020A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
Abstract
The invention discloses a method for testing a hardware module in a chip, which comprises the following steps: analyzing the received chip test request to obtain a target hardware module to be tested and a target signal position; switching the ground signal bits in each multi-path selector originally selected by default by the control register into each target signal bit selected by the chip test request; and testing the target hardware module by using each target signal bit. By applying the test method of the hardware module in the chip provided by the invention, when the hardware module is not required to be tested, signal jumping does not exist, and the power consumption of the chip is reduced. The invention also discloses a device, equipment and a storage medium for testing the hardware module in the chip, and the device, the equipment and the storage medium have corresponding technical effects.
Description
Technical Field
The present invention relates to the field of chip testing technologies, and in particular, to a method, an apparatus, a device, and a computer-readable storage medium for testing a hardware module in a chip.
Background
After the chip generation is completed, since the internal signals of the chip are very many, but the external pins of the chip are relatively few, it is usually very difficult to monitor the hardware modules in the chip.
In the existing test scheme of a hardware module in a chip, a group of Multiplexers (MUXs) which are programmable by software and controlled by a register are adopted, one side of each Multiplexer is connected with an internal signal of the chip, and the other side of each Multiplexer is connected with an external pin of the chip. When the hardware module is tested, the internal part of the chip is gated to an external pin according to user configuration so as to carry out direct measurement by using an oscilloscope, a logic analyzer and the like. When the hardware module in the chip is not required to be tested, the control register randomly selects a signal bit, and when the selected signal is a frequently-hopped signal like a clock, a state machine and the like, the signal jumps no matter whether the hardware module is required to be tested or not, so that the power consumption of the chip is increased.
In summary, how to effectively solve the problems of signal jump, power consumption increase of a chip and the like in the existing hardware module testing scheme in the chip no matter whether the hardware module testing is needed or not is a problem which needs to be solved urgently by a person skilled in the art at present.
Disclosure of Invention
The invention aims to provide a method for testing a hardware module in a chip, which has no signal jump when the hardware module is not required to be tested, thereby reducing the power consumption of the chip; another object of the present invention is to provide a device, an apparatus and a computer readable storage medium for testing hardware modules in a chip.
In order to solve the technical problems, the invention provides the following technical scheme:
a method for testing a hardware module in a chip comprises the following steps:
analyzing the received chip test request to obtain a target hardware module to be tested and a target signal position;
switching the ground signal bits in each multiplexer originally selected by default by the control register to the target signal bits selected by the chip test request;
and testing the target hardware module by using each target signal bit.
In a specific embodiment of the present invention, switching the ground signal bits in each multiplexer originally selected by default in the control register to each target signal bit selected in the chip test request includes:
and switching the grounding signal bits in each multiplexer corresponding to the target hardware module originally selected by default by the control register into the target signal bits selected by the chip test request.
In an embodiment of the present invention, after performing a test operation on the target hardware module by using each of the target signal bits, the method further includes:
and when the hardware module power-off triggering condition is reached, controlling the power supply circuit of the target hardware module to be switched off so as to enable each multiplexer preset in the power supply domain of the target hardware module to carry out power-off operation.
In an embodiment of the present invention, after performing a test operation on the target hardware module by using each of the target signal bits, the method further includes:
and when a subsystem power-off triggering condition is met, controlling a power supply circuit of a target subsystem to which the target hardware module belongs to be switched off so as to enable each multiplexer preset in a power supply domain of the target subsystem to carry out power-off operation.
In a specific embodiment of the present invention, after obtaining a target hardware module to be tested and a target signal bit, switching a ground signal bit in each multiplexer originally selected by default in a control register to each target signal bit selected by the chip test request, further includes:
counting the target number of each target signal bit;
respectively acquiring the number of signal connections between the target hardware module and each multiplexer;
judging whether the number of signal connections smaller than the target number exists or not;
if so, determining the multi-path selectors with the number of signal connections with the target hardware module smaller than the target number as target multi-path selectors;
and carrying out expansion operation on a connection bus between the target multiplexer and the target hardware module.
An apparatus for testing hardware modules in a chip, comprising:
the request analysis unit is used for analyzing the received chip test request to obtain a target hardware module to be tested and a target signal position;
a signal bit selection unit, configured to switch a ground signal bit in each multiplexer originally selected by default in the control register to each target signal bit selected by the chip test request;
and the module test unit is used for testing the target hardware module by utilizing each target signal bit.
In a specific embodiment of the present invention, the signal bit selecting unit is specifically a unit that switches a ground signal bit in each multiplexer corresponding to the target hardware module originally selected by default by the control register to each target signal bit selected by the chip test request.
In one embodiment of the present invention, the method further comprises:
and the first power supply control unit is used for controlling the power supply circuit of the target hardware module to be switched off when a hardware module power-off triggering condition is reached after the target hardware module is tested by using each target signal bit, so that each multiplexer preset in a power supply domain of the target hardware module is subjected to power-off operation.
A device for testing hardware modules in a chip, comprising:
a memory for storing a computer program;
and the processor is used for realizing the steps of the testing method of the hardware module in the chip when executing the computer program.
A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method for testing a hardware module in a chip as described above.
The method for testing the hardware module in the chip provided by the invention analyzes the received chip test request to obtain a target hardware module to be tested and a target signal position; switching the ground signal bits in each multi-path selector originally selected by default by the control register into each target signal bit selected by the chip test request; and testing the target hardware module by using each target signal bit. By presetting the grounding signal positions in each multiplexer selected by default by the control register when the chip test is not needed, when the hardware module test is not needed, signal jumping does not exist, charging and discharging caused by signal jumping does not exist, and the power consumption of the chip is reduced.
Correspondingly, the invention also provides a testing device, equipment and a computer readable storage medium of the hardware module in the chip, which correspond to the testing method of the hardware module in the chip.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a block diagram of a system for testing hardware modules in a chip;
FIG. 2 is a flowchart illustrating an implementation of a method for testing a hardware module in a chip according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating another embodiment of a method for testing a hardware module in a chip according to the present invention;
FIG. 4 is a schematic diagram of an input/output of a module-level multiplexer according to an embodiment of the present invention;
FIG. 5 is a block diagram of a system for testing hardware modules in a chip according to an embodiment of the present invention;
FIG. 6 is a block diagram of an apparatus for testing hardware modules in a chip according to an embodiment of the present invention;
FIG. 7 is a block diagram of a device for testing hardware modules in a chip according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a test apparatus for a hardware module in a chip according to this embodiment.
Detailed Description
In the existing test scheme of the hardware module in the chip, because signals to be tested have frequently jumping signals like a clock, a state machine and the like, when the signals are defaulted and selected signals of a control register, the signals can be communicated to the top layer MUX of the chip through a long path, namely through the module-level MUX and the subsystem-level MUX.
Referring to fig. 1, fig. 1 is a block diagram of a system for testing hardware modules in a chip. As shown in fig. 1 by the thick solid line. The signal jump is a 'charging and discharging' action in the chip, and the longer the signal path and the more frequent the jump, the more energy it consumes. Therefore, in the existing hardware module test scheme in the chip, no matter whether the hardware module test is needed or not, signal jump exists, and the power consumption of the chip is increased.
Therefore, in the test method of the hardware module in the chip provided by the application, when the hardware module is not required to be tested, signal jumping does not exist, and the power consumption of the chip is reduced.
In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 2, fig. 2 is a flowchart of an implementation of a method for testing a hardware module in a chip according to an embodiment of the present invention, where the method may include the following steps:
s201: and analyzing the received chip test request to obtain a target hardware module to be tested and a target signal position.
When the hardware module in the chip needs to be tested, a chip test request is sent to the test management center, and the chip test request comprises a target hardware module to be tested and a target signal position. The test management center receives the chip test request and analyzes the received chip test request to obtain a target hardware module to be tested and a target signal position.
S202: and switching the grounding signal bits in each multiplexer originally selected by default by the control register into each target signal bit selected by the chip test request.
And presetting default signal bits in each multiplexer selected by the control register as grounding signal bits. And after the test management center receives the chip test request and analyzes the chip test request to obtain a target hardware module to be tested and a target signal bit, switching the ground signal bit in each multiplexer originally selected by default by the control register into each target signal bit selected by the chip test request. The default signal bit in each multiplexer is preset as a grounding signal bit, the monitoring signal selected by the default of the control register is always grounded, if the lowest bit (bit 0) of each bottommost multiplexer (module level multiplexer) connected with the hardware module to be tested is always grounded, the rest positions are connected with the hardware module to be tested, and the lowest bit (bit 0) is selected by each bottommost multiplexer in the default, so that in a scene without signal debugging, for example, when the chip normally works after cold start, the value of the control register is set as a default value, no extra signal inversion exists on each level of multiplexers of the whole signal monitoring system, and the power consumption of the system can be effectively reduced.
S203: and testing the target hardware module by using each target signal bit.
And after the grounding signal bits in each multiplexer selected by the control register in a default mode are switched into the target signal bits selected by the chip test request, testing the target hardware module by using the target signal bits. Therefore, when the target hardware module is required to be tested, the value of the control register is rewritten according to the test requirement, each target signal bit is selected, and when the chip test is not required, the control register defaults to the selected grounding signal bit in each multiplexer, so that no signal jump exists, and the power consumption of the chip is reduced.
The method for testing the hardware module in the chip provided by the invention analyzes the received chip test request to obtain a target hardware module to be tested and a target signal position; switching the grounding signal bits in each multi-path selector selected by the control register as defaults to target signal bits selected by the chip test request; and testing the target hardware module by using each target signal bit. By presetting the grounding signal positions in each multiplexer selected by default by the control register when the chip test is not needed, when the hardware module test is not needed, signal jumping does not exist, charging and discharging caused by signal jumping does not exist, and the power consumption of the chip is reduced.
It should be noted that, based on the above embodiments, the embodiments of the present invention also provide corresponding improvements. In the following embodiments, steps that are the same as or correspond to those in the above embodiments may be referred to one another, and corresponding advantageous effects may also be referred to one another, which is not described in detail in the following modified embodiments.
Referring to fig. 3, fig. 3 is a flowchart of another implementation of the method for testing a hardware module in a chip according to the embodiment of the present invention, where the method may include the following steps:
s301: and analyzing the received chip test request to obtain a target hardware module to be tested and a target signal position.
S302: and counting the target number of each target signal bit.
And after the target signal bits are obtained through analysis, counting the target number of each target signal bit, so as to obtain the total number of the signal bits to be tested.
S303: and respectively acquiring the number of signal connections between the target hardware module and each multiplexer.
The target hardware module is in signal connection with each multiplexer respectively, and the number of signal connections between the target hardware module and each multiplexer is obtained respectively. For example, the number of signal connections between the multiplexer and the hardware module to be tested may be preset to be 32, 64, 128, 256, etc.
S304: it is determined whether there are less signal connections than the target number, if so, step S305 is executed, otherwise, no processing is performed.
After the target number of each target signal bit is obtained through statistics, and the number of signal connections between each target hardware module and each multiplexer is obtained respectively, whether the number of signal connections smaller than the target number exists is judged, if yes, the number of signal connections between the multiplexer and the target hardware module is insufficient, step S305 is executed, and if not, the number of signal connections between each multiplexer and the target hardware module is sufficient, and processing is not needed.
S305: and determining the multiplexers with the number of signal connections with the target hardware module smaller than the target number as target multiplexers.
When the signal connection number smaller than the target number is determined to exist, the fact that the signal connection number between the multi-path selector and the target hardware module is not enough currently exists is indicated, and the multi-path selector with the signal connection number smaller than the target number with the target hardware module is determined as the target multi-path selector, namely the signal connection number between the target multi-path selector and the target hardware module is not enough.
S306: and carrying out expansion operation on a connection bus between the target multiplexer and the target hardware module.
And after the target multi-path selectors with the number of signal connections with the target hardware modules smaller than the target number are determined, expanding the connection buses between the target multi-path selectors and the target hardware modules, so that sufficient signal connections between the target multi-path selectors and the target hardware modules are obtained through expansion, and effective bedding is made for the target hardware modules subsequently.
S307: and switching the grounding signal bits in each multiplexer corresponding to the target hardware module originally selected by default by the control register into each target signal bit selected by the chip test request.
Presetting each specific multiplexer corresponding to each hardware module to be tested, analyzing to obtain a target hardware module to be tested and a target signal position, determining that sufficient signal connection exists between the target hardware module and each multiplexer, and switching the ground signal position in each multiplexer corresponding to the target hardware module selected by the control register in an original default mode into each target signal position selected by the chip test request. The specific multiplexers are respectively arranged for each hardware module to be tested, so that the multiplexers corresponding to the hardware modules to be tested are independently controlled by taking the hardware modules to be tested as a unit.
Referring to fig. 4, fig. 4 is a schematic diagram of an input and an output of a module-level multiplexer according to an embodiment of the present invention. The module level MUX is responsible for selecting any 16 bits from 256 Bit (Bit) detection signals in a hardware module to be tested, and the interior of the module level MUX is designed to be 16 independent 256-to-1 MUXs, namely, the input 256-Bit signals are required to be connected to the internal MUXs. The lowest order signal (bit 0) may be set to be always grounded, and the remaining 255 interfaces are connected to the hardware module under test.
As shown in table 1, the lowest order signal is also all selected by its default value (reset value) to control the 32-bit control register of the 16 MUXs.
S308: and testing the target hardware module by using each target signal bit.
S309: and when the hardware module power-off triggering condition is reached, controlling the power supply circuit of the target hardware module to be switched off so as to enable each multiplexer preset in the power domain of the target hardware module to carry out power-off operation.
Presetting a hardware module power-off triggering condition, for example, presetting the power-off operation when the hardware module normally runs to a corresponding stage, or presetting the power-off operation when the hardware module normally runs for a preset time interval. And when the hardware module power-off triggering condition is reached, controlling the power supply circuit of the target hardware module to be switched off, so that each multiplexer preset in the power supply domain of the target hardware module performs power-off operation. Therefore, on-off control of each multi-path selector along with the corresponding hardware module to be tested is realized.
Referring to fig. 5, fig. 5 is a block diagram of a system for testing a hardware module in a chip according to an embodiment of the present invention. When the module x and the module y are in a power-off state, signal level debugging is unnecessary, and when a System on Chip (SoC) is integrated, the MUX of the module x is arranged in a power supply domain of the module x, and the MUX of the module y is arranged in a power supply domain of the module y, so that power supply of the two module-level MUXs can be completely cut off along with the module to be tested. Similarly, the module m and the module n are both located in the subsystem B, and when the system on chip is designed in an integrated manner, the MUXs of the module m and the module n are placed in the power domain of the subsystem B, so that the power supply of the MUXs at the two module levels can be completely cut off along with the subsystem to be tested.
In a specific embodiment of the present invention, after step S308, the method may further include the steps of:
and when the subsystem power-off triggering condition is reached, controlling the power supply circuit of the target subsystem to which the target hardware module belongs to be disconnected so as to enable each multiplexer preset in the power domain of the target subsystem to carry out power-off operation.
Presetting a subsystem power-off triggering condition, for example, presetting the power-off operation when the subsystem normally runs to a corresponding stage, or presetting the power-off operation when the subsystem normally runs for a preset time interval. When the subsystem power-off triggering condition is met, the whole target subsystem can be powered off currently, so that the power supply circuit of the target subsystem is controlled to be switched off, and each multiplexer preset in a power supply domain of the target subsystem is powered off.
Corresponding to the above method embodiments, the present invention further provides a device for testing a hardware module in a chip, and the device for testing a hardware module in a chip described below and the method for testing a hardware module in a chip described above may be referred to correspondingly.
Referring to fig. 6, fig. 6 is a block diagram of a testing apparatus for a hardware module in a chip according to an embodiment of the present invention, where the testing apparatus may include:
a request analysis unit 61, configured to analyze the received chip test request to obtain a target hardware module to be tested and a target signal bit;
a signal bit selecting unit 62, configured to switch the ground signal bit in each multiplexer originally selected by default by the control register to each target signal bit selected by the chip test request;
and a module test unit 63, configured to perform a test operation on the target hardware module by using each target signal bit.
The testing device of the hardware module in the chip provided by the invention analyzes the received chip testing request to obtain a target hardware module to be tested and a target signal position; switching the ground signal bits in each multi-path selector originally selected by default by the control register into each target signal bit selected by the chip test request; and testing the target hardware module by using each target signal bit. By presetting the grounding signal positions in each multiplexer selected by default by the control register when the chip test is not needed, when the hardware module test is not needed, signal jumping does not exist, charging and discharging caused by signal jumping does not exist, and the power consumption of the chip is reduced.
In a specific embodiment of the present invention, the signal bit selecting unit 62 is specifically a unit that switches the ground signal bit in each multiplexer corresponding to the target hardware module originally selected by default by the control register to the target signal bit selected by the chip test request.
In one embodiment of the present invention, the apparatus may further include:
and the first power supply control unit is used for controlling the power supply circuit of the target hardware module to be switched off when the power-off triggering condition of the hardware module is reached after the target hardware module is tested by utilizing each target signal bit, so that each multiplexer preset in the power domain of the target hardware module is subjected to power-off operation.
In one embodiment of the present invention, the method further comprises:
and the second power supply control unit is used for controlling the power supply circuit of the target subsystem to be disconnected when a subsystem power-off triggering condition is reached after the target hardware module is tested by using each target signal bit, so that each multiplexer preset in the power domain of the target subsystem is powered off.
In one embodiment of the present invention, the apparatus may further include:
the signal bit number counting unit is used for switching the grounding signal bits in each multi-channel selector originally selected by default in the control register to the target signal bits selected by the chip test request after the target hardware module to be tested and the target signal bits are obtained, and counting the target number of each target signal bit;
the signal connection number counting unit is used for respectively acquiring the number of signal connections between the target hardware module and each multiplexer;
the second judgment unit is used for judging whether the number of the signal connections smaller than the target number exists or not;
the target multiplexer determining unit is used for determining the multiplexers with the signal connection number smaller than the target number as the target multiplexers when the signal connection number smaller than the target number is determined to exist;
and the connection bus extension unit is used for carrying out extension operation on the connection bus between the target multiplexer and the target hardware module.
Corresponding to the above method embodiment, referring to fig. 7, fig. 7 is a schematic diagram of a testing apparatus for a hardware module in a chip provided by the present invention, where the apparatus may include:
a memory 332 for storing a computer program;
the processor 322 is configured to implement the steps of the method for testing the hardware module in the chip of the above-described method embodiment when executing the computer program.
Specifically, referring to fig. 8, fig. 8 is a schematic diagram illustrating a specific structure of a testing apparatus for a hardware module in a chip according to the present embodiment, the testing apparatus for the hardware module in the chip may generate a relatively large difference due to different configurations or performances, and may include one or more processors (CPUs) 322 (e.g., one or more processors) and a memory 332, where the memory 332 stores one or more computer applications 342 or data 344. Memory 332 may be, among other things, transient or persistent storage. The program stored in memory 332 may include one or more modules (not shown), each of which may include a sequence of instructions operating on a data processing device. Still further, the central processor 322 may be configured to communicate with the memory 332 to execute a series of instruction operations in the memory 332 on the test equipment 301 for the hardware-in-chip module.
The test equipment 301 for the on-chip hardware modules may also include one or more power supplies 326, one or more wired or wireless network interfaces 350, one or more input-output interfaces 358, and/or one or more operating systems 341.
The steps in the above described method for testing a hardware module in a chip may be implemented by the structure of the test equipment for the hardware module in the chip.
Corresponding to the above method embodiment, the present invention further provides a computer-readable storage medium having a computer program stored thereon, the computer program, when executed by a processor, implementing the steps of:
analyzing the received chip test request to obtain a target hardware module to be tested and a target signal position; switching the ground signal bits in each multi-path selector originally selected by default by the control register into each target signal bit selected by the chip test request; and testing the target hardware module by using each target signal bit.
The computer-readable storage medium may include: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
For the introduction of the computer-readable storage medium provided by the present invention, please refer to the above method embodiments, which are not described herein again.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device, the apparatus and the computer-readable storage medium disclosed in the embodiments correspond to the method disclosed in the embodiments, so that the description is simple, and the relevant points can be referred to the description of the method.
The principle and the implementation of the present invention are explained in the present application by using specific examples, and the above description of the embodiments is only used to help understanding the technical solution and the core idea of the present invention. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
Claims (10)
1. A method for testing a hardware module in a chip is characterized by comprising the following steps:
analyzing the received chip test request to obtain a target hardware module to be tested and a target signal position;
switching the ground signal bits in each multiplexer originally selected by default by the control register to the target signal bits selected by the chip test request;
and testing the target hardware module by using each target signal bit.
2. The method according to claim 1, wherein switching the ground signal bits in each multiplexer originally selected by default in the control register to the target signal bits selected by the chip test request comprises:
and switching the grounding signal bits in each multiplexer corresponding to the target hardware module originally selected by default by the control register into the target signal bits selected by the chip test request.
3. The method for testing hardware modules in a chip according to claim 2, wherein after the testing operation of the target hardware module is performed by using each target bit, the method further comprises:
and when the hardware module power-off triggering condition is reached, controlling the power supply circuit of the target hardware module to be switched off so as to enable each multiplexer preset in the power supply domain of the target hardware module to carry out power-off operation.
4. The method for testing hardware modules in a chip according to claim 2, wherein after the testing operation of the target hardware module is performed by using each target bit, the method further comprises:
and when a subsystem power-off triggering condition is met, controlling a power supply circuit of a target subsystem to which the target hardware module belongs to be switched off so as to enable each multiplexer preset in a power supply domain of the target subsystem to carry out power-off operation.
5. The method for testing a hardware module in a chip according to any one of claims 1 to 4, wherein after obtaining the target hardware module to be tested and the target signal bit, switching the ground signal bit in each multiplexer originally selected by default in the control register to be before each target signal bit selected by the chip test request, further comprising:
counting the target number of each target signal bit;
respectively acquiring the number of signal connections between the target hardware module and each multiplexer;
judging whether the number of signal connections smaller than the target number exists or not;
if so, determining the multi-path selectors with the number of signal connections with the target hardware module smaller than the target number as target multi-path selectors;
and carrying out expansion operation on a connection bus between the target multiplexer and the target hardware module.
6. A device for testing a hardware module in a chip, comprising:
the request analysis unit is used for analyzing the received chip test request to obtain a target hardware module to be tested and a target signal position;
a signal bit selection unit, configured to switch a ground signal bit in each multiplexer originally selected by default in the control register to each target signal bit selected by the chip test request;
and the module test unit is used for testing the target hardware module by utilizing each target signal bit.
7. The apparatus for testing hardware modules on a chip according to claim 6, wherein the signal bit selection unit is specifically a unit for switching a ground signal bit in each multiplexer corresponding to the target hardware module originally selected by default by the control register to each target signal bit selected by the chip test request.
8. The apparatus for testing hardware modules on a chip of claim 7, further comprising:
and the first power supply control unit is used for controlling the power supply circuit of the target hardware module to be switched off when a hardware module power-off triggering condition is reached after the target hardware module is tested by using each target signal bit, so that each multiplexer preset in a power supply domain of the target hardware module is subjected to power-off operation.
9. A device for testing hardware modules in a chip, comprising:
a memory for storing a computer program;
processor for implementing the steps of the method for testing a hardware module in a chip according to any one of claims 1 to 5 when executing said computer program.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method for testing a hardware module in a chip according to any one of claims 1 to 5.
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| CN113297020B (en) | 2023-02-28 |
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