CN114461579A - Processing method and system for parallel reading and dynamic scheduling of Pattern file and ATE (automatic test equipment) - Google Patents
Processing method and system for parallel reading and dynamic scheduling of Pattern file and ATE (automatic test equipment) Download PDFInfo
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Abstract
The invention provides a processing method, a system and ATE equipment for Pattern file parallel reading and dynamic scheduling, wherein the method comprises the following steps: the vector parsing unit provides a first control instruction. A Pattern reading unit reads a first vector corresponding to a vector address; analyzing to obtain a first vector analysis result; obtaining a test result of a first vector in a chip to be tested, and judging whether a branch exists when the first vector is executed; and if the branch exists, obtaining a second vector analysis result. And the waveform sending module selects the first vector analysis result or the second vector analysis result according to the test result and sends the corresponding waveform to the chip to be tested. The scheme of the invention can realize the parallel reading and dynamic scheduling of the vector, the reading and the analysis of the vector are both provided with two paths, and when the vector execution has branches due to different test results, the vector of the other branch can be read in advance; and obtaining a test result, and directly selecting a vector analysis result of a corresponding branch according to the test result to output a waveform.
Description
Technical Field
The invention relates to the field of semiconductor chip testing, in particular to a processing method and a processing system for parallel reading and dynamic scheduling of Pattern files and ATE (automatic test equipment).
Background
Ate (automatic Test equipment) is an automatic Test device, which is an aggregate of high-performance computer-controlled Test instruments, and is a Test system composed of a tester and a computer, and the computer controls Test hardware by running instructions of a Test program. The semiconductor ATE is used for detecting the integrity of the function and performance of an integrated circuit, is an important device for ensuring the quality of the integrated circuit in the production and manufacturing process of the integrated circuit, and generally performs four processes of test program design, program compiling, vector loading and test execution on the integrated circuit.
In the vector loading process, when the execution of the vector in the Pattern file has branches according to different test results, and the vector corresponding to the selected branch is not read out from the memory, a very high delay exists in the process from the reading out of the corresponding vector of the Pattern file from the memory to the emission of the waveform, and the test effect and the test efficiency of the ATE equipment on the chip are seriously influenced.
Therefore, a scheme for reasonably scheduling the Pattern file is urgently needed to solve the problem.
Disclosure of Invention
In view of this, the present invention provides a processing method, a processing system and ATE equipment for parallel reading and dynamic scheduling of Pattern files, and the specific scheme is as follows:
a processing method for parallel reading and dynamic scheduling of Pattern files comprises the following steps:
storing a Pattern file to be processed in a preset memory unit;
the preset vector analysis unit provides a first control instruction related to memory reading to a preset Pattern reading unit according to the configured vector address;
based on the first control instruction, the Pattern reading unit reads a first vector corresponding to the vector address in the Pattern file from the memory unit and sends the first vector to the vector analyzing unit;
the vector analyzing unit analyzes the first vector to obtain a first vector analyzing result;
the vector analysis unit obtains a test result of the first vector in a chip to be tested and judges whether a branch exists when the first vector is executed;
if a branch is present:
providing a second control instruction related to memory reading to the Pattern reading unit according to the branch address, and acquiring a second vector corresponding to the branch address to the vector analysis unit, wherein the vector analysis unit analyzes the second vector to obtain a second vector analysis result;
and the preset waveform sending module selects a first vector analysis result or a second vector analysis result according to the test result and sends a corresponding waveform to the chip to be tested.
In a specific embodiment, the processing method further includes:
if no branch is present:
the waveform sending module sends a waveform corresponding to the first vector analysis result to the chip to be tested;
and sequentially executing the vectors in the Pattern file.
In a specific embodiment, the vector parsing unit is configured with a first processing sub-module and a second processing sub-module, and the Pattern reading unit is configured with a first cache sub-module and a second cache sub-module, where the processing method specifically includes:
the first processing submodule provides a first control instruction related to memory reading to the first cache submodule according to the configured vector address;
the first cache submodule reads a vector corresponding to the vector address in the Pattern file from the memory unit according to the first control instruction, and sends the read vector serving as a first vector to the first processing submodule;
the first processing sub-module analyzes the first vector to obtain a first vector analysis result;
the first processing submodule obtains the test result of the first vector in the chip to be tested and judges whether a branch exists when the first vector is executed:
if a branch is present:
acquiring a branch address corresponding to a branch, and sending the branch address to the second processing submodule by the first processing submodule; the second processing submodule provides a second control instruction related to memory reading to the second cache submodule according to the branch address;
the second cache submodule reads a vector corresponding to the branch address in the Pattern file from the memory unit according to the second control instruction, and sends the read vector serving as a second vector to a preset second processing submodule;
and the second processing submodule analyzes the second vector to obtain a second vector analysis result.
In a specific embodiment, the waveform sending unit is configured with a branch selection sub-module and an interface sub-module, and the processing method specifically includes:
if the branch exists, the branch selection submodule selects the first vector analysis result or the second vector analysis result according to the test result and provides the first vector analysis result or the second vector analysis result to the interface submodule, and the interface submodule outputs a waveform corresponding to the vector analysis result selected by the branch selection submodule to the chip to be tested;
if no branch exists, the branch selection submodule selects the first vector analysis result and provides the first vector analysis result to the interface submodule, and the interface submodule outputs a waveform corresponding to the first vector analysis result to the chip to be tested.
In a specific embodiment, if a second vector analysis result of the second processing submodule is selected, the first cache submodule and the first processing submodule are reset, and the branch selection submodule provides the second vector analysis result to the interface submodule for output;
if the first vector analysis result of the first processing submodule is selected, the second cache submodule and the second processing submodule are reset, and the branch selection submodule provides the first vector analysis result for the interface submodule to output.
In a specific embodiment, the obtaining process of the test result includes:
sending the waveform corresponding to the first vector to a chip to be tested;
the chip to be tested feeds back a corresponding waveform signal according to the waveform;
and acquiring the waveform signal output by the chip to be tested through the interface submodule, and analyzing a corresponding test result according to the signal by the vector analysis unit.
A processing system for parallel reading and dynamic scheduling of Pattern files comprises:
the memory unit is used for storing a Pattern file to be processed;
the Pattern processing unit is used for performing vector reading and vector analysis on the Pattern file in the memory unit; obtaining the test result of a certain vector in the chip to be tested, and judging whether a branch exists when the vector is executed;
the Pattern processing unit specifically comprises:
the Pattern reading module is used for reading a first vector in the Pattern file from the memory unit according to a first control instruction and reading a second vector in the Pattern file from the memory unit according to a second control instruction;
the vector analysis module is used for providing a first control instruction related to memory reading for the Pattern reading module according to a vector address, providing a second control instruction related to memory reading for the Pattern reading module according to a branch address, and carrying out vector analysis on the read first vector and the read second vector;
and the waveform sending module is used for selecting the vector analysis result of the first vector or the vector analysis result of the second vector and outputting a corresponding waveform to the chip to be tested according to the vector analysis result.
In a specific embodiment, the vector parsing unit is configured with a first processing sub-module and a second processing sub-module, and the Pattern reading unit is configured with a first cache sub-module and a second cache sub-module;
the first processing submodule is used for providing a first control instruction related to memory reading to the first cache submodule according to the configured vector address;
the first cache submodule is configured to read a vector corresponding to the vector address in the Pattern file from the memory unit according to the first control instruction, and send the read vector to the first processing submodule as a first vector; if the branch exists, a branch address is sent to the second processing submodule;
the second processing submodule is used for providing a second control instruction related to memory reading to the second cache submodule according to the branch address;
the second cache submodule is configured to read a vector corresponding to the branch address in the Pattern file from the memory unit according to the second control instruction, and send the read vector to a preset second processing submodule as a second vector;
and the second processing submodule is used for analyzing the second vector to obtain a second vector analysis result.
In a specific embodiment, the waveform sending unit is configured with a branch selection sub-module and an interface sub-module;
the branch selection submodule is used for selecting the first vector analysis result or the second vector analysis result according to the test result and providing the first vector analysis result or the second vector analysis result to the interface submodule when a branch exists; when no branch exists, selecting the first vector analysis result and providing the first vector analysis result to the interface sub-module;
and the interface submodule is used for outputting a waveform corresponding to the vector analysis result selected by the branch selection submodule to the chip to be tested.
An ATE device comprises a main control board, a back board and a service board, wherein the main control board establishes communication connection with the service board through the back board, and the service board is connected with a chip to be tested;
a digital-to-analog conversion circuit and the processing system for parallel reading and dynamic scheduling of the Pattern file as claimed in any one of claims 7 to 9 are configured on the service board;
the digital-to-analog conversion circuit is connected with the waveform sending module and the chip to be tested, and is used for performing digital-to-analog conversion on the waveform output by the waveform sending module to obtain an analog signal and sending the analog signal to the chip to be tested.
Has the advantages that:
the invention provides a processing method and a processing system for parallel reading and dynamic scheduling of a Pattern file and ATE (automatic test equipment), which solve the problem that vector execution has branches due to different possible test results in the process of loading the Pattern file to sending out a waveform, and can realize parallel reading and dynamic scheduling of vectors. Reading and analyzing vector data in the Pattern file are provided with two paths, and when different test results cause that the vector execution has branches, the vector data of the other branch can be read in advance; when the test result is obtained, the vector analysis result of the corresponding branch can be directly selected according to the test result, and then the corresponding waveform is output. The processing method of the embodiment reduces the reading time and the analysis time of the vector with the branch, and can realize quick reading and analysis no matter whether the branch exists in the vector execution, thereby solving the problem of higher delay of the Pattern file from loading to waveform sending.
Drawings
FIG. 1 is a schematic flow chart of a processing method according to an embodiment of the present invention;
FIG. 2 is a block diagram of a processing system according to an embodiment of the present invention;
FIG. 3 is a block diagram of an ATE device according to an embodiment of the present invention.
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Reference numerals: 1-a memory cell; 2-Pattern processing unit; 3, a main control board; 4-a back plate; 5-a service board; 6-a digital-to-analog conversion circuit; 21-Pattern reading module; 22-a vector parsing module; 23-a waveform transmission module; 211-a first cache submodule; 212-a second cache submodule; 221-a first processing sub-module; 222-a second processing sub-module; 231-branch selection submodule; 232-interface sub-module.
Detailed Description
Hereinafter, various embodiments of the present disclosure will be described more fully. The present disclosure is capable of various embodiments and of modifications and variations therein. However, it should be understood that: there is no intention to limit the various embodiments of the disclosure to the specific embodiments disclosed herein, but rather, the disclosure is to cover all modifications, equivalents, and/or alternatives falling within the spirit and scope of the various embodiments of the disclosure.
The terminology used in the various embodiments of the disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the various embodiments of the disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the disclosed invention belong. Terms (such as those defined in commonly used dictionaries) will be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments of the present disclosure.
Example 1
The embodiment 1 of the invention discloses a processing method for parallel reading and dynamic scheduling of Pattern files, which reduces time delay by performing parallel reading and dynamic scheduling on the Pattern files. The processing method flow block diagram is shown in the attached figure 1, and the specific scheme is as follows:
a processing method for parallel reading and dynamic scheduling of Pattern files is applied to a system comprising a memory unit and a Pattern processing unit, and the structure of the system is shown in figure 2 of the specification. The Pattern processing unit comprises a Pattern reading module, a vector analyzing module and a waveform sending module. The Pattern file, a logic function file expressed by a truth table, is composed of a plurality of lines of vectors. Vectors, describe the logic input output states expected by the test device design.
The flow of the treatment method is shown in the attached figure 1 of the specification, and the treatment method comprises the following steps:
101. storing a Pattern file to be processed in a preset memory unit;
102. the preset vector analysis unit provides a first control instruction related to memory reading to a preset Pattern reading unit according to the configured vector address;
103. based on the first control instruction, the Pattern reading unit reads a first vector corresponding to the vector address in the Pattern file from the memory unit and sends the first vector to the vector analysis unit;
104. the vector analyzing unit analyzes the first vector to obtain a first vector analyzing result;
105. the vector analysis unit obtains a test result of the first vector in the chip to be tested and judges whether a branch exists when the first vector is executed;
106. if a branch is present:
providing a second control instruction related to memory reading to the Pattern reading unit according to the branch address, obtaining a second vector corresponding to the branch address to the vector analyzing unit, and analyzing the second vector by the vector analyzing unit to obtain a second vector analyzing result;
and the waveform sending module selects the first vector analysis result or the second vector analysis result according to the test result and sends the corresponding waveform to the chip to be tested.
107. If no branch is present: a preset waveform sending module sends a waveform corresponding to the first vector analysis result to a chip to be tested; the vectors in the Pattern file are executed in order.
The embodiment provides a processing method for a Pattern file, which can realize parallel reading and dynamic scheduling, aiming at the problem that branches exist in vector execution due to different possible test results in the process of loading the Pattern file to the waveform sending. Reading and analyzing vector data in the Pattern file are provided with two paths, and when the vector execution has branches due to different test results, the vector data of the other branch can be read in advance; when the test result is obtained, the vector analysis result of the corresponding branch can be directly selected according to the test result, and then the corresponding waveform is output.
Specifically, in this embodiment, two paths are provided for vector reading and vector parsing in a Pattern file, and the embodiment in a hardware facility is as follows: the vector analysis unit is provided with a first processing submodule and a second processing submodule, and the Pattern reading unit is provided with a first cache submodule and a second cache submodule.
Step 102 specifically includes: the first processing submodule provides a first control instruction related to memory reading to the first cache submodule according to the configured vector address. The vector address determines the vector data that reads a specific location in the Pattern file. The vector addresses may be preconfigured or may be obtained from test instructions. The first control instruction is specially used for controlling the Pattern reading unit to read the vector, and comprises the address, the time and other related parameters of the vector to be read.
Step 103 specifically comprises: and the first cache submodule reads a vector corresponding to the vector address in the Pattern file from the memory unit according to the first control instruction, and sends the read vector serving as the first vector to the first processing submodule. In this embodiment, the first cache submodule and the first processing submodule constitute a single path, the first cache is responsible for reading the vector, and the first processing submodule is responsible for sending the instruction and analyzing the vector.
Step 104 specifically includes: the first processing submodule analyzes the first vector to obtain a first vector analysis result. When a certain vector is executed and no branch exists, the waveform corresponding to the first analysis result is the output waveform. In the present embodiment, the vector analysis result is a specific analysis of the test vector, and relates to various types of detailed information of the test vector, such as a level state, an instruction parameter, and the like. The vector is analyzed to confirm what the waveform to be sent by the Pattern processing unit is
Step 105 specifically includes: the first processing submodule obtains a test result of the first vector in the chip to be tested and judges whether a branch exists when the first vector is executed. The process of obtaining the test result specifically includes: sending the waveform corresponding to the first vector to a chip to be tested; the chip to be tested feeds back a corresponding waveform signal according to the waveform; the waveform signal output by the chip to be tested is collected through the interface submodule, and the vector analysis unit analyzes a corresponding test result according to the signal. The test results are determined by the specific chip. For example, after sending a waveform to a chip to be tested, the chip to be tested may enter a certain mode, in which the chip to be tested may output a fixed level or waveform, and feedback of the chip may be obtained by collecting the level or waveform output by the chip to be tested. The Pattern processing unit sends the waveform to the chip to be tested, the chip to be tested outputs a corresponding feedback signal according to the received signal, and the Pattern processing unit obtains different test results according to the feedback signal, so that the quality of the chip is judged.
Step 105 specifically includes: if a branch is present:
10501. acquiring a branch address corresponding to the branch, and sending the branch address to the second processing submodule by the first processing submodule; the second processing submodule provides a second control instruction related to the memory reading to the second cache submodule according to the branch address;
10502. the second cache submodule reads a vector corresponding to the branch address in the Pattern file from the memory unit according to a second control instruction, and sends the read vector serving as a second vector to a preset second processing submodule;
10503. and the second processing submodule analyzes the second vector to obtain a second vector analysis result.
If a branch exists, vector information corresponding to the branch needs to be acquired. In practical application, the absence of a branch can be simply understood as that the vector is executed completely, and other vectors in the Pattern file are executed sequentially after the vector is executed without the participation of other vectors. While a branch means that other vector parameters are needed, taking jump as an example, the branch address is the specific address of the jump variable. When the branch exists, another path of vector reading and vector analysis is started, namely the second cache submodule and the second processing submodule. The operation flow of the second cache submodule and the second processing submodule is similar to that of the first cache submodule and the first processing submodule.
The second control instruction comprises related parameters such as a branch address, reading time and the like, and the second vector and the first vector are vector data in a Pattern file. The second vector analysis result is obtained by analyzing the second vector, and the first vector analysis result is obtained by analyzing the first vector. When a branch exists, the first vector analysis result and the second vector analysis result exist at the same time, and at this time, the branch needs to be selected.
In the present embodiment, the waveform transmission unit is configured with a branch selection submodule and an interface submodule.
If the branch exists, the branch selection submodule selects a first vector analysis result or a second vector analysis result according to the test result and provides the first vector analysis result or the second vector analysis result to the interface submodule, and the interface submodule outputs a corresponding waveform to the chip to be tested;
if no branch exists, the branch selection submodule selects a first vector analysis result and provides the first vector analysis result to the interface submodule, and the interface submodule outputs a waveform corresponding to the first vector analysis result to the chip to be tested.
If the second vector analysis result of the second processing submodule is selected, the first cache submodule and the first processing submodule are reset, and the branch selection submodule provides the second vector analysis result for the interface submodule to output;
if the first vector analysis result of the first processing submodule is selected, the second cache submodule and the second processing submodule are reset, and the branch selection submodule provides the first vector analysis result for the interface submodule to output.
The embodiment provides a processing method for parallel reading and dynamic scheduling of a Pattern file, which can realize parallel reading and dynamic scheduling of vectors, aiming at the problem that branches exist in vector execution due to different possible test results in the process of loading the Pattern file to a waveform sending process. Reading and analyzing vector data in the Pattern file are provided with two paths, and when different test results cause that the vector execution has branches, the vector data of the other branch can be read in advance; when the test result is obtained, the vector analysis result of the corresponding branch can be directly selected according to the test result, and then the corresponding waveform is output. The processing method of the embodiment reduces the reading time and the analysis time of the vector with the branch, can realize quick reading and analysis no matter whether the branch exists in the vector execution, and solves the problem that the delay of the Pattern file is high in the process from loading to waveform sending.
Example 2
The embodiment 2 of the invention discloses a processing system for parallel reading and dynamic scheduling of a Pattern file, the processing method for parallel reading and dynamic scheduling of the Pattern file of the embodiment 1 is systematized, the specific structure of the system is shown as the attached figure 2 in the specification, and the specific scheme is as follows:
a processing system for parallel reading and dynamic scheduling of Pattern files comprises:
the memory unit 1 is used for storing Pattern files;
the Pattern processing unit 2 is used for performing vector reading and vector analysis on the Pattern file in the memory unit; obtaining the test result of a certain vector in the chip to be tested, and judging whether a branch exists when the vector is executed;
the Pattern processing unit 2 specifically includes:
the Pattern reading module 21 is used for reading the vectors in the Pattern file from the memory unit in parallel;
the vector analysis module 22 is configured to provide a first control instruction related to memory reading for the Pattern reading module according to the vector address, provide a second control instruction related to memory reading for the Pattern reading module according to the branch address, and analyze the read first vector and the read second vector;
and the waveform sending module 23 is configured to select a vector analysis result of the first vector or a vector analysis result of the second vector, and output a corresponding waveform to the chip to be tested according to the vector analysis result.
The vector parsing unit 22 is configured with a first processing submodule 221 and a second processing submodule 222, and the Pattern reading unit 21 is configured with a first cache submodule 211 and a second cache submodule 212;
the first processing submodule 221 is configured to provide a first control instruction related to memory reading to the first cache submodule according to the configured vector address;
the first cache submodule 211 is configured to read a vector corresponding to a vector address in a Pattern file from the memory unit according to the first control instruction, and send the read vector to the first processing submodule 221 as a first vector; if there is a branch, send the branch address to the second processing submodule 222;
a second processing submodule 222, configured to provide a second control instruction related to memory read to the second cache submodule 212 according to the branch address; and analyzing the second vector to obtain a second vector analysis result.
The second cache submodule 212 is configured to read a vector corresponding to the branch address in the Pattern file from the memory unit according to the second control instruction, and send the read vector to the preset second processing submodule 222 as a second vector;
wherein, the waveform sending unit is configured with a branch selection submodule 231 and an interface submodule 232;
the branch selection submodule 231 is configured to select a first vector analysis result or a second vector analysis result according to the test result when a branch exists, and provide the first vector analysis result or the second vector analysis result to the interface submodule 232; when no branch exists, a first vector analysis result is selected and provided to the interface sub-module 232;
and an interface sub-module 232, configured to output a waveform corresponding to the vector analysis result selected by the branch selection sub-module 231 to the chip to be tested.
The embodiment discloses a processing system for parallel reading and dynamic scheduling of Pattern files, and the acceleration method of the embodiment 1 is systematized to be more practical.
Example 3
This embodiment proposes an ATE device, and the ATE device is provided with the processing system for parallel reading and dynamic scheduling of Pattern files proposed in embodiment 2. The hardware structure of the ATE device is shown in fig. 3 in the specification, and the specific scheme is as follows:
an ATE device comprises a main control board 3, a back board 4 and a service board 5, wherein the main control board 3 establishes communication connection with the service board 5 through the back board 4, and the service board 5 is connected with a chip to be tested;
the service board 5 is provided with a digital-to-analog conversion circuit 6 and the processing system of the embodiment 2;
the digital-to-analog conversion circuit 6 is connected to the waveform sending module 23 and the chip to be tested, and is configured to perform digital-to-analog conversion on the waveform output by the waveform sending module 23 to obtain an analog signal, and send the analog signal to the chip to be tested. Specifically, the digital-to-analog conversion circuit is connected to the interface sub-module 232 and the chip to be tested. The specific structure of the ATE equipment is shown in fig. 3 of the specification.
The processing system of embodiment 2, in practical application, belongs to a dio (digital io) functional module; the sent waveform is a digital signal, needs to be subjected to digital-to-analog conversion by a digital-to-analog conversion circuit to obtain an analog signal, and then is output to a chip to be tested.
The embodiment provides ATE equipment, and the processing system for parallel reading and dynamic scheduling of a Pattern file, which is provided in embodiment 2, is applied to specific equipment, so that reading and analysis of the Pattern file can be optimized, and the problem of delay of the Pattern file from loading to waveform emission is solved.
The invention provides a processing method and a processing system for parallel reading and dynamic scheduling of a Pattern file and ATE (automatic test equipment), which solve the problem that vector execution has branches due to different possible test results in the process of loading the Pattern file to sending out a waveform, and can realize parallel reading and dynamic scheduling of vectors. Reading and analyzing vector data in the Pattern file are provided with two paths, and when different test results cause that the vector execution has branches, the vector data of the other branch can be read in advance; when the test result is obtained, the vector analysis result of the corresponding branch can be directly selected according to the test result, and then the corresponding waveform is output. The processing method of the embodiment reduces the reading time and the analysis time of the vector with the branch, and can realize quick reading and analysis no matter whether the branch exists in the vector execution, thereby solving the problem of higher delay of the Pattern file from loading to waveform sending.
Those skilled in the art will appreciate that the figures are merely schematic representations of one preferred implementation scenario and that the blocks or flow diagrams in the figures are not necessarily required to practice the present invention. Those skilled in the art will appreciate that the modules in the devices in the implementation scenario may be distributed in the devices in the implementation scenario according to the description of the implementation scenario, or may be located in one or more devices different from the present implementation scenario with corresponding changes. The modules of the implementation scenario may be combined into one module, or may be further split into a plurality of sub-modules. The above-mentioned serial numbers of the present invention are merely for description and do not represent the advantages and disadvantages of the implementation scenarios. The above disclosure is only a few specific implementation scenarios of the present invention, however, the present invention is not limited thereto, and any variations that can be made by those skilled in the art are intended to fall within the scope of the present invention.
Claims (10)
1. A processing method for parallel reading and dynamic scheduling of Pattern files is characterized by comprising the following steps:
storing a Pattern file to be processed in a preset memory unit;
the preset vector analysis unit provides a first control instruction related to memory reading to a preset Pattern reading unit according to the configured vector address;
based on the first control instruction, the Pattern reading unit reads a first vector corresponding to the vector address in the Pattern file from the memory unit, and sends the first vector to the vector analysis unit;
the vector analyzing unit analyzes the first vector to obtain a first vector analyzing result;
the vector analysis unit obtains a test result of the first vector in a chip to be tested and judges whether a branch exists when the first vector is executed;
if a branch is present:
providing a second control instruction related to memory reading to the Pattern reading unit according to the branch address, and acquiring a second vector corresponding to the branch address to the vector analysis unit, wherein the vector analysis unit analyzes the second vector to obtain a second vector analysis result;
and the preset waveform sending module selects a first vector analysis result or a second vector analysis result according to the test result and sends a corresponding waveform to the chip to be tested.
2. The processing method according to claim 1, characterized in that it further comprises:
if no branch is present:
the waveform sending module sends a waveform corresponding to the first vector analysis result to the chip to be tested;
and sequentially executing the vectors in the Pattern file.
3. The processing method according to claim 2, wherein the vector parsing unit is configured with a first processing sub-module and a second processing sub-module, and the Pattern reading unit is configured with a first cache sub-module and a second cache sub-module, and the processing method specifically includes:
the first processing submodule provides a first control instruction related to memory reading to the first cache submodule according to the configured vector address;
the first cache submodule reads a vector corresponding to the vector address in the Pattern file from the memory unit according to the first control instruction, and sends the read vector serving as a first vector to the first processing submodule;
the first processing submodule analyzes the first vector to obtain a first vector analysis result;
the first processing submodule obtains the test result of the first vector in the chip to be tested and judges whether a branch exists when the first vector is executed:
if a branch is present:
acquiring a branch address corresponding to a branch, and sending the branch address to the second processing submodule by the first processing submodule; the second processing submodule provides a second control instruction related to memory reading to the second cache submodule according to the branch address;
the second cache submodule reads a vector corresponding to the branch address in the Pattern file from the memory unit according to the second control instruction, and sends the read vector serving as a second vector to a preset second processing submodule;
and the second processing submodule analyzes the second vector to obtain a second vector analysis result.
4. The processing method according to claim 3, wherein the waveform sending unit is configured with a branch selection submodule and an interface submodule, and the processing method specifically includes:
if the branch exists, the branch selection submodule selects the first vector analysis result or the second vector analysis result according to the test result and provides the first vector analysis result or the second vector analysis result to the interface submodule, and the interface submodule outputs a waveform corresponding to the vector analysis result selected by the branch selection submodule to the chip to be tested;
if no branch exists, the branch selection submodule selects the first vector analysis result and provides the first vector analysis result to the interface submodule, and the interface submodule outputs a waveform corresponding to the first vector analysis result to the chip to be tested.
5. The processing method according to claim 4, wherein if a second vector resolution result of the second processing submodule is selected, the first cache submodule and the first processing submodule are reset, and the branch selection submodule provides the second vector resolution result to the interface submodule for output;
if the first vector analysis result of the first processing submodule is selected, the second cache submodule and the second processing submodule are reset, and the branch selection submodule provides the first vector analysis result for the interface submodule to output.
6. The processing method according to claim 4, wherein the obtaining of the test result comprises:
sending the waveform corresponding to the first vector to a chip to be tested;
the chip to be tested feeds back a corresponding waveform signal according to the waveform;
and acquiring the waveform signal output by the chip to be tested through the interface submodule, and analyzing a corresponding test result according to the signal by the vector analysis unit.
7. A processing system for parallel reading and dynamic scheduling of Pattern files is characterized by comprising:
the memory unit is used for storing a Pattern file to be processed;
the Pattern processing unit is used for performing vector reading and vector analysis on the Pattern file in the memory unit; obtaining the test result of a certain vector in the chip to be tested, and judging whether a branch exists when the vector is executed;
the Pattern processing unit specifically comprises:
the Pattern reading module is used for reading a first vector in the Pattern file from the memory unit according to a first control instruction and reading a second vector in the Pattern file from the memory unit according to a second control instruction;
the vector analysis module is used for providing a first control instruction related to memory reading for the Pattern reading module according to a vector address, providing a second control instruction related to memory reading for the Pattern reading module according to a branch address, and carrying out vector analysis on the read first vector and the read second vector;
and the waveform sending module is used for selecting the vector analysis result of the first vector or the vector analysis result of the second vector and outputting a corresponding waveform to the chip to be tested according to the vector analysis result.
8. The processing system according to claim 7, wherein the vector parsing unit is configured with a first processing sub-module and a second processing sub-module, and the Pattern reading unit is configured with a first cache sub-module and a second cache sub-module;
the first processing submodule is used for providing a first control instruction related to memory reading to the first cache submodule according to the configured vector address;
the first cache submodule is configured to read a vector corresponding to the vector address in the Pattern file from the memory unit according to the first control instruction, and send the read vector to the first processing submodule as a first vector; if the branch exists, a branch address is sent to the second processing submodule;
the second processing submodule is used for providing a second control instruction related to memory reading to the second cache submodule according to the branch address;
the second cache submodule is configured to read a vector corresponding to the branch address in the Pattern file from the memory unit according to the second control instruction, and send the read vector to a preset second processing submodule as a second vector;
and the second processing submodule is used for analyzing the second vector to obtain a second vector analysis result.
9. The processing system of claim 8, wherein the waveform transmission unit is configured with a branch selection sub-module and an interface sub-module;
the branch selection submodule is used for selecting the first vector analysis result or the second vector analysis result according to the test result and providing the first vector analysis result or the second vector analysis result to the interface submodule when a branch exists; when no branch exists, selecting the first vector analysis result and providing the first vector analysis result to the interface sub-module;
and the interface submodule is used for outputting a waveform corresponding to the vector analysis result selected by the branch selection submodule to the chip to be tested.
10. An ATE device is characterized by comprising a main control board, a back board and a service board, wherein the main control board establishes communication connection with the service board through the back board, and the service board is connected with a chip to be tested;
a digital-to-analog conversion circuit and the processing system for parallel reading and dynamic scheduling of the Pattern file as claimed in any one of claims 7 to 9 are configured on the service board;
the digital-to-analog conversion circuit is connected with the waveform sending module and the chip to be tested, and is used for performing digital-to-analog conversion on the waveform output by the waveform sending module to obtain an analog signal and sending the analog signal to the chip to be tested.
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