CN103150436A - Assistance analysis device for EDA debugging process based on ChipScope - Google Patents
Assistance analysis device for EDA debugging process based on ChipScope Download PDFInfo
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- CN103150436A CN103150436A CN2013100781162A CN201310078116A CN103150436A CN 103150436 A CN103150436 A CN 103150436A CN 2013100781162 A CN2013100781162 A CN 2013100781162A CN 201310078116 A CN201310078116 A CN 201310078116A CN 103150436 A CN103150436 A CN 103150436A
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Abstract
The invention provides an assistance analysis device for an EDA (electronic design automation) debugging process based on ChipScope and relates to an assistance analysis tool for EDA debugging. The assistance analysis device comprises an FPGA (field programmable gate array) testing chip and peripheral auxiliary circuits, wherein the FPGA testing chip is used for loading a testing program in the EDA debugging process; the peripheral auxiliary circuits comprise LED (light-emitting diode) indicator lamps, testing pins, storage chips, configuration chips, dial switches, power supplies and JTAG (joint test action group) interfaces; and the peripheral auxiliary circuits are connected with the FPGA testing chip. With the adoption of the assistance analysis device, real variation situations of signals of the testing pins and testing points in the EDA debugging process can be observed visually, the real physical signals of the tested signal points and the pins can be measured, comparative testing result demonstration can be provided for the EDA debugging, and the precision and efficiency of the EDA testing process are improved greatly.
Description
Technical field
The present invention relates to a kind of EDA debugging assistant analysis instrument, particularly a kind of EDA debug process assistant analysis device based on ChipScope.
Background technology
The abbreviation that EDA(EDA is Electronic Design Automation, be translated into electric design automation) in debug process, often lack good debugging emulation instrument.Existing various EDA simulation analysis instruments and technology are all to simulate realization by the EDA simulation software basically at present, and the simulation analysis that this artificial debugging instrument can provide to the user all is based on software simulation and realizes.In actual debug process, the result of emulation often has relatively large deviation with the result of testing on actual hardware circuit.And, due to the assistant analysis lacked in simulation process the actual test case of objective circuit of EDA design, therefore increased the difficulty of EDA circuit design, and ChipScope(ChipScope is a on-line debugging software) instrument be a kind of be the abbreviation of FPGA(Field-Programmable Gate Array, be field programmable gate array) the assistant adjustment instrument of test chip design, utilize the ChipScope instrument to add virtual test point in FPGA test chip inside, and realize the virtual test to FPGA test chip internal signal.But the test process of ChipScope instrument can only be undertaken by emulation testing software on computers, can only be tested and be shown the detection to the signal intensity situation of FPGA internal port by means of the mode of simulation, lack equally side circuit and test corresponding aid.
Summary of the invention
The technical problem to be solved in the present invention is: provide a kind of EDA debug process assistant analysis device based on ChipScope, to solve the weak point that lacks corresponding hardware assistant analysis device in the EDA debug process.
The technical scheme solved the problems of the technologies described above is: a kind of EDA debug process assistant analysis device based on ChipScope, it is characterized in that: comprise FPGA test chip and peripheral auxiliary circuits, described FPGA test chip is for loading the test procedure of EDA debug process; Described peripheral auxiliary circuits comprises LED light, test pin, storage chip, configuring chip, toggle switch, power module, and each peripheral auxiliary circuits is connected with the FPGA test chip respectively.
Further technical scheme of the present invention is: described FPGA test chip is based on the chip of Xilinx VertexV6-240t, this FPGA test chip is connected with upper strata pc user's terminal by jtag interface, and upper strata pc user's terminal will need the EDA test procedure of debugging to be loaded in the FPGA test chip by jtag interface.
Described each test pin all is connected on the close beta signal wire output port of FPGA test chip, realization transfers to the function on test pin to FPGA close beta point signal, and the close beta signal wire output port of described FPGA test chip is fixed on the I/O port of FPGA test chip.
Described LED light is connected with the close beta signal wire output port of FPGA test chip by hard wired mode, the signal intensity situation that makes LED light indicate the close beta point of FPGA test chip by color and the on and off of lamp.
Described storage chip adopts ATmel 24C512 chip, and the data line of storage chip, address wire, chip slapper route selection, enable line, read and write control line are connected directly to respectively on the I/O port of FPGA test chip
.
The data line of described storage chip adopts the data line with transmitted in both directions function, for by storage chip, pre-stored test procedure is loaded on the FPGA test chip, and the program in FPGA is downloaded in storage chip, to realize that upper strata pc user's terminal is downloaded to the test procedure of FPGA test chip in storage chip by jtag interface, and realize EDA debug process assistant analysis device in the situation that power down still can be preserved the test procedure loaded before.
Described configuring chip is connected with the model selection port with the I/O input/output port of FPGA test chip respectively with toggle switch, to realize jointly being determined by outside toggle switch and configuring chip mode of operation and the running parameter of FPGA test chip.
Owing to adopting said structure, the present invention's the EDA debug process assistant analysis device based on ChipScope compared with prior art, has following beneficial effect:
1. can observe intuitively the signal real change situation of each test pin and test point, and can be measured each tested signaling point and the real physical signalling of pin:
Owing to the present invention includes FPGA test chip and peripheral auxiliary circuits, described FPGA test chip is for loading the test procedure of EDA debug process, described peripheral auxiliary circuits comprises LED light, test pin, storage chip, configuring chip, toggle switch, power module, each peripheral auxiliary circuits is connected with the FPGA test chip respectively, therefore, the emulation testing program that first will include ChipScope, by jtag interface, from pc user's terminal, program is loaded on the FPGA test chip, move afterwards this device, can will be embedded in the signal of each test point in test chip according to the trigger condition set in advance, signal is exported on LED lamp and test pin, dynamically show intuitively in real time the signal on tested pin by the LED lamp on the one hand, on the other hand can be by connecting multimeter above test pin, oscillograph or Digital Logic Analyzer are measured accurately to signal.
Therefore, the present invention can observe the signal real change situation of each test pin and test point in the EDA debug process intuitively, and can be measured each tested signaling point and the real physical signalling of pin, comprise electricity frequency, the isoparametric measurement of electric current.Thereby the present invention can be used as the assistant analysis device in the EDA debug process.
2. can provide for the EDA debugging test result checking of contrast property:
The mode of the software simulator test by ChipScope and the present invention can adopt two kinds of different modes be measured to the test point in chip under test inside or the signal on test pin, and the test result that obtains of two kinds of different modes of contrast and analysis, the test result checking of contrast property can be provided for the EDA debugging.
3. can increase substantially the efficiency of EDA emulation testing:
The present invention can also improve precision and the efficiency of EDA experimental test process, can be more in test process discovery EDA emulation testing early and signal response relation in actual test chip, thereby can increase substantially the efficiency of EDA emulation testing.
Below, in conjunction with the accompanying drawings and embodiments the technical characterictic of the present invention's the EDA debug process assistant analysis device based on ChipScope is further described.
The accompanying drawing explanation
Fig. 1: the structured flowchart of the present invention's the EDA debug process assistant analysis device based on ChipScope;
Fig. 2: the catenation principle figure of storage chip;
Fig. 3: the catenation principle figure of test pin.
In Fig. 3,
The 1-FPGA test chip, 2-test pin, 3-resistance, 4-5V power supply.
Embodiment
Embodiment mono-:
A kind of EDA debug process assistant analysis device (structured flowchart is referring to Fig. 1) based on ChipScope, comprise FPGA test chip and peripheral auxiliary circuits, and described FPGA test chip is for loading the test procedure of EDA debug process; Described peripheral auxiliary circuits comprises LED light, test pin, storage chip, configuring chip, toggle switch, power module and jtag interface, and each peripheral auxiliary circuits is connected with the FPGA test chip respectively, wherein:
Described FPGA test chip is based on the chip of Xilinx VertexV6-240t, this FPGA test chip is connected with upper strata pc user's terminal by jtag interface, and upper strata pc user's terminal will need the EDA test procedure of debugging to be loaded in the FPGA test chip by jtag interface.
Described each test pin all is connected on the close beta signal wire output port of FPGA test chip, realization transfers to the function on test pin to FPGA close beta point signal, and the close beta signal wire output port of described FPGA test chip is fixed on the I/O port of FPGA test chip.
Described LED light is connected with the close beta signal wire output port of FPGA test chip by hard wired mode, the signal intensity situation that makes LED light indicate the close beta point of FPGA test chip by color and the on and off of lamp.
Described storage chip adopts ATmel 24C512 chip, and the data line of storage chip, address wire, chip slapper route selection, enable line, read and write control line are connected directly to respectively on the I/O port of FPGA test chip.
The data line of described storage chip adopts the data line with transmitted in both directions function, be loaded on the FPGA test chip for test procedure that can storage chip is pre-stored, and the program in FPGA can be downloaded in storage chip, realize that upper strata pc user's terminal is downloaded to the test procedure of FPGA test chip in storage chip by jtag interface, power down realizes EDA debug process assistant analysis device in the situation that still can be preserved the test procedure loaded before.
Described configuring chip is connected with the model selection port with the I/O input/output port of FPGA test chip respectively with toggle switch, to realize jointly being determined by outside toggle switch and configuring chip mode of operation and the running parameter of FPGA test chip.
Described power module adopts independently FPGA test chip power supply, and guaranteeing provides reliable and stable power supply for the FPGA test chip course of work.
The performing step of the present invention's the EDA debug process assistant analysis device based on ChipScope is as follows:
1. prepare:
At first according to the composition structure of this device, the design function mainboard, place the blanket socket of FPGA test chip on the function mainboard, the placement location of test chip is provided in actual test process for the user, each functional module such as designing power supply, jtag interface, storage chip, configuring chip and toggle switch and LED light and test pin etc. on the function mainboard afterwards, and connect corresponding components and parts.
Independently FPGA test chip Power Management Design circuit realization for above-mentioned power acquisition, guaranteeing provides reliable and stable power supply for the FPGA test chip course of work.Storage chip adopts the 24C512 chip directly to be connected with the FPGA test chip, and the address wire of storage chip, data line and sheet choosing and read-write control line are connected to respectively on the I/O interface of FPGA test chip.The FPGA test chip in the course of the work, will and read by the rhetorical question to configuring chip and toggle switch coherent signal, obtain this chip work at present configuration parameter.LED light on functional cards and test pin are connected to respectively the close beta signal wire output port of FPGA test chip, this close beta signal wire output port is fixed on above the I/O port of FPGA test chip, can, by the dynamic adjustment to test procedure, all signal wires that are bundled on test pin be connected to any test point of FPGA test chip inside in FPGA test chip inside simultaneously.
2. at first by the user, by jtag interface, from the PC terminal, test procedure is loaded on FPGA test chip or storer, starts afterwards the present invention's the EDA debug process assistant analysis device based on ChipScope.
3. the test procedure that operation loads:
Owing to having embedded ChipScope emulation testing functional module in test procedure, therefore the signal testing point that the FPGA test chip will set in advance according to ChipScope and the trigger condition of signal testing, the signal of correlative measurement pilot is connected on the test pin of EDA debugging assistant analysis device, and according to the peripheral line relation of EDA debug process assistant analysis device to test pin, signal on all test points will transfer to respectively on LED lamp pin and test pin, and the real-time mode by bright light by the electricity frequency value on each test pin shows by LED light, the signal be connected on test pin can be by the user by outside multimeter, oscillograph or Digital Logic Analyzer are measured accurately.
Claims (7)
1. the EDA debug process assistant analysis device based on ChipScope is characterized in that: comprise FPGA test chip and peripheral auxiliary circuits, described FPGA test chip is for loading the test procedure of EDA debug process; Described peripheral auxiliary circuits comprises LED light, test pin, storage chip, configuring chip, toggle switch, power module, and each peripheral auxiliary circuits is connected with the FPGA test chip respectively.
2. the EDA debug process assistant analysis device based on ChipScope according to claim 1, it is characterized in that: described FPGA test chip is based on the chip of Xilinx VertexV6-240t, this FPGA test chip is connected with upper strata pc user's terminal by jtag interface, and upper strata pc user's terminal will need the EDA test procedure of debugging to be loaded in the FPGA test chip by jtag interface.
3. the EDA debug process assistant analysis device based on ChipScope according to claim 1 and 2, it is characterized in that: described each test pin all is connected on the close beta signal wire output port of FPGA test chip, realization transfers to the function on test pin to FPGA close beta point signal, and the close beta signal wire output port of described FPGA test chip is fixed on the I/O port of FPGA test chip.
4. the EDA debug process assistant analysis device based on ChipScope according to claim 3, it is characterized in that: described LED light is connected with the close beta signal wire output port of FPGA test chip by hard wired mode, the signal intensity situation that makes LED light indicate the close beta point of FPGA test chip by color and the on and off of lamp.
5. the EDA debug process assistant analysis device based on ChipScope according to claim 4, it is characterized in that: described storage chip adopts ATmel 24C512 chip, and the data line of storage chip, address wire, chip slapper route selection, enable line, read and write control line are connected directly to respectively on the I/O port of FPGA test chip
.
6. the EDA debug process assistant analysis device based on ChipScope according to claim 5, it is characterized in that: the data line of described storage chip adopts the data line with transmitted in both directions function, for by storage chip, pre-stored test procedure is loaded on the FPGA test chip, and the program in FPGA is downloaded in storage chip, to realize that upper strata pc user's terminal is downloaded to the test procedure of FPGA test chip in storage chip by jtag interface, and realize that EDA debug process assistant analysis device is in the situation that power down, the test procedure loaded before still can preserving.
7. the EDA debug process assistant analysis device based on ChipScope according to claim 6, it is characterized in that: described configuring chip is connected with the model selection port with the I/O input/output port of FPGA test chip respectively with toggle switch, to realize jointly being determined by outside toggle switch and configuring chip mode of operation and the running parameter of FPGA test chip.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104866401A (en) * | 2015-05-29 | 2015-08-26 | 福州瑞芯微电子有限公司 | Method and apparatus for obtaining on-chip signal |
| CN107589368A (en) * | 2017-08-24 | 2018-01-16 | 成都天奥技术发展有限公司 | EPC3C120F484 types FPGA configurations/test/debugging adapter |
| CN110968004A (en) * | 2019-12-10 | 2020-04-07 | 思尔芯(上海)信息科技有限公司 | Cable test system and method based on FPGA prototype verification development board |
| CN111443307A (en) * | 2020-03-31 | 2020-07-24 | 四川九洲电器集团有限责任公司 | Detection method and detection system of signal processing unit |
| CN113376514A (en) * | 2021-06-09 | 2021-09-10 | 深圳米飞泰克科技有限公司 | FPGA chip testing method, device, system and storage medium |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104866401A (en) * | 2015-05-29 | 2015-08-26 | 福州瑞芯微电子有限公司 | Method and apparatus for obtaining on-chip signal |
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| CN110968004A (en) * | 2019-12-10 | 2020-04-07 | 思尔芯(上海)信息科技有限公司 | Cable test system and method based on FPGA prototype verification development board |
| CN110968004B (en) * | 2019-12-10 | 2021-07-16 | 上海国微思尔芯技术股份有限公司 | Cable test system based on FPGA prototype verification development board |
| CN111443307A (en) * | 2020-03-31 | 2020-07-24 | 四川九洲电器集团有限责任公司 | Detection method and detection system of signal processing unit |
| CN113376514A (en) * | 2021-06-09 | 2021-09-10 | 深圳米飞泰克科技有限公司 | FPGA chip testing method, device, system and storage medium |
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Application publication date: 20130612 |